WINBOND W83792G

W83792AD/D
W83792AG/G
Winbond
H/W Monitoring IC
(CSB Version)
Date :2006 Apr. Revision: 0.9
W83792AD/AG/D/G
W83792AD/D
Data Sheet Revision History
PAGES
DATES
VERSION
WEB
VERSION
MAIN CONTENTS
1
Aug-27-2003
N/A
Move Low Bit I/II to AEh and AFh
2
Aug-27-2003
N/A
Add Description of ASF Severity/Offset
3
Sep-12-2003
0.6
N/A
Update register
4
70-72
Sep-16-2003
0.6.1.
N/A
Update Application circuit
5
12-34
Nov-06-2003
0.7
N/A
Add the part of “Function Description”
6
Jan-05-2004
0.82
N/A
Combining with W83792D and W83792AD
in one datasheet.
Move Low Bit I/II to 3Eh and 3Fh
7
Dec-13-2004
0.83
N/A
Add description on Voltage translation.
8
11
20
39
45
48
Mar-01-2005
0.85
N/A
5-6
11
20
9
45
Nov-10-2005
0.86
N/A
47
39
88
90-97
-I-
The Deletion of Vin4 4.096V(Voltage mode)
Modify Monitor negative voltage
Update voltage convert formula
Modify Device Version ID 13h for C version.
Modify Temperature Offset Attribute R/W
Modify the W83792AD/D pin outputs define
for BSA version. PIN25 and PIN26 pins are
High active for Thermtrip. PIN35 is
VCOREB/VIN4.
Modify the PIN35 descriptions. VCOREB
input detect range is 0~2.048V and Vin4 is
0~4.096V. Added the PIN37 VREF
reference voltage is equal to 3.6V.
Modify the monitor the negative voltage for
VREF equals 3.6V.
Modify Device Version ID 11h for B version
CR [49h] and Pin control register. CR [4Bh]
bit7
Modify Diode Selection Register CR[59h]
power on value.
Modify Low Bit I/II to AEh and AFh. The
voltage Calculation with Low Bit I/II to AEh
and AFh
Modify top marking for the BSA version.
Updated application circuits.
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
W83792AD/D Data Sheet Revision History, continued
PAGES
DATES
VERSION
WEB
VERSION
MAIN CONTENTS
N/A
Modify the W83792AD/D pin outputs define
for CSB version. PIN25 and PIN26 pins are
low active for Thermtrip. PIN35 is
VCOREB.
Modify the PIN35 descriptions. VCOREB
input detect range is 0~2.048V and Vin4 is
deleted.
Added the PIN37 VREF description.
Reference voltage is equal to 2.048V.
Modify Device Version ID 13h for C version.
Modify Low Bit I/II to 3Eh and 3Fh.
Updated application circuits.
Add Pb-free package
5~6
10
10
10
Apr-26-2006
0.9
40
35
83-90
- II -
W83792AD/AG/D/G
Table of Contents1.
GENERAL DESCRIPTION .............................................................................................................. 1
2.
FEATURES...................................................................................................................................... 2
2.1
VCORE Monitoring Items ...................................................................................................... 2
2.2
Monitoring Items .................................................................................................................... 2
2.3
Address Resolution Protocol (ARP) and Alert-Standard Format (ASF 2.0).......................... 2
2.4
Actions Enabling.................................................................................................................... 2
2.5
General.................................................................................................................................. 2
2.6
Package................................................................................................................................. 3
3.
KEY SPECIFICAITON ..................................................................................................................... 3
4.
BLOCK DIAGRAM........................................................................................................................... 4
5.
PIN CONFIGURATION.................................................................................................................... 5
6.
7.
5.1
W83792AD/AG ...................................................................................................................... 5
5.2
W83792D/G........................................................................................................................... 6
PIN DESCRIPTION ......................................................................................................................... 7
6.1
Pin Type Description ............................................................................................................. 7
6.2
Pin Description List................................................................................................................ 7
FUNCTION DECRIPPTION........................................................................................................... 12
7.1
General Description............................................................................................................. 12
7.2
Access Interface .................................................................................................................. 12
7.3
The first serial bus access timing ........................................................................................ 12
7.4
Address Resolution Protocol (ARP) Introduction ................................................................ 13
7.5
ASF (Alert Standard Format) Introduction........................................................................... 15
7.5.1
7.6
7.7
Platform Event Trap (PET) ...................................................................................................16
Analog Inputs....................................................................................................................... 18
7.6.1
Monitor over 4.096V voltage:................................................................................................18
7.6.2
Monitor negative voltage: .....................................................................................................19
FAN Speed Count and FAN Speed Control ........................................................................ 20
7.7.1
Fan speed count...................................................................................................................20
7.7.2
Fan speed control.................................................................................................................21
7.7.3
Smart FanTM I Control .........................................................................................................23
7.7.4
Smart FanTM II Control ........................................................................................................24
7.7.5
SMI# interrupt for W83792D/G Voltage ................................................................................26
7.7.6
SMI# interrupt for W83792D/G Fan......................................................................................26
7.7.7
SMI# interrupt for W83792D/G temperature sensor 1/2/3 ....................................................26
7.7.8
Over-Temperature (OVT#) for W83792D temperature sensor 1/2/3 ....................................27
- III -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
8.
CONTROL AND STATUS REGISTER.......................................................................................... 29
8.1
Watch Dog Timer Registers --- Index 01h-04h ................................................................... 29
8.2
VRM Tolerance Registers ⎯ Index 12h-13h (Bank 0)........................................................ 30
8.3
VID Control/Status Registers ⎯ Index 14h-18h (Bank 0) ................................................... 31
8.4
GPIO Control/Status Register ⎯ Index 1A~1Eh (Bank 0) .................................................. 33
8.5
VRM Output Control ---- Index 1F(Bank 0).......................................................................... 34
8.6
Value RAM ⎯ Index 20h- 2Ah AEh AFh (Bank 0) .............................................................. 35
8.7
Limit RAM ⎯ Index 2Bh- 2Dh (Bank 0)............................................................................... 36
8.8
Configuration Register ⎯ Index 40h (Bank 0)..................................................................... 37
8.9
Interrupt Status Registers ⎯ Index 41h 42h 9Bh(Bank 0) .................................................. 38
8.10 SMI#/IRQ Mask Registers ⎯ Index 43h~45h 9Ch 9Dh(Bank 0) ........................................ 38
8.11 Realtime Status Registers ⎯ Index A9h~ABh(Bank 0) ...................................................... 39
8.12 Serial Bus Address Registers ⎯ Index 48h 4A(Bank 0) ..................................................... 39
8.13 ID, Bank Select Registers-- Index 49h 4Eh 4Fh 58h (Bank 0)............................................ 40
8.14 Pin Control Register -- Index4Bh (Bank 0) .......................................................................... 40
8.15 SMI#/OVT# Property Select -- Index 4Ch (Bank 0) ............................................................ 41
8.16 Diode Selection Register -- Index 59h (Bank 0)................................................................. 43
8.17 FANIN Divisor Control Registers -- Index 47h 5Bh 5Ch(Bank 0)....................................... 44
8.18 VBAT Monitor Control Register -- Index 5Dh (Bank 0) ....................................................... 45
8.19 FAN Pre-Scale Registers-- Index 80h 82h 93h A0h A1h A2h(Bank 0).............................. 46
8.20 FAN Duty Cycle Select Register--81h 83h 94h A3h A4h A5h(Bank 0)............................... 47
8.21 FAN 1/2 Configuration Register-- Index 84h (Bank 0) ........................................................ 49
8.22 Fan 1 Target Temperature Registers -- Index 85h 86h 96h(Bank 0).................................. 49
8.23 Tolerance of Fan1/2 Target Temperature Register -- Index 87h 97h(Bank0).................... 50
8.24 Fan Stop/Start Duty Cycle/DC Level Registers -- Index 88h 89h 98h(Bank 0)................... 51
8.25 Fan Stop Time Register -- Index 8Ch 8Dh 9Ah(Bank 0)..................................................... 51
8.26 Fan Step Down/Up Time Register -- Index 8Eh 8Fh(Bank 0) ............................................. 52
8.27 Fan 1/2/3 Smart Fan II Temperature/ Duty Cycle setups -- Index E0h~EBh 5Fh(Bank 0) 52
8.28 Value RAM 2⎯ Index B0h B1h B8h ~ BAh (BANK 0) ........................................................ 54
8.29 Limit RAM 2--- Index B4h~B7h BBh~BDh (BANK0) ........................................................... 55
8.30 Temperature Sensor 2 (First LM75) .................................................................................... 55
8.31 Temperature (High Byte) Register - Index C0h (Bank 0) .................................................... 56
8.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index C1h (Bank 0)................ 56
8.33 Temperature Sensor 2 Configuration Register - Index C2h (Bank 0) ................................. 56
8.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index C3h (Bank 0)................... 56
8.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index C4h (Bank 0) ................... 56
- IV -
W83792AD/AG/D/G
8.36 Temperature Sensor 2 Over-temperature (High Byte) Register -Index C5h (Bank 0) ........ 57
8.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index C6h(Bank 0)......... 57
8.38 Temperature Sensor 3 (Second LM75)............................................................................... 57
8.39 Temperature Sensor 3 Hysteresis (High Byte) Register - Index CBh (Bank 0) .................. 57
8.40 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index CCh (Bank 0)................... 58
8.41 Temperature Sensor 3 Over-temperature (High Byte) Register - Index CDh (Bank 0) ...... 58
8.42 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index CEh(Bank 0) ........ 58
9.
ARP (ADDRESS RESOLUTION PROTOCOL) REGISTERS...................................................... 59
9.1
Unique Device Identifier (UDID) -- 20h-2Fh (Bank 1) ......................................................... 59
10. ASF SENSOR ENVIRONMENTAL EVENT .................................................................................. 61
10.1 Temperature: Get Event Data message.............................................................................. 61
10.2 Voltage: Get Event Data message ...................................................................................... 65
10.3 Fan: Get Event Data message ............................................................................................ 67
10.4 Case Intrusion: Get Event Data message ........................................................................... 70
10.5 Thermal Trip: Get Event Data message.............................................................................. 71
10.6 ASF Response Registers -- 40h-7Fh (Bank 1) ................................................................... 73
10.6.1
ASF Critical/non-critical Temperature Registers:..................................................................73
10.6.2
Sensor device: (SMBus Address, Read/Write).....................................................................73
10.6.3
Relative Entity ID Table ........................................................................................................73
10.6.4
Entity Instance Register........................................................................................................75
10.6.5
Remote Control Configuration Registers ..............................................................................76
11. ELECTRICAL CHARACTERISTICS ............................................................................................. 77
11.1 Absolute Maximum Ratings................................................................................................. 77
11.2 DC Characteristics............................................................................................................... 77
11.3 AC Characteristics............................................................................................................... 79
11.3.1
Serial Bus Timing Diagram...................................................................................................79
11.3.2
VID Input Skew.....................................................................................................................79
12. THE TOP MARKING ..................................................................................................................... 80
13. ACKAGE SPECIFICATION ........................................................................................................... 82
14. W83792AD/AG APPLICATION CIRCUIT...................................................................................... 83
15. W83792D/G APPLICATION CIRCUIT .......................................................................................... 87
-V-
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
1. GENERAL DESCRIPTION
W83792AD/AG and W8392D/G are two parts support single and dual CPU application, the former is
for single CPU application which provides 1 set thermal trip and 1 set of VID controlling; the latter is for
dual CPU application which provides dual CPU VID controlling and 2 sets of thermal trip. Other
functions are all the same without difference except thermal trip and VID controlling numbers.
W83792D/G is an evolving version of the W83791D --- Winbond's most popular hardware status
monitoring IC. Besides the conventional functions of W83791D, W83792D/G uniquely provides
several innovative features such as support dual CPU VID controlling, VRM9.0 and VRD10.0
specifications supported, ASF 2.0 specification compliant, SMBus 2.0 ARP command compatible, 2
sets of Thermal trip, 12 VID control, 6 sets of Smart fan TM, VID table selection trapping.
Conventionally, W83792D/G can be used to monitor several critical hardware parameters of the
system, including power supply voltages, fan speeds, and temperatures, which are very important for
a high-end computer system, such as server, workstation…etc, working very stably and efficiently.
A 10-bit analog-to-digital converter (ADC) was built inside W83792D/G. W83792D/G can
simultaneously monitor 9 analog voltage inputs (including power VDD/5VSB monitoring), 6 fan
tachometer inputs, 3 remote temperatures, and Watch Dog Timer function. The sense of remote
temperature can be performed by thermistors, or directly from IntelTM CPU with thermal diode output.
W83792D/G provides 6 PWM (pulse width modulation)/DC fan output modes for smart fan control - S
Thermal CruiseTM T mode and S Smart FanTM II T mode. Under S Thermal CruiseTM T mode,
temperatures of CPU and the system can be maintained within specific programmable ranges under
the hardware control. As Smart Fan TM II, which provides 4 sets of temperatures point each could
control fan’s duty cycle, depends on this construction, fan could be operated at the lowest possible
speed so that the acoustic noise could be avoided. As for warning mechanism, W83792D/G provides
SMI#, OVT#, IRQ signals for system protection events.
Additionally, 12 VID inputs are provided to read 2 sets of VID for CPU (i.e. PentiumTM III/4). These VID
inputs provide the information of Vcore voltage that CPU expects. W83792D/G also has 2 specific pins
to provide selectable address setting for application of multiple devices (up to 4 devices) wired through
I2C interface.
W83792D/G can uniquely serve as an ASF sensor to respond to ASF master’s request for the
implementation of network management in OS-absent status. Through W83792D/G’s compliance with
ASF2.0 sensor specification, network server is able to monitor the environmental status of each client
in OS-absent state by PET (Platform Event Trip) frame values returned from W83792D/G, such as
temperatures, voltages, fan speed, thermal trip, and case open. Moreover, W83792D/G supports
SMBus 2.0 ARP command to solve the problem of address conflicts by dynamically assigning a new
unique address for W83792D/G ASF Function after W83792D/G’s UDID is sent.
Through the application software or BIOS, the users can read all the monitored parameters of the
system from time to time. A pop-up warning can also be activated when the monitored item is out of
the proper/preset range. The application software could be Winbond's Hardware DoctorTM, IntelTM
LDCM (LanDesk Client Management), or other management application software. Besides, the users
can set up the upper and lower limits (alarm thresholds) of these monitored parameters and activate
one programmable and maskable interrupts.
-1-
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
2. FEATURES
2.1
VCORE Monitoring Items
y
Support dual CPU VID reading.
y
VRM9.0 / VRD10.0 compliant to monitor dual CPU voltage.
y
2 sets of thermal trip latch mechanism to protect CPU from over temperature.
2.2
Monitoring Items
y
Monitoring 9 voltage inputs.
y
6 DC / PWM Fan outputs for fan speed control and 6 Fan speed inputs for monitoring --- Total up
to 6 sets of fan speed monitoring and controlling
y
3 temperature inputs from remote thermistor and PentiumTM II/III/4 (Deschutes) thermal diode
output
y
6 sets Smart FanTM could control the most fitting speed automatically by temperature.
y
Case open detection input
y
2 sets of CPU thermal management:2 Thermal Trip signals latch up and generate VRM_EN signal
to PWM for removing CPU power.
y
Programmable hysteresis and setting points (alarm thresholds) for all monitored items
2.3
Address Resolution Protocol (ARP) and Alert-Standard Format (ASF 2.0)
y
Support System Management Bus (SMBus) version 2.0 specification
y
Comply with hardware sensor slave ARP (Address Resolution Protocol)
y
Response ASF 2.0 command --- Get Event Data, Get Event Status, Device Type Poll
y
Comply with ASF 2.0 sensors (Power on/off remote control, Monitoring fan speed, voltage,
temperature, thermal trip and case open)
y
Support Remote Control subset: Remote Power-on/ Power-off/ Reset.
2.4
Actions Enabling
y
Issue SMI#, OVT#, IRQ signals to activate system protection
y
Warning signal pop-up in application.
2.5
General
y
I2C serial bus interface
y
Support 2 sets of 6bit VID monitoring for dual processors application
y
Watch Dog Timer function with pin: RESET#, SYSRST_IN.
y
16 GPIOs
y
2 pins (A0, A1) to provide selectable address setting for application of multiple devices (up to 4
devices) wired through I2C interface
-2-
W83792AD/AG/D/G
y
Winbond hardware monitoring application software (Hardware DoctorTM) support, for both
Windows 95/98/2000/XP and Windows NT 4.0/5.0/2000
y
5V VSB operation
2.6
y
Package
48-pin LQFP
3. KEY SPECIFICAITON
y
Voltage monitoring accuracy
±1% (Max)
y
Intel VRM 9.x/VRD10.0 Voltage monitoring accuracy
±1% (Max)
y
Temperature Sensor Accuracy
Remote Diode Sensor Accuracy
± 3°C(Max)
Resolution
0.5 ℃
y
Supply Voltage
5V
y
Operating Supply Current
5 mA typ.
y
ADC Resolution
10 Bits
-3-
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
4. BLOCK DIAGRAM
ADDR 1:2
VID A 0:5
VID register * 2
SDA
SCL
SMBus Address
Selection
Serial Bus
Interface
SMBus Control
ARP Control
ASF2.0
Commend
Decoder
VID B 0:5
FAN Mode
FAN IN/OUT 1:6
Smart FanTM II
Thermal Cruise
W83792D
Manual Mode
Control Logic & Register
THERMALTRIP# 1:2
WDTRST#
SYSRTIN#
GPIOs
Thermal Protection
Watch Dog Timer
10 Bits ADC
Band Gap
Reference
GPIO
Temp. Sensor
Voltage Sensor
CLK
VTIN 1:3
-4-
VIN 1:7 VDD
VRM_EN
PWRBTN#
VID 90_10
CASEOPEN
SMI#/IRQ
OVT#
VREF
VBAT
GND
W83792AD/AG/D/G
5. PIN CONFIGURATION
NC
THERMTRIP1 #
VCOREA
VCOREB
VIN0
VIN1
VIN2
VIN3
VBAT
CASEOPEN
VRM_EN
GND
W83792AD/AG
VTIN3
3 3 3 3 3 3 3 2 2 2 2 2
6 5 4 3 2 1 0 9 8 7 6 5
37
24
38
23
PWRBTN#
VTIN2
39
22
SDA
21
SCL
VREF
+5VSB
VTIN1
40
SMI# / IRQ
41
20
FANIN1
OVT#
42
19
FANIN2
FAN_OUT4 / GPIOA0
43
FANIN4 / GPIOA1
44
FAN_OUT5 / GPIOA2
45
FANIN5 / GPIOA3
46
WDTRST# / FAN_OUT6
SYSRSTIN# / FANIN6
W83792AD
18
FANIN3
17
CLK
16
FAN_OUT1/A0
15
FAN_OUT2/A1
47
14
FAN_OUT3/VID90_10
48
13
1 1 1
1 2 3 4 5 6 7 8 9
0 1 2
Version C
VDD
VIDA0 / GPIOA4
VIDA1 / GPIOA5
VIDA2 / GPIOA6
VIDA3 / GPIOA7
VIDA4 / GPIOB0
VIDA5 / GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
5.1
-5-
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
VRE
F
VTIN
3
VTIN
2
VTIN
1
SMI# / IRQ
VIN3
VBAT
CASEOPEN
VRM_EN / FAN_OUT7
GND
THERMTRIP2
THERMTRIP1/ FAN_IN7
VCOREA
VCOREB / VIN4
VIN0
VIN1
VIN2
W83792D/G
3 3 3 3 3 3 3 2 2 2 2 2
6 5 4 3 2 1 0 9 8 7 6 5
37
24
38
23
39
40
41
22
W83792D
21
20
OVT#
42
19
FAN_OUT4 / GPIOA0
43
18
+5VS
B
PWRBTN#
SDA
SC
L
FANIN
1
FANIN
FANIN4 / GPIOA1
44
17
2
FANIN
3
CLK
FAN_OUT5 / GPIOA2
45
16
FAN_OUT1/A0
FANIN5 / GPIOA3
46
15
FAN_OUT2/A1
WDTRST# / FAN_OUT6
47
14
FAN_OUT3/VID90_10
SYSRSTIN# / FANIN6
48
13
1 1 1
1 2 3 4 5 6 7 8 9
0 1 2
Version C
VIDA0 / GPIOA4
VIDA1 / GPIOA5
VIDA2 / GPIOA6
VIDA3 / GPIOA7
VIDA4 / GPIOB0
VIDA5 / GPIOB1
VIDB0 / GPIOB2
VIDB1 / GPIOB3
VIDB2 / GPIOB4
VIDB3 / GPIOB5
VIDB4 / GPIOB6
VIDB5 / GPIOB7
5.2
-6-
VDD
W83792AD/AG/D/G
6. PIN DESCRIPTION
6.1
6.2
Pin Type Description
I/O12t
TTL level bi-directional pin with 12 mA source-sink capability
I/O12ts
TTL level and schmitt trigger with 12 mA source-sink capability
I/O8ts
TTL level and schmitt trigger with 8 mA source-sink capability
I/O6ts
TTL level and schmitt trigger with 6 mA source-sink capability
I/OD12ts
TTL level and schmitt trigger open drain output with 12 mA sink capability
OUT12
Output pin with 12 mA source-sink capability
OD12
Open-drain output pin with 12 mA sink capability
AOUT
Output pin (Analog)
INt
TTL level input pin
INts
TTL level input pin and schmitt trigger
AIN
Input pin(Analog)
Pin Description List
PIN NAME
PIN
NO.
POWER
PLANE
VIDA0
INts
1
5VSB
GPIOA4
VIDA1
2
5VSB
GPIOA5
VIDA2
3
5VSB
GPIOA6
VIDA3
4
5VSB
GPIOA7
VIDA4
5
GPIOB0
TYPE
5VSB
DESCRIPTION
Voltage Supply readouts bit 0 from CPU A.
12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 1 from CPU A.
I/O D-
I/O D12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 2 from CPU A.
I/O D12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 3 from CPU A.
I/O D12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 4 from CPU A.
I/O D12ts
After programming, this pin can be VID output or
GPIO.
-7-
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Pin Description List, continued
PIN NAME
PIN
NO.
POWER
PLANE
VIDA5
6
5VSB
GPIOB1
VIDB0
7
5VSB
GPIOB2
VIDB1
8
5VSB
GPIOB3
VIDB2
9
5VSB
GPIOB4
VIDB3
10
5VSB
GPIOB5
VIDB4
11
5VSB
GPIOB6
INts
Voltage Supply readouts bit 5 from CPU A. Only used
in VRD10.0.
12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 0 from CPU B.
I/O D-
12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 1 from CPU B.
I/O D-
12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 2 from CPU B.
I/O D-
12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 3 from CPU B.
I/O D-
12ts
After programming, this pin can be VID output or
GPIO.
INts
Voltage Supply readouts bit 4 from CPU B.
I/O D-
I/O DINts
12
5VSB
GPIOB7
I/O D12ts
13
-
FAN_OUT3
14
VID9_10
DESCRIPTION
12ts
VIDB5
VDD
TYPE
After programming, this pin can be VID output or
GPIO.
Voltage Supply readouts bit 5 from CPU B. Only used
in VRD10.0.
After programming, this pin can be VID output or
GPIO.
POWE
R
+5V VDD power. Bypass with the parallel combination
of 10μF (electrolytic or tantalum) and 0.1μF (ceramic)
bypass capacitors.
OUT1 2
Fan speed control PWM/DC output. When the power
of VDD is 0v, this pin will drive logic 0. The power of
this pin is supplied by VSB 5V.
INt s
At 5VSB power on, this pin is used to select Internal
VRM 9 or 10 table. Detect 1, Select VRM9, Detect 0,
selects VRM10.
5VSB
-8-
W83792AD/AG/D/G
Pin Description List, continued
PIN NAME
PIN
NO.
POWER
PLANE
TYPE
DESCRIPTION
OUT12
Fan speed control PWM/DC output. When the power
of VDD is 0v, this pin will drive logic 0. The power of
this pin is supplied by VSB 5V.
A1
INts
I2C device address bit 1 trapping during 5VSB power
on.
FAN_OUT1
I/O12t
Fan speed control PWM/DC output. When the power
of VDD is 0v, this pin will drive logic 0. The power of
this pin is supplied by VSB 5V.
INts
I2C device address bit 0 trapping during 5VSB power
on.
FAN_OUT2
15
16
5VSB
5VSB
A0
CLK
17
VDD
INts
14.318MHz System clock while VCC5V powered up.
FANIN3
18
VDD
INts
0V to +5V amplitude fan tachometer input
FANIN2
19
VDD
INts
0V to +5V amplitude fan tachometer input
FANIN1
20
VDD
INts
0V to +5V amplitude fan tachometer input
SCL
21
5VSB
INts
Serial Bus Clock.
SDA
22
5VSB
I/OD12ts
PWRBTN#
23
5VSB
OD12
+5VSB
24
-
25
5VSB
Power Button output for enable/disable power supply.
This pin is power for W83792D/G. Bypass with the
POWER parallel combination of 10μF (electrolytic or tantalum)
and 0.1μF (ceramic) bypass capacitors.
THERMTRIP1#
Thermal Trip signal from CPU A. Low Active.
INts
FANIN7
THERMTRIP2#
Serial Bus bi-directional data.
0~+5V FANIN 7 tachometer.
26
5VSB
INts
Thermal Trip signal from CPU B. Low Active.
-9-
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Pin Description List, continued
PIN NAME
PIN
NO.
POWER
PLANE
GND
27
-
VRM_EN
28
CASEOPEN
29
VBAT
VBAT
30
-
VIN0
DESCRIPTION
POWER System Ground.
OD12
Any assertion of thermal trip after VDD power good
will disable Voltage Regulator Module.
OUT12
Fan speed control PWM output. By default it’s high.
The power of this pin is supplied by VSB 5V.
INts
CASE OPEN detection. An active high input from an
external device when case is Intruded. This signal
can be latched in external circuit which power is
supplied by VBAT, even if W83792D is power off.
5VSB
FAN_OUT7
VIN3-
TYPE
VBAT
supplies
power
for
CASEOPEN,
POWER THERMALTRIP. Besides, it is also a voltage monitor
channel.
31
-
AIN
0V to 4.096V Analog Voltage Monitor Inputs.
34
VCOREB
35
AIN
CPU B Core Voltage Input. Detect range is 0~2.048V.
VCOREA
36
AIN
CPU A Core Voltage Input. Detect range is 0~2.048V.
VREF
37
AOUT
Reference voltage and is equal to 2.048V
Thermistor 3 terminal input.(Default).
VTIN3
38
AIN
PentiumTM 4 diode 3 input.
This multi-functional pin is programmable.
Thermistor 2 terminal input. (Default).
VTIN2
39
AIN
PentiumTM 4 diode 2 inputs.
This multi-functional pin is programmable.
Thermistor 1 terminal input. (Default).
VTIN1
40
AIN
PentiumTM 4 diode 1 inputs.
This multi-functional pin is programmable.
- 10 -
W83792AD/AG/D/G
Pin Description List, continued
PIN NAME
PIN
NO.
POWER
PLANE
IRQ /
TYPE
OUT12
41
DESCRIPTION
Interrupt request.
VDD
SMI#
OD12
System Management Interrupt (open drain).
OD12
Over temperature Shutdown Output for temperature
sensor 1-3.
OUT12
Fan speed control PWM/DC output. When the power
of VDD is 0v, this pin will drive logic 0. The power of
this pin is supplied by VSB 5V.
I/O12ts
After programming, this pin can be GPIO.
INts
0V to +5V amplitude fan tachometer input
GPIOA1
I/O12ts
After programming, this pin can be GPIO.
FAN_OUT5
OUT12
Fan speed control PWM output. When the power of
VDD is 0v, this pin will drive logic 0. The power of this
pin is supplied by VSB 5V.
I/O12ts
After programming, this pin can be GPIO.
INts
0V to +5V amplitude fan tachometer input
GPIOA3
I/O12ts
After programming, this pin can be GPIO.
FAN_OUT6
OUT12
Fan speed control PWM output. By default it’s high.
The power of this pin is supplied by VSB 5V.
OD12
Low active System RESET. If triggered, this pin will
send out 100ms low pulse for system reset.
OVT#
42
VDD
FAN_OUT4
43
5VSB
GPIOA0
FANIN4
44
45
5VSB
5VSB
GPIOA2
FANIN5
46
47
5VSB
5VSB
RESET#
FANIN6
48
SYSRSTIN#
INts
0V to +5V amplitude fan tachometer input
INts
System reset input, used to control WDT.
5VSB
- 11 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
7. FUNCTION DECRIPPTION
7.1
General Description
The W83792D/G provides 9 analog voltage inputs, 7 fan speed inputs and output controls which
support both of PWM (Pulse Width Modulation) control and DC (Direct Current) fan control, all of them
are implemented with Smart FANTM I and Smart FANTM II. 3 sets of thermal inputs for remote
thermistor or PentiumTM 4 thermal diode outputs, and case open detection also supported in
W83792D/G. Further more, W83792D/G provides several innovative and practical functions to make
the whole system manage more efficiently and compliant with future trend of network management,
such as ASF2.0 sensor compliant, which could remote Power on/off control the system, report the
status of thermal trip, fan, and temperature limitation. Also, it is SMBus 2.0 ARP command compatible.
VID table could be selected by hardware trapping for VRM9.0 and VRD 10 specifications. 2 sets of 6
bits of VID input/output control for dual processors and 2 sets of thermal Trip input for disable VRM
module, and for the more, once the monitoring function of W83792D/G is enabled, the watch dog will
monitor every function and store the values to registers for comparison with preset ranges. If the
monitoring value exceeds the limit value, the interrupt status will be set to 1 and W83792D/G will issue
interrupt signals such as SMI# and IRQ if they are not masked off. W83792D/G also provides software
and hardware Watch Dog Timer to avoid system hang on.
7.2
Access Interface
The W83792D/G provides I2C Serial Bus for microprocessor to read/write internal registers. In the
W83792D/G, there are three serial bus addresses. Through the fi
The first serial bus address of W83792D/G has 2 hardware setting bits set by Pin15-16. The address
is 01011[pin15][pin16]X. Hence, the content of CR [48h] would be 00101110 if pin15=1 and pin16=0.
The read/write of the CPUT1/CPUT2 temperature sensor registers can be implemented through the
second address (defined at CR [4Ah] bit2-0 10011[IA1][IA0]X) and the third address (defined at
CR[4Ah] bit6-4 10010[IA1][IA0]X).rst address defined at CR[48h], all the registers can be read and
written.
7.3
The first serial bus access timing
(a) Serial bus writes to internal address register followed by the data byte
0
7
8
0
7
8
SCL
0
SDA
Start By
Master
1
0
1
1
0
1
R/W
D7
D6
Ack
by
792D
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
792D
Frame 2
Internal Index Register Byte
0
7
8
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
Frame 3
Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
- 12 -
D0
Ack
by
792D
784R
Stop
by
Master
W83792AD/AG/D/G
(b) Serial bus read from a register
0
7
8
0
7
8
SCL
0
SDA
1
Start By
Master
0
1
1
0
1
R/W
D7
D6
Ack
by
792D
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
792D
Frame 2
Internal Index Register Byte
0
0
0
Repeat
start
by
Master
7
1
0
1
1
0
1
8
R/W
0
D7
Ack
by
792D
Frame 3
Serial Bus Address Byte
7
D6
D5
D4
D3
D2
D1
8
D0
Nak
by
Master
Frame 4
Data Byte
Stop by
Master
0
Figure 2. Serial Bus Read from Internal Address Register
7.4
Address Resolution Protocol (ARP) Introduction
As the W8792D/G is a slave device existing on the System Management Bus, it must have a unique
address to prevent itself from conflicting with the other devices existing on the same bus. In order to
solve the problem of address conflicts, SMBus version 2.0 introduces the concept of dynamically
assigned address called Address Resolution Protocol (ARP). By such mechanism, each device
existing on the SMBus will be given with an unique slave address if it is a ARP-capable device. Thus,
to meet the new spec, W83792D/G uniquely provides ARP compliant function to acquire an unique
slave address.
The typical process of ARP contains several steps, including Prepare to ARP, Reset Device, Get
UDID, Assign Address, and so on. Whenever the slave device accepts the command of ARP master,
it must reply an Acknowledgement to the ARP master, thus the ARP master is able to carry on the
next step. In order to provide a mechanism to isolate device for the purpose of address assignment,
each device must implement a unique device identifier (UDID). The UDID is a 128-bit number
comprised of several field, including Device Capabilities, Version Revision, Vendor ID, Device ID,
Interface, Subsystem Vendor ID, Subsystem Device ID, and Vendor Specific ID. After the UDID of the
device is sent to the ARP master, the ARP master will then assign an address not in the Used
Address Pool to the device.
Generally speaking, there are eleven possible commands to read /write the data of SMBus device,
and a slave device may use any or all of the eleven protocols to communicate. These protocols are
Quick Command, Send Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read word, Process
Call, Block Write, and Block Write-Block Read Process Call. W83792D/G itself supports the Block
Write-Block Read Process with PEC to communicate with ARP Master. Following is a description of
the SMBus packet protocol diagrams element key. Not all protocol elements will be present in every
command, that is, not all packets are required to include the Packet Error Code.
- 13 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
1-bit
7
1
1
S
Slave Address
Wr A
8
1
8
1
1-bit
Command
A
PEC
A
P
S
Start Condition
Sr
Repeated Start Condition
Rd
Read (bit value of 1)
Wr
Write (bit value of 0)
A
Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK)
P
Stop Condition
PEC
Packet Error Code
Master-to-Slave
Slave-to-Master
Relative command list:
SLAVE ADDRESS
COMMAND
DESCRIPTION
C2h
01h
Prepare to ARP
C2h
02h
Reset device (general)
C2h
03h
Get UDID (general)
C2h
04h
Assign address
C2h
Slave_Addr | 1
Direct Get UDID
C2h
Slave_Addr | 0
Direct Reset
C2h
05h-1Fh
Reserved.
Following is an example of the Block Write-Block Read Process Call. The Block Write-Block Read
Process Call is a two-part message. It begins with a salve address and a write condition. After the
command code the host issues a write count M that describes how many more bytes will be written in
the first part of the message. The second part of the message is a block of read data beginning with a
repeat start condition followed by the salve address and a Read Bit. The next read byte count N
indicates how many more data will be read in the second part of the message. Note that the combined
data payload must not exceed 32bytes. Besides, W83792D/G also provides packet error code (PEC)
to ensure the accuracy during data transmission.
- 14 -
W83792AD/AG/D/G
1
7
1
1
8
S
Slave
Address
Wr
A
Command Code A
8
1
8
1
Byte Count=M
A
Data Byte 1
A
8
1
…
8
1
Data Byte 2
A
…
Data Byte M
A
1
7
1
Sr
Slave Address Rd A
8
7.5
1
1
8
1
1
…
8
1
Data Byte 2 A
…
Data Byte N A
…
8
Byte Count=N A
1
Data Byte 1 A
8
…
1
1
PEC A
P
1
…
ASF (Alert Standard Format) Introduction
In order to implement network management in OS-absent, W83792D/G provides ASF Response
Registers to meet ASF sensor spec. As a result, the network server is able to monitor several
environmental status of the client in OS-absent by PET frame values returned from W83792D/G,
including temperature, voltage, fan speed, and case open. In below is the ASF diagram:
Alert Message
LAN on Card
Management
Server
Polling
(PET Subset)
Motherboard
PCI Bus
SMBus
LAN on Board
Chipset
792D
Slave
Figure 3. ASF Block Diagram
- 15 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
7.5.1 Platform Event Trap (PET)
PET is the ASF transmit protocol used to provide common fields for trap regardless of trap source.
The variable bindings fields in a PET frame contain the system and sensor information for an event,
such as event sensor type, event type, event offset, event source type, sensor device, sensor number,
entity ID, entity instance, event status index, event status, and event severity. Each field has its
definition and is described in the following table.
PET VARIABLE BINDING
FIELD
DESCRIPTION
Event Sensor Type
The Event Sensor Type field indicates what types of events the
sensor is monitoring. E.g. temperature, voltage, fan, etc.
Event Type
The Event Type indicates what type of transition/state change
triggered the trap.
Event Offset
The Event Offset indicates which particular event occurred for a given
Even Type.
Event source Type
The Event Source Type describes the originator of the event. It is
ASF2.0(68h) for all PET frames defined by this specification.
Sensor Device
The Sensor Device is the SMBus address of the sensor that caused
the event for the PET frame.
Sensor Number
The Sensor Number is used to identify a given instance of a sensor
relative to the Sensor Device.
Entity ID
The Entity ID indicates the platform entity the event is associated with.
E.g. processor, system board, etc.
Entity Instance
The Entity Instance indicates which instance of the Entity the event is
for. E.g. processor 1 or processor 2.
Event Status Index
The Event Status Index identifies a unique event monitored by the
ASF-sensor. It is zero-based, sequential, continuous, and ranging
form 0-37h.
Event Status
The Event Status indicates the event state of the ASF-sensor device
associated with the message’s Event Status Index.
Event Severity
The Event Severity gives the management station an indication of the
severity of the event in the PET frame. Typical values are Monitor
(0x01), Non Critical (0x08), or Critical Condition (0x10).
- 16 -
W83792AD/AG/D/G
Following is the illustration of ASF SMBus command for Get Event Data.
1
7
1
1
8
1
8
1
S
Slave Address
Wr
A
Command
A
Wr Byte Count
A
ASF-sensor
Address
0
0
Sensor Device
0
0000 0100
0
…
0000 0001
8
1
8
1
8
1
8
1
Wr Data 1
A
Wr Data 2
A
Wr Data 3
A
Wr Data 4
A …
Sub Command
0
Version
0
Status 0
Reserved
0
Number
Event
Index
0001 0000
00ii iiii
Get Event Data
0001 0001
0000 0000
1
7
1
1
8
1
Sr
Slave Address
R
A
Rd Byte Count
A
ASF-sensor Address
1
0
0000 1010 to0000 1111
0
1
8
1
8
1
8
1
A
Rd Data 1
A
Rd Data 2
A
Rd Data 3
A
0
Status
0
Event Sensor Type 0
Event Type
0
8
1
8
1
8
1
8
1
Rd Data 4
A
Rd Data 5
A
Rd Data 6
A
Rd Data 7
A
Sensor Device
0
Event Offset 0
Event Source 0
Type
Event Severity 0
8
1
8
1
8
1
Rd Data 8
A
Rd Data 9
A
Rd Data 10
A
Sensor
Number
0
Entity
0
Entity Instance
0
…
1
1
PEC
A
P
- 17 -
…
…
…
8
From zero to five bytes of Event Data [data dependent]
…
1
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
7.6
Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 10-bit ADC has a 4mv LSB.
Actually, the application of the PC monitoring would most often be connected to power supply. The
CPU V-core voltage, +3.3V and battery voltage can directly connect to these analog inputs. The –
5V, –12V and +12V inputs should be reduced a factor with external resistors to meet the input range.
As Figure 4 shows.
*PS : VCORE channel resolution = 2mv VIN0-4 channel resolution = 4mv
Pin 36
Pin 35
VcoreA
Positive Inputs
V1
R1
Pin 34
Pin 30
12VIN
Pin 32
10-bit ADC
with
4mV LSB
R2
Positive Input
Negative Input
VcoreB
+3.3VIN
VBAT
R5
V3
V4
N12VIN
R7
Pin 31
Pin 33
N5VIN
R8
R
10K, 1%
VREF
VTIN3
Typical Thermister Connection
VTIN2
R
THM
10K, 25 C
VTIN1
R6
Pin 37
Pin 38
Pin 39
Pin 40
**The Connections of VTIN1 and VTIN2
are same as VTIN3
Figure 4.
7.6.1
Monitor over 4.096V voltage:
The input voltage +12VIN can be expressed as the following equation.
12VIN = V1 ×
R2
R1 + R2
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input
voltage V1 is 12V. The node voltage of +12VIN should be subject to under 4.096V for the maximum
input range of the 8-bit ADC. The pin 13 and pin 29 are discretely connected to the power supply +5V
and 5VSB . There are two functions in these pins with 5V. The first function is to supply internal analog
power in the W83792D and the second one is that these voltages are all connected to internal serial
resistors to monitor the +5V and 5VSB voltage.
- 18 -
W83792AD/AG/D/G
7.6.2 Monitor negative voltage:
The negative voltage should be connected to two series resistors and a positive voltage VREF (equal
to 2.048V). In the Figure 11, the voltage V3 and V4 are two negative voltages and are -12V and -5V
respectively. The voltage V3 is connected to two serial resistors as well as another positive terminal
VREF. Therefore, the voltage node N12VIN would be a positive voltage if the scale of the two serial
resistors are carefully selected. It is recommended from Winbond that the scale of the two serial
resistors are R5=232K ohms and R6=10K ohm. The input voltage of node -12VIN can be calculated
by the following equation.
N12VIN = (VREF + V5 ) × (
232 KΩ
) + V5
232 KΩ + 10 KΩ
where VREF is equal to 2.048V.
If the V5 is equal to -12V then the voltage is equal to 1.467V and the converted hexdecimal data is set
to 60h by the 8-bit ADC with 8mV-LSB.This monitored value should be converted to the real negative
voltage and the express equation is shown as follows.
V5 =
Where
β
N12VIN − VREF × β
1− β
is 232K/(232K+10K). If the N2VIN is 1.467 then the V5 is approximately equal to -12V.
The other negative voltage input V6 (approximate -5V) can also be evaluated by the similar method
and the serial resistors can be R7=120K ohms and R8=10K ohms by the Winbond recommended. The
expression equation of V6 With -5V voltage is shown as follows.
V6 =
N 5VIN − VREF × γ
1− γ
Where the γ is set to 120K/(120K+10K). If the monitored ADC value in the N5VIN channel is 1.505,
VREF=2.048V and the parameter γ is 0.923, then the negative voltage of V6 can be evaluated -5V.
- 19 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
7.7
FAN Speed Count and FAN Speed Control
7.7.1 Fan speed count
W83792D/G support 6 sets of fan counting. Fan inputs are provided for signals from fans equipped
with tachometer outputs. The level of these signals should be set to TTL level, and the maximum input
voltage should not be over +5.5V. If the input signals from the tachometer outputs are over the VCC,
the external trimming circuit should be added to reduce the voltage to meet the input specification. The
normal circuit and trimming circuits are shown as Figure 8.
Determine the fan counter according to:
1.35 × 10 6
Count =
RPM × Divisor
In other words, if the fan speed counter has been read from register CR [28], CR [29], CR [2A], CR
[B8], CR [B9] or CR [BA] , then the fan speed can be evaluated by the following equation.
RPM =
1.35 × 10 6
Count × Divisor
The default divisor is 2 and defined at CR47, CR5B, and CR5C which are three bits for divisor. This
provides very low speed fan counter such as power supply fan. The followed table is an example for
the relation of divisor, RPM, and count.
DIVISOR
NOMINAL RPM
TIME PER
REVOLUTION
COUNTS
1
8800
6.82 ms
153
2 (default)
4400
13.64 ms
153
4
2200
27.27 ms
153
8
1100
54.54 ms
153
16
550
109.08 ms
153
32
275
218.16 ms
153
64
137
436.32 ms
153
128
68
872.64 ms
153
Table 2.
- 20 -
W83792AD/AG/D/G
+12V
+12V
+5V
Pull-up resister
4.7K Ohms
Pull-up resister
4.7K Ohms
+12V
+12V
FAN Out
Fan Input
Pin 18/19/20
W83792D
FAN
Connector
Figure 5-1. Fan with Tach Pull-Up to +5V
Pin 18/19/20
W83792D
Figure 5-2. Fan with Tach Pull-Up to +12V, or Totem-Pole
Output and Register Attenuator
+12V
Pull-up resister < 1K
or totem-pole output
Pull-up resister
> 1K
+12V
+12V
FAN
Connector
10K
FAN
Connector
+12V
GND
Fan Input
GND
GND
FAN Out
14K~39K
FAN Out
Fan Input
Pin 18/19/20
> 1K
FAN Out
Fan Input
Pin 18/19/20
GND
3.9V Zener
W83792D
Figure 5-3. Fan with Tach Pull-Up to +12V
and Zener Clamp
3.9V Zener
FAN
Connector
W83792D
Figure 5-4. Fan with Tach Pull-Up to +12V, or
Totem-Pole Putput and Zener Clamp
7.7.2 Fan speed control
The W83792D/G provides six sets both of PWM and DC mode for fan speed control. The duty cycle of
PWM can be programmed by a 4-bit registers defined in the Bank0 CR[81], CR[83], CR[94],
CR[A3],CR[A4] and CR[A5] . The default duty cycle is set to 100%, that is, the default 4-bit register is
set to 0x8Fh. The expression of duty cycle can be represented as follows.
- 21 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
7.7.2.1. PWM mode :
Duty − cycle(%) =
Programmed 8 - bit Register Value
× 100%
255
+12V
R1
R2
G
PWM Clock Input
PNP Transistor
D
NMOS
S
+
C
FAN
-
Figure 6.
7.7.2.2. DC mode:
W83792D/G has a 4-bit DAC, which produces 0 to 5 volts DC output that provides maximum 3 sets for
fan speed control. The analog output can be programmed in the Bank0 CR[81], CR[83], CR[94],
CR[A3],CR[A4] and CR[A5]. That is default output value is 5 V. The expression of output voltage can
be represented as follow,
OUTPUT VOLTAGE
= AVCC ×
Programmed 4 - bit Register Value
16
The application circuit is shown as follow,
IO+12V
IO+12V
Q1
NPN
R1
3
FANOUT
0
C1
2
4
+
LM358
1
-
Tachometer output
0.1U
3
2
1
11
IO-12V
R4
R3
47K
33K
- 22 -
FAN
W83792AD/AG/D/G
Must be take care when choosing the OP-AMP and the transistor. The OP-AMP is used for amplify the
5V range of the DC output up to 12V. The transistor should has a suitable β value to avoid its base
current pulling down the OP-AMP ’s output and gain the common current to operate the fan at fully
speed. (For more cost and effort efficiently solution please refer to W8339TS/QS –which is the DC fan
pre-driver and it could provide up to 24V gate voltage for external N-channel MOSFET with lower cost
and better performance)
7.7.3
Smart FanTM I Control
W83792D/G supports two Smart Fan function and mapping to temp1 (FAN1, PWMOUT1), temp2
(FAN2, PWMOUT2), temp3 ( FAN3, PWMOUT3) .Smart Fan Control provides two mechanisms. One
is Thermal Cruise mode and the other is Smart FanTM II mode.
7.7.3.1. Thermal Cruise mode
At this mode, W83792D/G provides the Smart Fan system to automatically control fan speed to keep
the temperatures of CPU and the system within specific range. At first a wanted temperature and
interval must be set (ex. 55 °C ± 3 °C) by BIOS and the fan speed will be lowered as long as the
current temperature remains below the setting value. Once the temperature exceeds the high limit
(58°C), the fan will be turned on with a specific speed set by BIOS (ex: 80% duty cycle) and
automatically controlled its PWM duty cycle with the temperature varying. Three conditions may occur:
(1) If the temperature still exceeds the high limit (ex: 58°C), PWM duty cycle will increase slowly. If the
fan has been operating in its full speed but the temperature still exceeds the high limit (ex: 58°C),
a warning message will be issued to protect the system.
(2) If the temperature goes below the high limit (ex: 58°C), but still above the low limit (ex: 52°C), the
fan speed will be fixed at the current speed because the temperature is in the target range (ex: 52
°C ~ 58°C).
(3) If the temperature goes below the low limit (ex: 52°C), PWM duty cycle will decrease slowly to 0 or
a preset stop value until the temperature exceeds the low limit.
Figure 7-1, 7-2 gives an illustration of Thermal Cruise Mode.
A
B
C
D
58`C
55`C
52`C
PWM
Duty
Cycle
100
Fan Start = 20%
50
0
Figure 7-1.
- 23 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
A
B
D
C
58`C
55`C
52`C
PWM
Duty
Cycle
100
Fan Start = 20%
Fan Start = 20%
Fan Stop = 10%
50
0
Figure 7-2.
Of course, Smart Fan control system can be disabled and the fan speed control algorithm can be
programmed by BIOS or application software.
7.7.4
Smart FanTM II Control
W83792D/G provide 4 temperature point each can auto control PWM or DC fan mode. Each Temp
maps
Different fan out level, the relationship is shown as follow:
Fan Duty Cycle
Temp. Tolerance
Fan Duty Cycle 100%
Fan Duty Cycle Level 3
Fan Duty Cycle Level 2
Fan Duty Cycle Level 1
Non-Stop Duty Cycle
Temp. 1
Temp.2
Temp.3
Figure 8. Smart Fan II behavior
- 24 -
Temp.4
Temperature
W83792AD/AG/D/G
7.7.4.1. Temperature Measurement Machine
The temperature data format is 8-bit two-complement for sensor 1 and 9-bit two-complement for
sensor 2/3. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature
data can be obtained by reading the 8 MSBs from the bank0 CR[C0/ C8h] and the LSB from the
bank0 CR[C1/C9h] bit 7. The format of the temperature data is show in Table 3.
8-BIT DIGITAL OUTPUT
TEMPERATURE
9-BIT DIGITAL OUTPUT
8-BIT BINARY
8-BIT HEX
9-BIT BINARY
9-BIT HEX
+125°C
0111,1101
7Dh
0,1111,1010
0FAh
+25°C
0001,1001
19h
0,0011,0010
032h
+1°C
0000,0001
01h
0,0000,0010
002h
-
-
0,0000,0001
001h
00h
0,0000,0000
000h
+0.5°C
+0°C
0000,0000
Table 3.
7.7.4.2. Monitor temperature from thermistor:
The W83792D/G can be connected three thermistors to measure three different environmental
temperatures. The specification of thermistor should be considered to (1) β value is 3435K, (2) resistor
value is 10K ohms at 25°C. In the Figure 11, the thermistor is connected by a serial resistor with 10K
Ohms(1% error), then connect to VREF (Pin 37).
7.7.4.3. Monitor temperature from Pentium IVTM thermal diode or bipolar transistor 2N3904
The W83792D/G can alternate the thermistor to Pentium IVTM thermal diode interface or transistor
2N3904 and the circuit connection is shown as Figure 11. The pin of Pentium IVTM D- is connected to
power supply ground (GND) and the pin D+ is connected to pin VTINx in the W83792D/G. The resistor
R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor
C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be
connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied
together to act as a thermal diode.
VREF
R =1 5K , 1%
B ipolar T ransistor
T em perature S en sor
P IV T D x
B
C = 3300p F
C
2N 3904
W 83792D
E
R =15 K , 1%
OR
P entium IV
CPU
T herm inal
D iode
D+
P IV T D x
C =33 00pF
D-
F igure 9.
- 25 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
7.7.5
SMI# interrupt for W83792D/G Voltage
SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below
low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt
Status Register. (Figure 10-1.)
7.7.6
SMI# interrupt for W83792D/G Fan
SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and
then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading
all the interrupt Status Register. (Figure 10-2.)
High limit
Fan Count limit
Low limit
SMI#
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 10-1. Voltage SMI# Mode
7.7.7
Figure 10-2. Fan SMI# Mode
SMI# interrupt for W83792D/G temperature sensor 1/2/3
(1) Comparator Interrupt Mode
Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the
Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the
temperature remains above the THYST, the interrupt will occur again when the next conversion has
completed. If an interrupt event has occurred by exceeding TO but has not been reset, the interrupts
will not occur again. The interrupts will continue to occur in this manner until the temperature goes
below THYST. (Figure 10-3.)
(2) Two-Times Interrupt Mode
Temperature exceeding TO causes an interrupt and then temperature going below THYST will also
cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register.
Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above
the THYST , the interrupt will not occur. (Figure 10-4.)
(3) One-Time interrupt mode
Temperature exceeding TO causes an interrupt and then temperature going below THYST will not cause
an interrupt. Once an interrupt event has occurred by exceeding TO, then going below THYST, an
interrupt will not occur again until the temperature exceeding TO. (Figure 10-5.)
- 26 -
W83792AD/AG/D/G
TOI
TOI
THYST
THYST
SMI#
*
*
*
*
SMI#
*
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 10-3. Comparator Interrupt Mode
Figure 10-4. Two-Times Interrupt Mode
TOI
THYST
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 10-5. One-Time Interrupt Mode
Note. The IRQ interrupt action like SMI# , but the IRQ is level signal.
7.7.8
Over-Temperature (OVT#) for W83792D temperature sensor 1/2/3
7.7.8.1. Comparator Mode:
Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST.
(Figure 13)
7.7.8.2. Interrupt Mode:
Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading
temperature sensor 1 or sensor 2 or sensor 3 registers. Temperature exceeding TO, then OVT# reset,
and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by
reading temperature sensor 1 or sensor 2 or sensor 3 registers. Once the OVT# is activated by
exceeding TO, then reset, if the temperature remains above THYST, the OVT# will not be activated
again.( Figure 11)
- 27 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
7.7.8.3. ACPI Mode
At this mode, temperature exceeding one level of temperature separation, starting from 0 degree,
causes the OVT# output activated. OVT# will be activated again once temperature exceeds the next
level. OVT# output will act the same manner when temperature goes down. (Figure 11-1).
The granularity of temperature separation between each OVT# output signal can be programmed at
Bank0 CR[4Ch] bit 4-5.
To
THYST
OVT#
(Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*Interrupt Reset when Temperature 1/2/3 is read
Figure 11 Over-Temperature Response Diagram
('C)
100
90
80
70
60
50
40
30
20
10
0
Current Temperature
OVT#
Figure 11-1. ACPI Mode
- 28 -
*
W83792AD/AG/D/G
8. CONTROL AND STATUS REGISTER
8.1
Watch Dog Timer Registers --- Index 01h-04h
MNEMONIC
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
LOCK Watch Dog
0
1
WO
Watch Dog Enable
0
2
RO
Watch Dog Status
0
3
R/W
Watch Dog Timer
0
4
R/W
BIT 1
BIT 0
Reserve
HARD
SOFT
0-
0
0
Unlock Code
Reserve
WDT Stage HARD_TO SOFT_TO
0
0
0
0
Timeout Time
00h (Unit in min)
Reset Condition: Resume reset
Two kinds of watchdog timer function are supported by W83792D/G. One is so-called Soft Watch Dog
Timer, and the other is Hard Watch Dog Timer.
Hard Watch Dog timer if enabled which will start a 4 minutes WDT after completion of system reset. (A
Low to High transition on SYSRSTIN# pin). BIOS need to write a 00 into Watch Dog Timer Register
(04h) to disable timer within 4 minutes, otherwise pin 47 WDTRST# will assert to reset system.
Soft Watch Dog Timer will start to down counting whenever Timeout Time is set and Soft Watch Dog
Timer is enabled. A WDTRST# will be issued while the timer timeouts.
Soft Watch Dog Timer will be disabled automatically after received a SYSRSTIN_N low signal.
To write these registers requires CR40[4]/ENWDT being asserted.
CR01 LOCK Watch Dog
BIT
7~0
NAME
Unlock
Code
ATTRIBUTE
WO
DESCRIPTION
Write 55h, Enable Soft Watch Dog Timer.
Wire AAh, Disable Soft Watch Dog Timer.
Write 33h, Enable Hard Watch Dog Timer.
Write CCh, Disable Hard Watch Dog Timer.
CR02 Watch Dog Enable
BIT
NAME
ATTRIBUTE
DESCRIPTION
7~2
reserve
RO
reserve
1
HARD
RO
1 indicates the Hard Watch Dog is enabled; 0, Hard Watch
Dog is disabled.
0
SOFT
RO
1 indicates the Soft Watch Dog is enabled; 0, Soft Watch Dog
is disabled.
- 29 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
CR03 Watch Dog Status
BIT
NAME
ATTRIBUTE
DESCRIPTION
7~4
reserve
R/W
Reserve.
3~2
WDT
Stage
R/W
Default 0, these 2 bits record last WDT stage for BIOS readout.
The information is used to help BIOS to identify WDT timeout
issue.
1
HARD_TO
RO
1: a hard timeout occurs. This bit will be cleared while reading.
0
SOFT_TO
RO
1: a soft timeout occurs. This bit will be cleared while reading.
CR04 Watch Dog Timer
BIT
NAME
ATTRIBUTE
7~0
Watch Dog
Timer
R/W
8.2
DESCRIPTION
Time to issue WDTRST#. Unit in minutes.
Write 00h will disable the timer.
VRM Tolerance Registers ⎯ Index 12h-13h (Bank 0)
MNEMONIC
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Vcore High Tolerance (2mV unit)
Vcore High Tolerance
0
12
RW
64h(0.2V)
Vcore Low Tolerance (2mV unit)
Vcore Low Tolerance
0
13
RW
64h(0.2V)
Vcore Offset (12.5mV/LSB, 2s complement)
VRM Offset
0
FD
RW
0
RESET Condition: Resume Reset, INIT(CR40.7), or both VID detect no CPU.
Writing Tolerance register will force VCORE Limit Generator generate new voltage limit for VCORE.
For example, writing CR[FDh] with 01 in VRM 10.1 mode will result in VCORE limit registers
CR[2B/2C/2D/2E] become Voltage(VID) +/- Tolerance + 12.5mV.
- 30 -
W83792AD/AG/D/G
8.3
VID Control/Status Registers ⎯ Index 14h-18h (Bank 0)
Mnemonic
VID IN A
Bank Index Attr
0
14
RO
VID Control A
0
15
RW
Entry/Disable VID Output
0
16
RW
VID IN B
0
VID Control B
0
17
18
RO
RW
BIT 7
BIT 6
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VRD10
VRM_CK
VIDIN5 VIDIN4 VIDIN3 VIDIN2 VIDIN1 VIDIN0
RW
RO
EN_VIDO
VIDCHG
VID5
VID4
VID3
RO
VID2
VID1
VID0
0
RO
0
0
0
0
0
0
ENTRYOK
ENTRY_ST
0
Write pattern/ Read 00h
0
0
EN_VIDTG AUTOUPD VIDIN5 VIDIN4 VIDIN3 VIDIN2 VIDIN1 VIDIN0
RW 0
1 RW
EN_VIDO
VIDCHG
VID5
VID4
VID3
RO
VID2
VID1
VID0
0
RO
0
0
0
0
0
0
RESET Condition: Both VID detects no CPU, Resume Reset, INIT(CR40.7),
These registers are used to control 12 VID Pins. When power on, system can strap Pin14 to decide
which VRM table will be used later. This information is shown at CR14.VRM_CK. In VRM9, power on
value will be shown at VIDIN. When system wants to program VID pins, it must program a sequence
to CR16 first, the sequence is 5A, 73, B2, E0. After this, one can set EN_VIDO, and write VID to
output. To disable, write CR16 with A5, 4C, D9, 8A. In this way, the W83792D/G will lock its latest
status.
CR14/CR17 VID IN
7.VRD10
Set to enable VRD10 table translation, clear to enable VRM9 table translation.
Default value is Inversion of VRM_CK.
6.VRM_CK
Power on strapping value of Pin14, this will determine default value of VRD10 (bit 7).
6.AUTOUPD
Auto-update for VRD10.0 VID. In auto-update mode, VID is automatically update
and SMBus to modify upper/lower limit of vcore is not applicable. If programming
High/Low limit is required with VRD10=1, this bit must be cleared as 0.
5~0.VIDIN
Power-on value of VID pins(VRM9 mode) or current VID value on pins(VRM10
mode).
- 31 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
CR15/CR18 VID Control
7.EN_VIDO
Set to enable VID output.
6.VIDCHG
VID on the fly. (Read only) Use to indicate VID have been changed in last 1ms~2ms.
5~0.VID
The desired VID to output to pin. (ENTRY OK must be 1 to write this register)
CR16 Entry/Disable VID Output
7.ENTRYOK
Read only. An one means entry pattern all successfully received, and programming
VID function is valid.
1~0.
ENTRY_ST
Read only. These 2 bits indicate how many patterns have been written into CR16.
7~0 Pattern
Write 8-bit to input patterns for writing VID output privilege. Entrance:
5A(Entry_ST=1), 73(Entry_ST=2), B2(Entry_ST=3), E0(ENTRY_OK=1). Exit:
A5(Entry_ST=2), 4C(Entry_ST=1), D9(Entry_ST=0), 8A(ENTRY_OK=0). The
pattern must be sequentially input without other writes interrupt, otherwise, the
current input sequence is considered as in-effective.
Note. Programming VID for output and using VID pins as GPIO are different. Programming VID output
will activate VID translation, but GPIO will not.
Writing VID should be separated into 2 steps at the first time after VID Entry is enabled. One for set
EN_VIDOUT, the other for set the wanted VID. These actions are used to inform VID Limit Generator
generate new VCORE Limits for written VID. If writing EN_VIDOUT/VIDOUT in the same SMBus
transaction, VID will be output to port but will not update internal Vcore Limits.
VIDIN latches external pin value, and will not affect by VIDOUTDATA.
VID on the fly flag is only used in VRM10 mode. User should not assume its value under VRM9 value.
- 32 -
W83792AD/AG/D/G
GPIO Control/Status Register ⎯ Index 1A~1Eh (Bank 0)
8.4
Mnemonic
GPIO Enable
Bank Index Attr BIT 7
0
1A
RW
GPIOA Output Control
0
1B
RW
GPIOA Data/Status
0
1C
RW
GPIOB Output Control
0
1D
RW
GPIOB Data/Status
0
1E
BIT 6
BIT 5
BIT 4
BIT 3 BIT 2 BIT 1 BIT 0
reserve GPA0_1 GPA2_3 GPA4_B0 GPB1 GPB2_6 GPB_7 reserve
RW
0
0
0
0
0
0
0
0
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
0
0
0
0
0
0
0
0
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
0
0
0
0
0
0
0
0
GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0
0
0
0
0
0
0
0
0
GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0
0
0
0
0
0
0
0
0
Reset Condition: Resume Reset, INIT.
16 GPIO pins are provided in W83792D. Three kinds of registers are used to control GPIO
mechanism. GPIO Enable enables GPIO function, Output Control determines direction of the GPIO
pin, and Data/status put/get data from the pin.
CR1A GPIO Enable
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
reserve
RO
Reserved.
6
GPA0_1
R/W
Enable GPIO function for GPA0 and GPA1.
5
GPA2_4
R/W
Enable GPIO function for GPA2 and GPA3.
4
GPA4_B0
R/W
Enable GPIO function for GPA4, GPA5, GPA6, GPA7 and
GPB0.
3
GPB1
R/W
Enable GPIO function for GPB.
2
GPB2_6
R/W
Enable GPIO function for GPB2, GPB3, GPB4, GPB5 and
GPB6.
1
GPB7
R/W
Enable GPIO function for GPB7.
CR1B/CR1D GPIO Output Control
These bits control the direction of each GPIO pins. Write 0, GPIO serves as input. Write 1, GPIO
serves as output. Default is input.
CR1C/CR1E GPIO Data/Status
Write these bits, the data will response to GPIO, set to output mode. If read this register, will return
this pin data that can input or output in this pin.
- 33 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
8.5
VRM Output Control ---- Index 1F(Bank 0)
Mnemonic
Bank Index Attr BIT 7 BIT 6 BIT 5
VRM Output Control
0
1F
RW
VRM_EN
DIR
1
0
BIT 4
BIT 3 BIT 2
BIT 1
BIT 0
VRMSTS VRMOPV reserve reserve TTRIP2_N TTRIP1_N
RO
1
0
0
1
1
Reset Condition: Resume Reset, INIT.
W83792D have the ability to control VRM(Voltage Regulator Module) enable. At normal power on,
VRM is always enabled. But once TTRIP1_N(Thermal Trip1) or TTRIP2_N is asserted, all VRM will be
disabled until resume reset, no matter TTRIP_N is written 1 again or not.
CR1F VRM Output Control
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
VRM_EN
R/W
Set to 1 will enable VRM Enable control. Clear to 0 enable
GPIO function.
6
DIR
R/W
Pin direction when VRM_EN. Set to 1, serves as output ; 0 will
change into input mode.
5
VRMSTS
RO
Current value on pin VRM_EN. For GPIO use
4
VRMOPV
R/W
VRM_EN Output Value. When Thermal Trip occurs, this bit will
reset to 0 also. In GPIO mode, write this bit will force the value
output to pin.
1
TTRIP2_N
RO
Thermal Trip input 1. This bit is powered by 5VSB. It will latch
a 0 once THERMTRIP1 goes high. It can be reset to 1 by
5VDD Power on and resume reset.
0
TTRIP1_N
RO
Thermal Trip input 0. This bit is powered by 5VSB. It will latch
a 0 once THERMTRIP0 goes high. It can be reset to 1 by
5VDD Power on and resume reset.
TTRIP2_N and TTRIP1_N, any of these two bits cleared as 0 means thermal trip shutdown is
happening. If VRM_EN is set, a zero will be outputted at pin 28 to shut down voltage regulator.
- 34 -
W83792AD/AG/D/G
8.6
Value RAM ⎯ Index 20h- 2Ah AEh AFh (Bank 0)
MNEMONIC
BANK INDEX ATTR
BIT 7
BIT 6
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Vcore A Readout
0
20
RO
Vcore A Voltage
Vcore B Readout
0
21
RO
Vcore B(VIN4) Voltage
VIN0 Readout
0
22
RO
VIN0 Voltage
VIN1 Readout
0
23
RO
VIN1 Voltage
VIN2 Readout
0
24
RO
VIN2 Voltage
VIN3 Readout
0
25
RO
VIN3 Voltage
5VCC Readout
0
26
RO
5VCC Voltage
Temperature 1 Readout
0
27
RO
Temperature Sensor 1
FAN 1 Count
0
28
RO
FAN 1 Count Readout
FAN 2 Count
0
29
RO
FAN 2 Count Readout
FAN 3 Count
0
2A
RO
FAN 3 Count Readout
LOW BITS I
0
3E
RO
VIN1
VIN0
VCOREB
VCOREA
LOW BITS II
0
3F
RO
TEMP1 EN_HLD
5VCC
VIN3
VIN2
Value RAM stores the latest sensed system parameter. Each data will refresh automatically after the
channel input converted.
EN_HLD bit(Writable, default is 0) of AFh is capable of turn on Sample and Hold mechanism.
VcoreA Calculation
Vcore A Voltage = (CR[20]*4 + CR[3E]&0x03) * 0.002;
VcoreB Calculation
VcoreB Voltage = (CR[21]*4 + CR[3E]&0x0C/4) * 0.002;
VIN0~VIN3 Calculation
VIN0 Voltage = (CR[22]*4 + CR[3E]&0x30/16) * 0.004;
VIN1 Voltage = (CR[23]*4 + CR[3E]&0xC0/16) * 0.004;
VIN2 Voltage = (CR[24]*4 + CR[3F]&0x03) * 0.004;
VIN3 Voltage = (CR[25]*4 + CR[3F]&0x0C/4) * 0.004;
5VCC Calculation
5VCC Voltage = (CR[26]*4 + CR[3F]&0x30/16) * 0.006;
- 35 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
8.7
Limit RAM ⎯ Index 2Bh- 2Dh (Bank 0)
MNEMONIC
Vcore 1 High Limit
MNEMONIC
Vcore 1 Low Limit
Vcore 2 High Limit
Vcore 2 Low Limit
VIN0 High Limit
VIN0 Low Limit
VIN1 High Limit
VIN1 Low Limit
VIN2 High Limit
VIN2 Low Limit
VIN3 High Limit
VIN3 Low Limit
5VCC High Limit
5VCC Low Limit
Temperature 1 High Limit
Temperature 1 Low Limit
FAN 1 Count High Limit
FAN 2 Count High Limit
FAN 3 Count High Limit
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Vcore A Voltage High Limit (unit 8mV)
0
2B
RW
DEPENDS ON VID
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Vcore A Voltage Low Limit
0
2C
RW
DEPENDS ON VID
Vcore B Voltage High Limit
0
2D
RW
DEPENDS ON VID
Vcore B Voltage Low Limit
0
2E
RW
DEPENDS ON VID
VIN0 Voltage High Limit
0
2F
RW
FFh
VIN0 Voltage Low Limit
0
30
RW
00h
VIN1 Voltage High Limit
0
31
RW
FFh
VIN1 Voltagez
0
32
RW
00h
VIN2 Voltage High Limit
0
33
RW
FFh
VIN2 Voltage Low Limit
0
34
RW
00h
VIN3 Voltage High Limit
0
35
RW
FFh
VIN3 Voltage Low Limit
0
36
RW
00h
5VCC Voltage High Limit
0
37
RW
FFh
5VCC Voltage Low Limit
0
38
RW
00h
Temperature Sensor 1 High Limit
0
39
RW
7Fh
Temperature Sensor 1 Low/Hysteresis Limit
0
3A
RW
00h
FAN 1 Count High Limit
0
3B
RW
FFh
FAN 2 Count High Limit
0
3C
RW
FFh
FAN 3 Count High Limit
0
3D
RW
FFh
- 36 -
W83792AD/AG/D/G
Limit RAM setups the high/low limit for each channel in Value RAM. While exceeding these limits,
system will take certain action determined by prior setups.
FAN Count high limits should be the limit for lowest fan speed. This is because the slower the fan is,
the more the internal clock will be counted by internal clock.
Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means
interrupt will never be generated except the case when voltages go below the low limits.
VcoreA Limit Setup
CR[2B/2C] = [Desired Voltage]/0.008;
VcoreB Limint Setup
CR[2D/2E] = [Desired Voltage]/0.008;
VIN0~VIN3 Limit Setup
CR[2F~36] = [Desired Voltage] / 0.016;
5VCC Limit Setup
CR[37/38] = [Desired Voltage] / 0.024;
8.8
Configuration Register ⎯ Index 40h (Bank 0)
MNEMONIC BANK INDEX ATTR BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
INIT IRQEDGE IRQPOL ENWDT INT_CLR EN_IRQ EN_SMI START
Configuration
0
40
RW
0
0
0
0
0
0
0
1
Reset Condition: Resume Reset, INIT.
Configuration Register controls the system reset, stop, power down and warning output mode.
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
Initialization
R/W
6
IRQ output
R/W
Set one restores power on default value to all registers except
the Serial Bus Address register. This bit clears itself since the
power on default is zero.
Set 0 , IRQ output level signal . Set 1, output 200 us pulse
signal. Default is 0.
5
IRQ
Polarity
R/W
When set to 0, IRQ active high. Set to 1, IRQ active low.
Default is 0.
4
ENWDT
R/W
Set this bit to 1 will enable Watch Dog Timer function. Watch
dog timer function will reset system(pin 47) while it timeouts.
3
INT_Clear
R/W
A one disables the SMI# and IRQ# outputs without affecting
the contents of Interrupt Status Registers. The device will stop
monitoring at last channel. It will resume upon clearing of this
bit.
Note: The outputs of Interrupt pins will not be cleared if the
user writes a zero to this location after an interrupt has
occurred unlike "INT_Clear'' bit.
- 37 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Continued.
BIT
NAME
ATTRIBUTE
DESCRIPTION
2
EN_IRQ
R/W
A one enables the IRQ Interrupt output.
1
EN_SMI#
R/W
A one enables the SMI# Interrupt output. If EN_SMI# and
EN_IRQ are both set to 1, SMI# will override the IRQ output.
0
START
R/W
A one enables startup of monitoring operations; a zero puts
the analog part in Power-down mode.
Note: The outputs of Interrupt pins will not be cleared if the
user writes a zero to this location after an interrupt has
occurred unlike "INT_Clear'' bit.
8.9
Interrupt Status Registers ⎯ Index 41h 42h 9Bh(Bank 0)
MNEMONIC
BANK INDEX ATTR BIT 7
BIT 6
BIT 5
FAN2
FAN1
BIT 4
BIT 3
Interrupt Status 1
0
41
RO
FAN3
Interrupt Status 2
0
42
RO
FAN7 VIDCHG Chassis 5VCC
VIN3
Interrupt Status 3
0
9B
RO
FAN6
VSB
FAN5
BIT 2
BIT 1
BIT 0
TEMP3 TEMP2 TEMP1 VcoreB VcoreA
FAN4
VBAT
VIN2
VIN1
VIN0
TART3 TART2 TART1
An one represents corresponding channel have been exceed its limit.
TART will assert while target temperature cannot be achieved after 3 minutes full speed of
corresponding FAN. Read Interrupt Status will clear the interrupt flag.
8.10 SMI#/IRQ Mask Registers ⎯ Index 43h~45h 9Ch 9Dh(Bank 0)
MNEMONIC
BANK INDEX ATTR
SMI/IRQ Mask 1
0
43
RW
SMI/IRQ Mask 2
0
44
RW
SMI/IRQ Mask 3
0
9C
RW
BIT 7
BIT 6
BIT 5
FAN3
FAN2
FAN1
0
0
0
CLR_CHS VIDCHG Chassis
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TEMP3 TEMP2 TEMP1 VcoreB VcoreA
0
0
0
0
0
VDD
VIN3
VIN2
VIN1
VIN0
0
0
0
0
0
0
0
0
FAN6
FAN5
FAN4
VBAT
VSB
0
0
0
0
0
TART3 TART2 TART1
0
0
0
These are SMI/IRQ mask registers. Set to one will disable the corresponding interrupt sources. Clear
to 0 will enable that interrupt source.
SMI Mask 2 bit 7 is CLR_CHS(Clear Chassis), write this bit with an one will clear internal caseopen
latch, and after latch is clear, CLR_CHS will be reset to 0 itself.
- 38 -
W83792AD/AG/D/G
8.11 Realtime Status Registers ⎯ Index A9h~ABh(Bank 0)
MNEMONIC
BANK INDEX ATTR BIT 7
BIT 6
BIT 5
FAN2
FAN1
BIT 4
BIT 3
Realtime status 1
0
A9
RO
FAN3
Realtime status 2
0
AA
RO
FAN7 VIDCHG Chassis
VDD
VIN3
Realtime status 3
0
AB
RO
FAN6
VBAT
VSB
FAN5
FAN4
BIT 2
BIT 1
BIT 0
TEMP3 TEMP2 TEMP1 VcoreB VcoreA
VIN2
VIN1
VIN0
TART3 TART2 TART1
Realtime status registers show the related channel exceeding limit or not at the polling moment.
Return 1 represents related channel have exceeded the limit defined in limit RAM.
8.12 Serial Bus Address Registers ⎯ Index 48h 4A(Bank 0)
MNEMONIC
BANK INDEX ATTR
SMBus Address
0
48
RW
TEMP2/3 Address
0
4A
RW
BIT 7
BIT 6 BIT 5 BIT 4
reserve
0
BIT 2 BIT 1 BIT 0
SMBus address
0
DIS_T3
0
BIT 3
1
1
0
1
T3 Address
DIS_T2
IA[1]
0
IA[0]
1
IA[1]
IA[0]
T2 Address
0
IA[1]
IA[0]
Reset Condition: Resume Reset
W83792D provides 2 power on strapping pin for default SMBus address. With these 2 pins, 4 kinds of
default address setups are possible.
CR48 SMBus Address
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
Reserved
RO
Reserved.
6-0
SMBADDR1
R/W
Serial Bus Address <7:1> for general index registers. The
address bit 0 and bit 1 are trapped by the pin 10 and pin 11,
respectively.
CR4A Temperature 2 and Temperature 3 Serial Bus Address Register
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
DIS_T3
R/W
Set to 1, disable temperature 3 sensor accessing from
Temperature 3 Serial Bus Address. Still can access from Bank
0 Cxh.
6-4
I2CADDR3
R/W
Temperature 3 Serial Bus Address. The serial bus address is
1001xxx. Where xxx are defined in these bits.
3
DIS_T2
R/W
Set to 1, disable temperature Sensor accessing from
Temperature 2 Serial Bus Address. Still can access from Bank
0 Cxh.
2-0
I2CADDR2
R/W
Temperature 2 Serial Bus Address. The serial bus address is
1001xxx. Where xxx are defined in these bits.
- 39 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
8.13 ID, Bank Select Registers-- Index 49h 4Eh 4Fh 58h (Bank 0)
MNEMONIC
BANK INDEX ATTR
BIT 7
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
13h for CSB version.
Device Version ID
0
49
RO
Bank Select
x
4E
RW
Winbond vendor ID(Toggle)
0
4F
RO
Return 5Ch(if HBACS=1); return A3h(if HBACS=0)
Winbond Chip ID
0
58
RO
7Ah
HBACS
Reserved
1
0 RO
BANK Select
0
0
0
CR4E Bank Select Register (Reset Condition: Resume Reset)
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
HBACS
R/W
High Byte Access of Winbond Vendor ID. Set to 1, read 4Fh will
get 5Ch ; Clear as 0, read 4Fh will return A3h.
2-0
Bank
Select
R/W
Bank select is to change current indexed bank. Available banks
are 0,1, and 7.
8.14 Pin Control Register -- Index4Bh (Bank 0)
MNEMONIC BANK INDEX ATTR
Pin Control
0
4B
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
VIDLevel FAN6/WDT SELVIDA SELVIDB reserve EnFAN7
VRM10
0
0
0
0
0
BIT 1 BIT 0
TT Level
0
Reset Condition: Resume Reset
Pin Controls enables different pin/clock selections.
ATTRIBUTE
DESCRIPTION
7
BIT
VID Level
R/W
6
FAN6/WDT
R/W
5
SELVIDA
R/W
4
SELVIDB
R/W
3
2
reserve
FAN7
Enable
Thermal
Trip Level
R/W
R/W
Set this bit enables VID with 0.8/0.4V level. Clear this bit makes
VID in input mode with TTL level. Default value is set by VRM10
power-on trapping.
Set this bit enables FAN6 Functionality. Default is Watch Dog
Timer Function.
Clear this bit to 0 will perform Watch Dog Functionality on Pin
47/48.
Set to enable VIDA with offset output at VID port B.
Clear to disable this function.
Set to enable VIDB with offset output at VID port A.
Clear to disable this function.
reserved
Set to enable FAN7 function and disable Thermaltrip/VRM_EN
pin function.
Thermal Trip Level Selector. These two bits select the input level
for ThermalTrip 1/2. 11b is 1.0Vref GTLP. 10b enables 0.8Vref
GTL. 00b set these 2 pins to TTL.
1-0
NAME
R/W
- 40 -
W83792AD/AG/D/G
8.15 SMI#/OVT# Property Select -- Index 4Ch (Bank 0)
MNEMONIC
BANK INDEX ATTR
IRQ/OVT Polarity
0
4C
RW
ACPI Difference
0
5E
RW
BIT 7
BIT 6
BIT 5
TEMP_SMI_MD
BIT 4
OVT_MD
0(Comp Interrupt) 0(Comparator)
BIT 3
BIT 2
BIT 1
BIT 0
EN_OVT3 EN_OVT2 EN_OVT1 OVTPOL
0
0
0
reserve
DIFFREG (ACPI Increment Difference)
0
5
1
Reset Condition: Resume Reset.
Register 4Ch selects SMI modes, OVT modes, OVT sources and OVT polarity.
If OVT_MD selects ACPI mode, register 5Eh determines the temperature interval between each OVT
is issued. Default sets to 5, that is, every time temperature reaches 5*n degree, an OVT will be issued.
BIT
NAME
7-6
TEMP_SMI_MD
[1:0]
ATTRIBUTE
R/W
DESCRIPTION
Temperature SMI# Mode Select.
<00> - Comparator Interrupt Mode:(Default)
Temperature 1/2/3 exceeds TO (Over-temperature)
limit causes and interrupt and this interrupt will be reset by
reading all the Interrupt Status.
<01> - Two Time Interrupt Mode:
This bit use in temperature sensor 1/2/3 interrupt
mode with hysteresis type. Temperature exceeding TO,
causes an interrupt and then temperature going below
THYST will also cause an interrupt if the previous interrupt
has been reset by reading all the interrupt Status
Register. Once an interrupt event has occurred by
exceeding TO, then reset, if the temperature remains
above the THYST.
<10> - One Time Interrupt Mode:
This bit use in temperature sensor 1/2/3 interrupt
mode with hysteresis type. Temperature exceeding TO
(Over-temperature, defined in Bank 1/2) causes an
interrupt and then temperature going below THYST
(Hysteresis temperature, defined in Bank 1/2) will not
cause an interrupt. Once an interrupt event has occurred
by exceeding TO, then going below THYST, and interrupt
will not occur again until the temperature exceeding TO.
- 41 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Continued.
BIT
5-4
NAME
OVT_MD[1:0]
ATTRIBUTE
R/W
DESCRIPTION
OVT# Mode Select. There are three OVT# signal output
type.
<00> - Comparator Mode: (Default)
Temperature exceeding TO causes the OVT# output
activated until the temperature is less than THYST.
<01> - Interrupt Mode:
Setting temperature exceeding TO causes the OVT#
output activated indefinitely until reset reading
temperature sensor 1/2/3 registers. Temperature
exceeding TO, then OVT# reset, and then temperature
going below THYST will also cause the OVT# activated
indefinitely until reset by reading temperature sensor
1/2/3(reading interrupt status). Once the OVT# will not be
activated by exceeding TO, then reset, if the temperature
remains above THYST, the OVT# will not be activated
again.
<10> - ACPI Mode:
If set to 1 then enable ACPI OVT# output. Which is
always send an OVT# pulse signal (22us, if not a
suddenly temperature jump)when the temperature over
the ACPI temperature increment value defined at Index
5Eh.
3
EN_OVT3
R/W
Enable temperature sensor 3 over-temperature (OVT)
output if set to 1. Default 0, disable OVT2 output through
pin OVT#. The pin OVT# is wire OR with OVT1 and
OVT2.
2
EN_OVT2
R/W
Enable temperature sensor 2 over-temperature (OVT)
output if set to 1. Default 0, disable OVT2 output through
pin OVT#. The pin OVT# is wire OR with OVT1 and
OVT3.
1
EN_OVT1
R/W
Enable temperature sensor 1 over-temperature (OVT)
output .if set to 1. Default 0, disable OVT1 output through
pin OVT#. The pin OVT# is wire OR with OVT2 and
OVT3.
0
OVTPOL
R/W
Over-Temperature Polarity. Write 0, OVT# active high.
Write 1, OVT# active low. Default is 1 .
- 42 -
W83792AD/AG/D/G
8.16 Diode Selection Register -- Index 59h (Bank 0)
Mnemonic
Thermal Diode Select
Temperature 1 Offset
Temperature 2 Offset
Temperature 3 Offset
Bank Index Attr
0
59
0
90
0
91
0
92
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
reserve TDSEL3 TDSEL2 TDSEL1 K8SEL1 NVSEL1 K8SEL23 NVSEL23
RW
RW
0
1
1
0
0
0
reserve
OFFSET1
0
00h
reserve
OFFSET2
0
0
reserve
OFFSET3
0
00h
0
0
RW
Reset Condition: Resume Reset, INIT.
CR59h Thermal Diode Select
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
Reserved
RO
Reserved.
6
TDSEL3
R/W
Temperature sensor 3 diode mode. When set to 1, select
Pentium IV compatible Diode. Set to 0 to select Thermistor
mode
5
TDSEL2
R/W
Temperature sensor 2 diode mode. When set to 1, select
Pentium IV compatible Diode. Set to 0 to select Thermistor
mode
4
TDSEL1
R/W
Temperature sensor 1 diode mode. When set to 1, select
Pentium IV compatible Diode. Set to 0 to select Thermistor
mode
3
K8SEL1
R/W
Set to select K8 Temperature Table for VTIN1.
2
NVSEL1
R/W
Set to select nVidia NV34 Temperature Table for VTIN1.
1
K8SEL23
R/W
Set to select K8 Temperature Table for VTIN2/3.
0
NVSEL23
R/W
Set to select nVidia NV34 Temperature Table for VTIN2/3.
K8 and NV34 GPU table is also supported in W83792D. VTIN2, VTIN3 should be always in the same
mode since they will decide the VID mapping. There is only one exception, that is, thermistor mode.
VTIN2 and VTIN3 can choose one in thermistor mode and another in other modes.
VTIN1 is separately set up in this configuration.
Configuration these bits have priority as…
Thermistor mode > K8 diode mode > NVIDIA diode mode > P4 mode.
- 43 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
CR90h-92h Temperature Offset
BIT
NAME
7-6
5-0
Reserved
Temperature
Offset
ATTRIBUTE
RO
R/W
DESCRIPTION
Reserved.
Related temperature channel base temperature. The
temperature is added by both monitor value and offset value.
01,1111 => +31 degree C
01,1110 => +30 degree C
:
00,0001 => +1 degree C
00,0000 => +0 degree C
11,1111 => -1 degree C
11,1110 => -2 degree C
:
10,0000 => -32 degree C
8.17 FANIN Divisor Control Registers -- Index 47h 5Bh 5Ch(Bank 0)
MNEMONIC
BANK INDEX ATTR
FAN Divisor 1
0
47
RW
FAN Divisor 2
0
5B
RW
FAN Divisor 3
0
5C
RW
FAN 7 Divisor and Control
0
9E
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2 BIT 1 BIT 0
FAN2_OB
FAN 2 Divisor
FAN1_OB
FAN 1 Divisor
0
1
0
1
FAN4_OB
FAN 4 Divisor
FAN3_OB
FAN 3 Divisor
0
1
0
1
FAN6_OB
FAN 6 Divisor
FAN5_OB
FAN 5 Divisor
0
1
0
1
Manual
0
- 44 -
Trigger Mask Reserve FAN7_OB
0
0
0
0
FAN 7 Divisor
1
W83792AD/AG/D/G
Reset Condition: Resume Reset, INIT, 5VDD posedge
BIT
7,3
NAME
ATTRIBUTE
FAN_OB
DESCRIPTION
R/W
Enable Fan as Output Buffer. Set to 1, FANOUT can drive
logical high or logical low.
6-4,
FAN_DIV
R/W
FAN PWM Input Divisor.
2-0
000 - divided by 1;
001 - divided by 2(Default);
010 - divided by 4;
011 - divided by 8;
100 - divided by 16;
101 - divided by 32;
110 - divided by 64;
111 - divided by 128.
W83792D supports different FAN power on time. The FAN will power on one by one after 5VDD is
ready. (At sequence FAN6-2-3-1-4-5) Fan Divisor also determines the FAN power on time. Under
power-on-default setting(divisor = 2), to power on all FAN will take 71.5ms. If divisor is change, the
timing will be different.
CR9E FAN 7 Divisor and Control
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
Manual
R/W
Fan7 Automatic/Manual Mode Selection. Clear to 0, always
polling FAN7 automatically; Set to 1, only polling once while
Trigger<bit 6> is set to 1.
6
Trigger
R/W
Fan7 count trigger. Once set, W83792D will count FANIN7 in
Auto Mode.
After FAN count write back, this bit will be clear to 0.
5
Mask
R/W
Interrupt/SMI mask for FAN7.
8.18 VBAT Monitor Control Register -- Index 5Dh (Bank 0)
OLARIT
VBAT Monitor Control
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4
0
5D
BIT 3
TT1
TT2
reserve
CLR_TT1
RO
RO
0
0
BIT 2
BIT 1
CLR_TT2 reserve
BIT 0
EN_VBAT
RW
0
0
0
Reset Condition: Resume Reset
.
- 45 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
TT1
RO
Thermal Trip 1 event log. Powered by VBAT.
6
TT2
RO
Thermal Trip 2 event log. Powered by VBAT.
5-4,1
reserve
RO
Reserved.
3
CLR_TT1
R/W
Set this bit to 1 will reset TT1 to 0, after bit 7 reset,
CLR_TT1 will deassert automatically.
2
CLR_TT2
R/W
Set this bit to 1 will reset TT2 to 0, after bit 6 reset,
CLR_TT2 will deassert automatically.
0
EN_VBAT_MNT
R/W
Write 1, enable battery voltage monitor. Write 0,
disable battery voltage monitor. If enable this bit, the
monitor value is valid after one monitor cycle.
TT1, TT2, 2 thermal trip event log bits powered by VBAT. They will never cleared by all reset. To
clear it must set CLR_TT1 and CLR_TT2 to 1. For real time status of Thermal trip, please refer to
CR[1F].
8.19 FAN Pre-Scale Registers-- Index 80h 82h 93h A0h A1h A2h(Bank 0)
OLARIT
BANK
INDEX
ATTR
PWM1 Prescalar
0
80
RW
PWM 2 Prescalar
0
82
RW
FAN 3 Prescalar
0
93
RW
FAN 4 Prescalar
0
A0
RW
FAN 5 Prescalar
0
A1
RW
FAN 6 Prescalar
0
A2
RW
FAN 7 Prescalar
0
9D
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
CLKSEL
PRE_SCALE1
0
01h (divider equals PRE_SCALE1 + 1)
CLKSEL
PRE_SCALE2
0
01h (divider equals PRE_SCALE2 + 1)
CLKSEL
PRE_SCALE3
0
01h
CLKSEL
PRE_SCALE4
0
01h
CLKSEL
PRE_SCALE5
0
01h
CLKSEL
PRE_SCALE6
0
01h
CLKSEL
PRE_SCALE7
0
01h
- 46 -
BIT 0
W83792AD/AG/D/G
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT
7
NAME
ATTRIBUTE
DESCRIPTION
R/W
PWM Input Clock Select. This bit select Fan input clock
to pre-scale divider.
PWM_CLK_SEL
0: 14.318MHz(External)
6-0
PRE_SCALE[6:0]
R/W
1: 1MHz(Internal)
Fan PWMOUT Input Clock Pre-Scale. The divider of
input clock is the number defined by pre-scale. Thus,
writing 0 transfers the input clock directly to counter. The
maximum divider is 128 (7Fh).
00h : divider is 1
01h : divider is 2
02h : divider is 3
:
:
PWM frequency = (Input clock / pre-scale ) / 16
8.20 FAN Duty Cycle Select Register--81h 83h 94h A3h A4h A5h(Bank 0)
MNEMONIC
BANK
INDEX
ATTR
FAN 1 Duty Cycle
0
81
RW
FAN 2 Duty Cycle
0
83
RW
FAN 3 Duty Cycle
0
94
RW
FAN 4 Duty Cycle
0
A3
RW
FAN 5 Duty Cycle
0
A4
RW
FAN 6 Duty Cycle
0
A5
RW
FAN 7 Duty Cycle
0
A6
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
PWM/DC
reserve
PRGVAL1
1
0
Fh
PWM/DC
reserve
PRGVAL2
1
0
Fh
PWM/DC
reserve
PRGVAL3
1
0 RO
Fh
PWM/DC
SYNC T1/2/3
reserve
PRGVAL4
1
0(Stand alone)
0
Fh
PWM/DC
SYNC T1/2/3
reserve
PRGVAL5
1
0
0
Fh
PWM/DC
SYNC T1/2/3
reserve
PRGVAL6
1
0
0
Fh
PWM/DC
SYNC T1/2/3
reserve
PRGVAL7
1
0
0
Fh
- 47 -
BIT 0
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Reset Condition: Resume Reset, INIT.
BIT
7
NAME
PWM/DC
ATTRIBUTE
R/W
DESCRIPTION
PWM/DC FAN Config.
Set 1, FANOUT is configured as PWM output.
Clear to 0, FANOUT is configured as DC output.
6-5
SYNC T1/2/3
R/W
Sync with Temp Sensor.
00: Stand alone, does not sync with any temperature sensor
01: Sync with Temp1.
10: Sync with Temp2.
11: Sync with Temp3.
4
Reserve
RO
Reserved
3-0
FAN_DC[3:0]
R/W
Fan Duty Cycle. This 4-bit register determines the number of
input clock cycles, out of 16-cycle period, during which the
PWM output is high. During smart fan control mode, read this
register will return smart fan duty cycle. In Manual mode, write
this register to control the output PWM Duty cycle.
0h: PWM output is always logical Low.
Fh: PWM output is always logical High.
Xh: PWM output logical High percentage is (X/16*100%)
during one cycle.
Notice. To use SYNC T1/2/3 function, the corresponding FAN1, FAN2, or FAN3 must be enabled with
temperature cruise mode. Otherwise, only 2 DC output is available. One is full speed when exceeding
flag raised, and the other is start speed when not exceeding temperature limit.
User may not read out PRGVAL with 0xF when system power up, because the FAN will sequentially
powered on one by one. The order of FAN power on is followed the sequence 6-2-3-1-4-5.
At DC FAN mode, the output level and corresponding programmed value have the relation as
following table.
PRGVAL
OUTPUT LEVEL
(VOLT)
PRGVAL
OUTPUT LEVEL
(VOLT)
0000
0001
0010
0011
0100
0101
0110
0111
0
0.31
0.62
0.94
1.25
1.56
1.87
2.19
1000
1001
1010
1011
1100
1101
1110
1111
2.50
2.81
3.12
3.44
3.75
4.06
4.37
4.69
For Fan1, Fan2, and Fan 3, the output value will be affected by power-on-strap resistor. In the case of
using 100K resistor, the output drifts about 0.15V with normal value.
- 48 -
W83792AD/AG/D/G
8.21 FAN 1/2 Configuration Register-- Index 84h (Bank 0)
MNEMONIC
FAN Configuration
BANK INDEX ATTR BIT 7 BIT 6
0
84
RW
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
reserve
FAN3_TYPE
FAN2_TYPE
FAN1_TYPE
0h
0
0
0
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT
NAME
7-6
5-4
Reserved
FAN3_TYPE
ATTRIBUTE
R/W
3-2
FAN2_TYPE
R/W
1-0
FAN1_TYPE
R/W
DESCRIPTION
Reserved
FAN 3 PWM Control Type.
00 - Manual PWM/DC Control Mode. (Default)
01 - Thermal Cruise mode. (Corresponding to VTIN3)
10/11 – Smart FAN II mode. (Corresponding to VTIN3)
FAN 2 PWM Control Type.
00 - Manual PWM/DC Control Mode. (Default)
01 - Thermal Cruise mode. (Corresponding to VTIN2)
10/11 – Smart FAN II mode. (Corresponding to VTIN2)
FAN 1 PWM Control Type.
00 - Manual PWM/DC Control Mode. (Default)
01 - Thermal Cruise mode. (Corresponding to VTIN1)
10/11 – Smart FAN II mode. (Corresponding to VTIN1)
8.22 Fan 1 Target Temperature Registers -- Index 85h 86h 96h(Bank 0)
MNEMONIC
BANK INDEX ATTR
FAN 1 Target Temperature
0
85
RW
FAN 2 Target Temperature
0
86
RW
FAN 3 Target Temperature
0
96
RW
BIT 7
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
reserve
FAN_TAR_T1
0
00h
reserve
FAN_TAR_T2
0
00h
reserve
FAN_TAR_T3
0 RO
00h
Reset Condition: Resume Reset, INIT, 5VDD posedge.
- 49 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
VTIN target temperature register for Thermal Cruise mode.
BIT
NAME
7
Reserved
6-0
FAN_TAR_T
ATTRIBUTE
DESCRIPTION
Reserved.
R/W
Fan Target Temperature. / Temperature Point 1 For
Thermal Cruise mode. When the sensed temperature is over
the target temperature with tolerance, the smart fan duty cycle
will go up until the duty cycle reach FFh.
For Smart Fan II Mode, this temperature is used to distinguish
the FANOUT between Fan Duty Cycle Level 1 and Non-stop
Duty Cycle.
8.23 Tolerance of Fan1/2 Target Temperature Register -- Index 87h 97h(Bank0)
MNEMONIC
BANK
INDEX
ATTR
FAN Tolerance
0
87
RW
FAN 3 Tolerance
0
97
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
TOL_TEMP2
TOL_TEMP1
0h
0h
reserve
TOL_TEMP3
0 RO
0h
BIT 0
Reset Condition: Resume Reset, INIT, 5VDD posedge.
Tolerance of Fan1/2 target temperature register.
BIT
NAME
ATTRIBUTE
DESCRIPTION
7-4
TOL_T2[3:0]
R/W
Tolerance of Fan 2 Target Temperature. Only for Thermal
Cruise mode and Smart Fan II mode.
3-0
TOL_T1[3:0]
R/W
Tolerance of Fan 1 Target Temperature. Only for Thermal
Cruise mode and Smart Fan II mode.
Tolerance of Fan 3 target temperature register.
BIT
NAME
ATTRIBUTE
DESCRIPTION
7-4
reserved
R/W
reserved
3-0
TOL_T3[3:0]
R/W
Tolerance of Fan 3 Target Temperature. Only for Thermal
Cruise mode and Smart Fan II mode.
- 50 -
W83792AD/AG/D/G
8.24 Fan Stop/Start Duty Cycle/DC Level Registers -- Index 88h 89h 98h(Bank 0)
MNEMONIC
BANK
INDEX
ATTR
FAN 1 Nonstop/Start
0
88
RW
FAN 2 Nonstop/Start
0
89
RW
FAN 3 Nonstop/Start
0
98
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
START_DC1
MIN_NOSTOP_DC1
01h
01h
START_DC2
MIN_NOSTOP_DC2
01h
01h
START_DC3
MIN_NOSTOP_DC3
01h
01h
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT
NAME
7-4
START_DC
ATTRIBUTE
R/W
DESCRIPTION
In Thermal Cruise mode, PWM duty will increase from 0 to this
register value to provide a minimum duty cycle to turn on the
fan. This register should be written a fan start-up duty cycle.
At Smart Fan II mode. This register is used as Fan Duty Cycle
Level 1.
3-0
STOP_DC
R/W
In Thermal Cruise mode, PWM duty will be 0 if it decreases to
under this value. This register should be written a non-zero
minimum PWM stop duty cycle.
8.25 Fan Stop Time Register -- Index 8Ch 8Dh 9Ah(Bank 0)
MNEMONIC
BANK
INDEX
ATTR
FAN 1 Stop Time
0
8C
RW
FAN 2 Stop Time
0
8D
RW
FAN 3 Stop Time
0
9A
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
STOP_TIME1
3Ch (6 sec)
STOP_TIME2
3Ch (6 sec)
STOP_TIME3
3Ch (6 sec)
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT
NAME
7-0
STOP_TIME
ATTRIBUTE
R/W
DESCRIPTION
In Thermal Cruise mode, this register determines the time of
which PWM duty/DC Level is from stop duty cycle/DC level to
0. The unit of this register is 0.1 second. Set Stop Time to 0
implies never stop FANs. The default value is 6 seconds.
- 51 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
8.26 Fan Step Down/Up Time Register -- Index 8Eh 8Fh(Bank 0)
MNEMONIC
BANK
INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FAN Step Up Time
0
8E
RW
FAN Step Down Time
0
8F
RW
UPTIME
0Ah (1 sec)
DOWNTIME
0Ah (1 sec)
Reset Condition: Resume Reset, INIT, 5VDD posedge.
FAN Step Up Time
BIT
NAME
ATTRIBUTE
DESCRIPTION
7-0
STEP_DOWN_T
R/W
The time interval, which is 0.1 second unit, to decrease
PWM duty in Thermal Cruise mode.
FAN Step Down Time
BIT
7-0
NAME
ATTRIBUTE
DESCRIPTION
R/W
The time interval, which is 0.1 second unit, to increase PWM
duty in Thermal Cruise mode.
STEP_UP_T
8.27 Fan 1/2/3 Smart Fan II Temperature/ Duty Cycle setups -- Index E0h~EBh
5Fh(Bank 0)
Mnemonic
Bank
Index
Attr
FAN 1 Duty Cycle Level
0
E0
RW
FAN 2 Duty Cycle Level
0
E1
RW
FAN 3 Duty Cycle Level
0
E2
RW
FAN 1 Temperature Point 2
0
E3
RW
FAN 1 Temperature Point 3
0
E4
RW
FAN 1 Temperature Point 4
0
E5
RW
FAN 2 Temperature Point 2
0
E6
RW
FAN 2 Temperature Point 3
0
E7
RW
FAN 2 Temperature Point 4
0
E8
BIT 7
RW
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Fan Duty Cycle Level 2
Fan Duty Cycle Level 3
8h
Bh
Fan Duty Cycle Level 2
Fan Duty Cycle Level 3
8h
Bh
Fan Duty Cycle Level 2
Fan Duty Cycle Level 3
8h
Bh
reserve
Temperature Point 2
0
28h
reserve
Temperature Point 3
0
3Ch
reserve
Temperature Point 4
0
50h
reserve
Temperature Point 2
0
28h
reserve
Temperature Point 3
0
3Ch
reserve
Temperature Point 4
0
50h
- 52 -
W83792AD/AG/D/G
Fan 1/2/3 Smart Fan II Temperature/ Duty Cycle setups -- Index E0h~EBh 5Fh(Bank 0), continued.
Mnemonic
Bank
Index
Attr
FAN 3 Temperature Point 2
0
E9
RW
FAN 3 Temperature Point 3
0
EA
RW
FAN 3 Temperature Point 4
0
EB
RW
All FAN on Temperature
Point
0
5F
RW
BIT 7
BIT 6
BIT 5
reserve
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Temperature Point 2
0
28h
reserve
Temperature Point 3
0
3Ch
reserve
Temperature Point 4
0
50h
Temperature point above this will turn all FAN to full
speed
reserve
0
7Fh
Reset Condition: Resume Reset, INIT.
W83792D also provides a special mode for FAN. It’s called Smart Fan II mode. In this mode,
W83792D will output fix cycles when related temperature sensors detects the temperature in preset
temperature region. Their relation looks like the following figure.
5Fh specifies a temperature point, if any temperature sensor is sensed above this, all FAN will be
push to full speed. Default is 127 degree, that means, this is disabled, since no temperature can
higher than 127 degree in W83792D.
Fan Duty Cycle
Temp. Tolerance
Fan Duty Cycle 100%
Fan Duty Cycle Level 3
Fan Duty Cycle Level 2
Fan Duty Cycle Level 1
Non-Stop Duty Cycle
Temp. 1
Temp.2
Temp.3
Temp.4
Temperature
In Register E0h-EBh defines the relationship of temperature and duty cycle. Also previous Target
Temperature and Non-Stop Duty Cycle are used as Temperature Point 1 and minimum duty cycle.
To prevent FAN Duty Cycle from throttling at Temperature Point, Temperature Tolerances(87h, 97h)
are used to provide a hysterisis mechanism. When temperature is going up (Blue Line), duty cycle
changes only when temperature reaches Temperature Point + Tolerance. On the contrary, when
temperature is going low (Green Line), duty cycle changes only when sensor temperature down to
Temperature Point – Tolerance.
- 53 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
FAN Duty Cycle Level
BIT
NAME
ATTRIBUTE
DESCRIPTION
7-4
Duty Cycle Level 2
R/W
For Smart Fan II mode. The output duty cycle when
temperature is between Temperature point 2 and 3.
3-0
Duty Cycle Level 3
R/W
For Smart Fan II mode. The output duty cycle when
temperature is between Temperature 3 and 4.
FAN Temperature Point
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
Reserved
RO
reserved
6-0
Temperature
R/W
For Smart Fan II mode. Specifies each temperature point
at which the output duty cycle changes.
8.28 Value RAM 2⎯ Index B0h B1h B8h ~ BAh (BANK 0)
MNEMONIC
BANK
INDEX
ATTR
BIT 7
BIT 6
5VSB Readout
0
B0
RO
5VSB Voltage Readout
VBAT Readout
0
B1
RO
VBAT Voltage Readout
FAN4 Readout
0
B8
RO
FAN 4 Count Reading
FAN5 Readout
0
B9
RO
FAN 5 Count Reading
FAN6 Readout
0
BA
RO
FAN 6 Count Reading
FAN7 Readout
0
BE
RO
FAN 7 Count Reading
5VSB Calculation
5VSB Voltage = CR[B0] * 0.024;
VBAT Calculation
VBAT Voltage = CR[B1] * 0.016;
- 54 -
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W83792AD/AG/D/G
8.29 Limit RAM 2--- Index B4h~B7h BBh~BDh (BANK0)
MNEMONIC
BANK
INDEX
ATTR
5VSB High Limit
0
B4
RO
5VSB Low Limit
0
B5
RO
VBAT High Limit
0
B6
RO
VBAT Low Limit
0
B7
RW
FAN4 Limit
0
BB
RW
FAN5 Limit
0
BC
RW
FAN6 Limit
0
BD
RW
FAN7 Limit
0
BF
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
5VSB Voltage High Limit
FFh
5VSB Voltage Low Limit
00h
VBAT Voltage High Limit
FFh
VBAT Voltage Low Limit
00h
FAN 4 Count Low Limit
FFh
FAN 5 Count Low Limit
FFh
FAN 6 Count Low Limit
FFh
FAN 7 Count Low Limit
FFh
5VSB Limit Setup
CR[B4/B5] = [Desired Voltage] / 0.024;
VBAT Limit Setup
CR[B6/B7] = [Desired Voltage] / 0.016;
8.30 Temperature Sensor 2 (First LM75)
MNEMONIC
BANK INDEX ATTR
Temperature 2 Readout
0
C0
RO
Temperature 2 Readout
0
C1
RO
Temperature 2 Config
0
C2
RW
Temperature 2 Thyst High
0
C3
RW
Temperature 2 Thyst Low
0
C4
RW
BIT 7
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Temperature 2
0.5deg
reserve
#of faults
0
0
reserve
0
STOP
0
Temperature 2 Thryst
4Bh
0.5deg
0
- 55 -
Reserve
0
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Temperature Sensor 2 (First LM75), continued.
MNEMONIC
BANK
INDEX
ATTR
BIT 7
BIT 6
BIT 5
Temperature 2 Over High
0
C5
RW
Temperature 2 Over Low
0
C6
RW
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Temperature 2 Over Limit
50h
0.5deg
reserve
0
0
8.31 Temperature (High Byte) Register - Index C0h (Bank 0)
BIT
NAME
7-0
TEMP2<8:1>
ATTRIBUTE
Read Only
DESCRIPTION
Temperature <8:1> of VTIN 2, which is high byte.
8.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index C1h (Bank 0)
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
TEMP2<0>
Read Only
Temperature <0> of VTIN2, which is low byte.
6-0
Reserved
Read Only
Read 0.
8.33 Temperature Sensor 2 Configuration Register - Index C2h (Bank 0)
BIT
NAME
ATTRIBUTE
DESCRIPTION
7-5
Reserved
RO
Reserved
4-3
FAULT
R/W
Number of faults to detect before setting OVT# output to
avoid false tripping due to noise.
2:1
Reserved
0
STOP2
Reserved
R/W
When set to 1 the sensor will stop monitor.
8.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index C3h (Bank 0)
BIT
NAME
ATTRIBUTE
DESCRIPTION
7-0
THYST2<8:1>
R/W
Temperature hysteresis bit 8-1, which is High Byte. The
temperature default 75 degree C.
8.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index C4h (Bank 0)
BIT
NAME
ATTRIBUTE
DESCRIPTION
7
THYST2<0>
R/W
Temperature hysteresis bit 0, which is low Byte.
6-0
Reserved
Read Only
Read 0
- 56 -
W83792AD/AG/D/G
8.36 Temperature Sensor 2 Over-temperature (High Byte) Register -Index C5h
(Bank 0)
BIT
7-0
NAME
TOVF2<8:1>
ATTRIBUTE
DESCRIPTION
R/W
Over-temperature bit 8-1, which is High Byte. The
temperature default 80 degree C.
8.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index
C6h(Bank 0)
BIT
NAME
ATTRIBUTE
7
TOVF2<0>
R/W
6-0
Reserved
DESCRIPTION
Over-temperature bit 0, which is low Byte.
Read Only
Read 0
8.38 Temperature Sensor 3 (Second LM75)
MNEMONIC
BANK INDEX ATTR
Temperature 3 Readout
0
C8
RO
Temperature 3 Readout
0
C9
RO
Temperature 3 Config
0
CA
RW
Temperature 3 Thyst High
0
CB
RW
Temperature 3 Thyst Low
0
CC
RW
Temperature 3 Over High
0
CD
RW
Temperature 3 Over Low
0
CE
RW
BIT 7
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Temperature 3
0.5deg
reserve
#of faults
reserve
STOP
0
0
0
0
Temperature 3 Thryst
4Bh
0.5deg
Reserve
0
0
Temperature 3 Over Limit
50h
0.5deg
Reserve
0
0
8.39 Temperature Sensor 3 Hysteresis (High Byte) Register - Index CBh (Bank 0)
BIT
7-0
NAME
THYST3<8:1>
ATTRIBUTE
R/W
DESCRIPTION
Temperature hysteresis bit 8-1, which is High Byte. The
temperature default 75 degree C.
- 57 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
8.40 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index CCh (Bank 0)
BIT
NAME
ATTRIBUTE
DESCRIPTION
6-0
Reserved
Read Only
Read 0
7
THYST3<0>
R/W
Temperature hysteresis bit 0, which is low Byte.
8.41 Temperature Sensor 3 Over-temperature (High Byte) Register - Index CDh
(Bank 0)
BIT
7-0
NAME
OVTF3<8:1>
ATTRIBUTE
DESCRIPTION
R/W
Over-temperature bit 8-1, which is High Byte. The
temperature default 80 degree C.
8.42 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index
CEh(Bank 0)
BIT
NAME
7
OVTF3<0>
6-0
Reserved
ATTRIBUTE
R/W
DESCRIPTION
Over-temperature bit 0, which is low Byte.
Reserved
- 58 -
W83792AD/AG/D/G
9. ARP (ADDRESS RESOLUTION PROTOCOL) REGISTERS
9.1
Unique Device Identifier (UDID) -- 20h-2Fh (Bank 1)
In order to provide a mechanism to isolate each device for the purpose of address assignment each
device must implement a unique device identifier (UDID).
MNEMONIC
BANK INDEX ATTR
Device Capability
1
20
RO
Version/Revision
1
21
RO
Vendor ID
1
22-23
RO
Device ID
1
24-25
RW
Interface
1
26-27
RW
Subsystem Vendor ID
1
28-29
RW
Subsystem Device ID
1
2A-2B
RW
Vendor specific ID
1
2C-2F
RW
BIT 7
BIT 6
BIT 5
BIT 4
Random Number
1
1
RESERVED
0
0
BIT 3
BIT 2 BIT 1 BIT 0
RESERVED
0
0
0
PEC
0
0
1
SMBUS 2.0 SUPPORT SILICON REVISION
0
0
1
0
1
1
WINBOND PCI SIG VENDOR ID
1050h
DEVICE ID assigned by Manufacturer
0100h
ASF protocol layer interface over SMBus.
0024h
SUBSYSTEM VENDOR
0000h
SUBSYSTEM
0000h
VENDOR SPEC
Random Number
- 59 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
NAME
DESCRIPTIONS
Device
Capabilities
Describes the device’s capabilities. See detail SMBus 2.0.
Version/Rev
ision
UDID version number and silicon revision identification. See detail SMBus2.0.
Vendor ID
The device manufacturer’s ID as assigned by the SBS Implementers’ Forum or the
PCI SIG.
Device ID
The device ID as assigned by the device manufacturer (identified by the Vendor ID
field).
Interface
Identifies the protocol layer interfaces supported over the SMBus connection by the
device. For example, ASF and IPMI.
Subsystem
Vendor ID
This field may hold a value derived from any of several sources:
1. The device manufacturer’s ID as assigned by the SBS Implementers’ Forum or
the PCI SIG.
2. The device OEM’s ID as assigned by the SBS Implementers’ Forum or the PCI
SIG.
3. A value that, in combination with the Subsystem Device ID, can be used to
identify an organization or industry group that has defined a particular common
device interface specification.
Subsystem
Device ID
The subsystem ID identifies a specific interface, implementation, or device. The part
identified by the Subsystem Vendor ID field defines the subsystem ID.
Vendor
Specific ID
A unique number per device. See detail SMBus 2.0.
- 60 -
W83792AD/AG/D/G
10. ASF SENSOR ENVIRONMENTAL EVENT
10.1 Temperature: Get Event Data message
In the W83792D, it has three temperatures for monitoring System Board, CPU1, and CPU2. The listed
table show that have the entity ID, entity instance, event source type, event type, event offset, and so
on.
ASF PACKET
DATA
TEMPERATURE 1
Event sensor
type
0x01 (Temperature sensor)
Event type
Threshold-based: 0x01h.
Event offset
Event Status:
011b (Asserted, Send)
0x01:Threshold-based
(iii)
0x09: Upper critical
going
Upper Temp.
0x01:Threshold-based
0x08: Upper Critical,
going
(Reserved)
(iv)
Event Status:
011b (Asserted, Send)
(ii)
0x01:Threshold-based
0x06 : Upper Non-critical,
going low.
(v)
0x01:Threshold-based
0x07: Upper non-critical
going
Lower Temp
0x01:Threshold-based
(i)
(vi)
0x01:Threshold-based
0x01: Lower Non-critical
Going
(Reserved)
0x00: Lower non-critical,
going
Event Status:
010b (Deasserted, Send)
Event sensor type: 0x01
Event Type: 0x01
Event source
type
The W83792D is complying ASF 2.0.I specification and the value is 0x68.
Sensor device
The ASF specification indicates that the Sensor Device is the SMBus address of the
sensor that caused the event for the PET Frame. Therefore, the Sensor Device of
the W83792D is ARP assigned address.
Sensor number Temperature 1: 0Dh (Don’t use 00h and FFh. Therefore 01h Æ VCOREA).
Temperature 2: 0Eh
Temperature 3: 0Fh
Entity ID
Temperature 1: 07h (System board)
Temperature 2/3: 03h (Processor)
These are defined in Table 6 of PET v1.0 specification. This value is programmable
because that may be used in add-in-card or connected to other device.
- 61 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Temperature: Get Event Data message, continued.
ASF PACKET
DATA
TEMPERATURE 1
Entity instance Temperature 1: 01h (main system board).
Temperature 2: 01h (Processor 1)
Temperature 3: 02h (Processor 2)
These are programmable.
Event status
index
Temperature 1: 0Ch (zero-based)
Temperature 2: 0Dh
Temperature 3: 0Eh
Event status
Status
Value
Status type
Description
0000_0010b Deasserted (send) Refer as above figure.
Byte Count for
GetEventStatus
0Ah
0000_0011b Asserted (send)
W83792D will respond all 0Ah
relative information.
0000_0111b Event Status End
When event status index 02h
is more than 14h, the
machine will be ended the
transmission.
Event Severity Monitor (0x01): That is represented the monitored temperature is under the lower
temperature.
Non Critical (0x08): that is represented the temperature is located between the lower
and upper temperature.
Critical Condition (0x10): that is represented the monitored temperature is over the
upper temperature.
Critical Condition (0x10)
Upper Temp.
Non Critical (0x08)
Lower Temp.
Monitor (0x01)
- 62 -
W83792AD/AG/D/G
Event Offset, Type and Severity
DESCRIPTION
SENSOR
TYPE
EVENT
TYPE
EVENT
OFFSET
STATUS
EVENT SEVERITY
TEMPERATURE SENSORS
Upper-Critical
Going High
09h
Upper-Critical
Going Low
08h
Upper-Non-critical
Going High
Upper-Non-critical
Going Low
10h
Critical
3h
01h
01h
Temperature
ThresholdBased
Assert
07h
08h
Non-critical
06h
Lower-Non-critical
Going High
01h
Lower-Non-critical
Going Low
00h
2h
01h
Deassert
Monitor
VOLTAGE SENSORS
Generic Over
Voltage Problem
Normal Voltage
Generic Under
Voltage Problem
02h
Voltage
07h
02h
3h
10h
GenericSeverity
07h
2h
01h
02h
3h
10h
07h
2h
01h
02h
3h
10h
FAN SENSORS
Normal FAN Speed
Generic FAN
Failure
04h
07h
Fan
CASEOPEN
Case Intruded
05h
6Fh
00h
3h
10h
Case Normal
Physical
Security
Sensor
Specific
80h
2h
01h
01h
3h
10h
81h
2h
01h
THERMAL TRIP SENSORS
Thermal Trip
Occurs
No Thermal Trip
07h
Processor
6Fh
- 63 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Entity ID and Instance (Default):
ENTITY ID
SENSOR IN
W83792D
EVENT
STATUS
INDEX
EVENT
NUMBER
EVENT SENSOR
TYPE
01h
VIN0
02h
03h
02h (Voltage)
02h
VIN1
03h
04h
02h
03h
VIN2
04h
05h
02h
04h
VIN3
05h
06h
02h
05h
5VDD
06h
07h
02h
06h
VSB
07h
08h
02h
07h
VBAT
08h
09h
02h
01h
02h
03h
04h
01h
01h
01h
01h
02h
02h
02h
01h
02h
FAN1
FAN4
FAN5
FAN6
Temperature1
VCOREA
FAN2
Temperature 2
VCOREB
FAN3
Temperature 3
Thermal Trip 1
Thermal Trip 2
09h
0Fh
10h
11h
0Ch
00h
0Ah
0Dh
01h
0Bh
0Eh
12h
13h
0Ah
10h
11h
12h
0Dh
01h
0Bh
0Eh
02h
0Ch
0Fh
13h
14h
04h (Fan)
04h
04h
04h
01h (Temperature)
02h
04h
01h
02h
04h
01h
07h (Processor)
07h (Processor)
01h
Case Intrusion
14h
15h
05h (Physical
Security)
ENTITY INSTANCE
(PROGRAMMABLE) (PROGRAMMABLE)
07h (System Board)
03h (Processor)
23h
(System Chassis)
- 64 -
W83792AD/AG/D/G
10.2 Voltage: Get Event Data message
In the W83792D, it has nine voltage inputs for monitoring System Board, CPU1, and CPU2. The listed
table show that have the entity ID, entity instance, event source type, event type, event offset, and so
on.
ASF PACKET
DATA
VOLTAGE INPUT
Event sensor type 02h (Voltage sensor)
Event type
Discrete (Generic Severity): 07h
Event offset
07h: Discrete (Generic Severity)
(i)
02h: Transition to Critical
from less severe
Event Status: 011b (Asserted, send)
High voltage
07h: Discrete (Generic Severity)
07h: Monitor
Event Status: 010b (Deasserted, send)
Low voltage
07h: Discrete (Generic Severity)
(ii)
02h: Transition to Critical
from less severe
Event Status: 011b (Asserted, send)
Event sensor type: 02h (Voltage)
Event Type: 07h (Discrete, Generic Severity)
Event source type The W83792D is complying ASF 2.0.I specification and the value is 0x68.
Sensor device
The ASF specification indicates that the Sensor Device is the SMBus address of
the sensor that caused the event for the PET Frame. Therefore, the Sensor
Device of the W83792D is ARP assigned address.
Sensor number
The number is shown as following:
Voltage Sensor
Sensor Number
VCOREA
01h
VCOREB
02h
VIN0
03h
VIN1
04h
VIN2
05h
VIN3
06h
5VDD
07h
VSB
08h
VBAT
09h
- 65 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Voltage: Get Event Data message, continued.
ASF PACKET
DATA
Entity ID
VOLTAGE INPUT
The Entity ID is shown as following.
Voltage Sensor
Entity ID
VCOREA
03h (Processor)
VCOREB
07h (System board)
VIN0
VIN1
VIN2
VIN3
5VDD
VSB
VBAT
These ID are defined in Table 6 of PET v1.0 specification. This value is
programmable because that may be used in add-in-card or connected to other
device.
Entity instance
The Entity Instance is shown as following.
Sensor
Entity Instance
VCOREA
01h
VCOREB
02h
VIN0
01h
VIN1
02h
VIN2
03h
VIN3
04h
5VDD
05h
VSB
06h
VBAT
07h
Event status index VCOREA: 00h
VCOREB: 01h
VIN0: 02h
VIN1: 03h
VIN2: 04h
VIN3: 05h
5VDD: 06h
VSB: 07h
VBAT: 08h
- 66 -
W83792AD/AG/D/G
Voltage: Get Event Data message, continued.
ASF PACKET
DATA
Event status
Event Severity
VOLTAGE INPUT
Status
Value
0000_0010b
0000_0011b
Status type
Description
Desserted (send)
Asserted (send)
Byte
Count
0Ah
0Ah
W83792D will respond all
relative information.
0000_0111b Event Status End When event status index
02h
is more than 0Fh, the
machine will be ended the
transmission.
Monitor (0x01): That is represented the monitored voltage is during the limit value.
Critical Condition (0x10): that is represented the monitored voltage is over the
limit value.
Critical Condition (0x10)
Upper Volt.
Monitor (0x01)
Lower Volt.
Critical Condition (0x10)
10.3 Fan: Get Event Data message
In the W83792D, it has Six Fan tachometers for monitoring System Board, CPU1, and CPU2. The
listed table show that have the entity ID, entity instance, event source type, event type, event offset,
and so on.
ASF PACKET
DATA
FAN CLOCK INPUT
Event sensor type 04h (Fan speed sensor)
Event type
Discrete (Generic Severity): 07h
07h: Discrete
07h: Monitoring
Event Status: 010b (Deasserted, send)
High Speed (Low Count)
Fan Limit
Lower Speed (High Count) Event Status: 011b (Asserted, send)
07h: Discrete
02h: Transition from less severe to critical
Event sensor type: 04h
Event Type: 07h Discrete
- 67 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Fan: Get Event Data message, continued.
ASF PACKET
DATA
FAN CLOCK INPUT
Event source type The W83792D is complying ASF 2.0.I specification and the value is 0x68.
Sensor device
The ASF specification indicates that the Sensor Device is the SMBus address of
the sensor that caused the event for the PET Frame. Therefore, the Sensor Device
of the W83792D is ARP assigned address.
Sensor number
The number is shown as following:
Entity ID
Fan Sensor
Sensor Number
FAN 1
0Ah
FAN 2
0Bh
FAN 3
0Ch
FAN 4
11h
FAN 5
12h
FAN 6
13h
The Entity ID is shown as following.
Voltage Sensor
Entity ID (default)
FAN 1
07h (System board)
FAN 2
03h (Processor)
FAN 3
FAN 4
07h
FAN 5
FAN 6
These ID are defined in Table 6 of PET v1.0 specification. This value is
programmable because that may be used in add-in-card or connected to other
device.
Entity instance
The Entity Instance is shown as following.
Fan Sensor
Entity Instance (default)
FAN 1
01h (Main system board)
FAN 2
01h (Processor 1)
FAN 3
02h (Processor 2)
FAN 4
02h (Main system board)
FAN 5
03h (Main system board)
FAN 6
04h (Main system board)
- 68 -
W83792AD/AG/D/G
Fan: Get Event Data message, continued.
ASF PACKET
DATA
Event
index
FAN CLOCK INPUT
status FAN1 : 0Ah
FAN2 : 0Bh
FAN3 : 0Ch
Event status
Status
Value
Status type
Description
0000_0010b
Byte
Count
0Ah
Deasserted (send)
0000_0011b Asserted (send)
W83792D will respond all 0Ah
relative information.
0000_0100b Disabled
FAN 6 also supports Watch
Dog Timer function. ASF
return disabled when the pin
switch to Watch Dog
Function.
0000_0111b Event Status End
02h
02h
When event status index is
more than 0Fh, the machine
will be ended the
transmission.
Event Severity
Monitor (0x01): That is represented the monitored fan count is under the limit
count.
Critical Condition (0x10): that is represented the monitored fan count is over the
limit count.
Monitor (0x01)
Upper Speed
Fan Speed
Lower Speed
Critical Condition (0x10)
- 69 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
10.4 Case Intrusion: Get Event Data message
In the W83792D, it has one chassis intrusion monitoring for System Board. The listed table shows the
entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET
DATA
CASE INTRUSION INPUT
Event sensor type 05h (Chassis Intrusion)
Event type
Sensor Specific : 6Fh
Logic High
Event type: 6Fh
Event offset: 80h (Deassert)
Event type: 6Fh
Event offset: 00h (Asserted)
Event Status: 010b (Deasserted, send)
Event Status: 011b (Asserted, send)
Logic Low
Event sensor type: 05h (Physical security)
Event Type: 6Fh ( Sensor specific)
Event source type The W83792D is complying ASF 2.0.I specification and the value is 0x68.
Sensor device
The ASF specification indicates that the Sensor Device is the SMBus address of
the sensor that caused the event for the PET Frame. Therefore, the Sensor Device
of the W83792D is ARP assigned address.
Sensor number
The sensor number for case intrusion is 15h
Entity ID
The Entity ID is 23h for case intruded
These ID are defined in Table 28-11 of IPMI v1.0 specification. This value is
programmable because that may be used in add-in-card or connected to other
device.
Entity instance
The Entity Instance is 01h for (Main system board)
Event
status 0x14 (W83792D sensor index)
index
Event status
Status
Status type
Description
Byte
Value
Count
0000_0010b Deasserted (send)
0Ah
0000_0011b Asserted (send)
W83792D will respond all 0Ah
relative information.
0000_0111b Event Status End When event status index 02h
is more than 0Fh, the
machine will be ended the
transmission.
- 70 -
W83792AD/AG/D/G
Case Intrusion: Get Event Data message, continued.
ASF PACKET
DATA
Event Severity
CASE INTRUSION INPUT
Monitor (0x01): That is represented the monitored CASEOPEN is logic Low
Critical Condition (0x10): that is represented the monitored CASEOPEN is logic
High.
Logic High
Monitor (0x01)
Critical Condition (0x10)
Logic Low
Case Intruded Input Pin
10.5 Thermal Trip: Get Event Data message
In the W83792D, it has two thermal trip monitoring for System Board. The listed table shows the
entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET
DATA
THERMAL TRIP INPUT
Event sensor type 07h (Processor related event)
Event type
Sensor Specific : 6Fh
Logic High
Event type: 6Fh
Event offset: 81h (Deassert)
Event type: 6Fh
Event offset: 01h (Asserted)
Event Status: 010b (Deasserted, send)
Event Status: 011b (Asserted, send)
Logic Low
Event sensor type: 07h (Processor)
Event Type: 6Fh ( Sensor specific)
Event source type The W83792D is complying ASF 2.0.I specification and the value is 0x68.
Sensor device
The ASF specification indicates that the Sensor Device is the SMBus address of
the sensor that caused the event for the PET Frame. Therefore, the Sensor Device
of the W83792D is ARP assigned address.
Sensor number
The sensor number for thermal trip 1 is 13h ; 14h for thermal trip 2.
Entity ID
The Entity ID is 3h for thermal trip.
These ID are defined in Table 6 of PET v1.0 specification. This value is
programmable because that may be used in add-in-card or connected to other
device.
- 71 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Thermal Trip: Get Event Data message, continued.
ASF PACKET
DATA
THERMAL TRIP INPUT
Entity instance
The Entity Instance is 01h for Thermal Trip 1. 02h for thermal trip 2.
Event
index
0x13 (Thermal Trip 2)
status 0x12 (Thermal Trip 1)
Event status
Status
Value
Status type
Description
0000_0010b
Byte
Count
0Ah
Deasserted (send)
0000_0011b Asserted (send)
W83792D will respond all 0Ah
relative information.
0000_0111b Event Status End
02h
When event status index
is more than 0Fh, the
machine will be ended the
transmission.
Event Severity
Monitor (0x01): That is represented the monitored Thermal trip is logic Low
Critical Condition (0x10): that is represented the monitored Thermal Trip has been
logic High.
Logic High
Monitor (0x01)
Critical Condition (0x10)
Logic Low
Case Intruded Input Pin
Once W83792D detects thermal trip event, it will report to host polling. Thermal Trip event can only be
cleared by CLR_TT, the event itself is latched by VBAT power.
- 72 -
W83792AD/AG/D/G
10.6 ASF Response Registers -- 40h-7Fh (Bank 1)
10.6.1 ASF Critical/non-critical Temperature Registers:
These registers shall never assign negative temperature.
Generic/Upper/Under temperature
MNEMONIC
BANK
INDEX
ATTR
Temp 1 Noncritical
1
40
RW
Temp 1 Critical
1
41
RW
Temp 2 Noncritical
1
42
RW
Temp 2 Critical
1
43
RW
Temp 3 Noncritical
1
44
RW
Temp 3 Critical
1
45
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Temp 1 Noncritical
4Bh
Temp 1 Critical
50h
Temp 2 Noncritical
4Bh
Temp 2 Critical
50h
Temp 3 Noncritical
4Bh (75 DEGREE)
Temp 3 Critical
50h (80 DEGREE)
10.6.2 Sensor device: (SMBus Address, Read/Write)
MNEMONIC
BANK
INDEX
ATTR
ASF Address
1
4F
RO
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 1
BIT 0
SMBus address assigned by ARP
00h
10.6.3 Relative Entity ID Table
MNEMONIC
BANK
INDEX
ATTR
Vcore A Entity ID
1
50
RW
Vcore B Entity ID
1
51
RW
VIN0 Entity ID
1
52
RW
VIN1 Entity ID
1
53
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Vcore A Entity ID
3(CPU)
Vcore B Entity ID
3(CPU)
VIN0 Entity ID
7(System)
VIN1 Entity ID
7(System)
- 73 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Relative Entity ID Table, continued
MNEMONIC
BANK
INDEX
ATTR
VIN2 Entity ID
1
54
RW
VIN3 Entity ID
1
55
RW
5VCC Entity ID
1
56
RW
VSB Entity ID
1
57
RW
VBAT Entity ID
1
58
RW
FAN 1 Entity ID
1
59
RW
FAN 2 Entity ID
1
5A
RW
FAN 3 Entity ID
1
5B
RW
FAN 4 Entity ID
1
5C
RW
FAN 5 Entity ID
1
5D
RW
FAN 6 Entity ID
1
5E
RW
Chassis Entity ID
1
5F
RW
Temp 1 Entity ID
1
60
RW
Temp 2 Entity ID
1
61
RW
Temp 3 Entity ID
1
62
RW
FAN7 Entity ID
1
63
RW
BIT 7
BIT 6
BIT 5
BIT 4 BIT 3 BIT 2
VIN2 Entity ID
7(System)
VIN3 Entity ID
7(System)
5VCC Entity ID
7(System)
VSB Entity ID
7(System)
VBAT Entity ID
7(System)
FAN 1 Entity ID
7(System)
FAN 2 Entity ID
3(CPU)
FAN 3 Entity ID
3(CPU)
FAN 4 Entity ID
7(SYSTEM)
FAN 5 Entity ID
7(SYSTEM)
FAN 6 Entity ID
7(SYSTEM)
Chassis Entity ID
23(Chassis)
Temp 1 Entity ID
7(SYSTEM)
Temp 2 Entity ID
3(CPU)
Temp 3 Entity ID
3(CPU)
FAN7 Entity ID
7(SYSTEM)
Table of Entity ID defined in PET 1.0 or IPMI 1.0
ENTITY DEFINITION
ENTITY ID
CPU
3
System
Memory module
System Chassis
Fan/Cooling device
7
8
23
29
Memory device
32
- 74 -
BIT 1
BIT 0
W83792AD/AG/D/G
10.6.4 Entity Instance Register
Maximum number of instance is 15
MNEMONIC
ENTITY INSTANCE I
ENTITY INSTANCE II
ENTITY INSTANCE III
ENTITY INSTANCE IV
ENTITY INSTANCE V
ENTITY INSTANCE VI
ENTITY INSTANCE VII
ENTITY INSTANCE VIII
ENTITY INSTANCE IX
ENTITY INSTANCE X
ENTITY INSTANCE XI
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Vcore B
Vcore A
1
70
RW
2 (CPU B)
1 (CPU A)
VIN1
VIN0
1
71
RW
2 (SYSTEM 1)
1 (SYSTEM 1)
VIN3
VIN2
1
72
RW
4 (SYSTEM 1)
3(SYSTEM 1)
VSB
5VCC
1
73
RW
6(SYSTEM 1)
5 (SYSTEM 1)
FAN1
VBAT
1
74
RW
1 (SYSTEM 1)
7 (SYSTEM 1)
FAN3
FAN2
1
75
RW
2 (CPU B)
1 (CPU A)
TEMP2
TEMP1
1
76
RW
1 (CPU A)
1 (SYSTEM 1)
FAN4
TEMP3
1
77
RW
2 (SYSTEM 1)
2 (CPU B)
FAN6
FAN5
1
78
RW
4 (SYSTEM 1)
3(SYSTEM 1)
FAN7
CHASSIS
1
79
RW
5(SYSTEM 1)
1 (SYSTEM Chassis)
THERMALTRIP2
THERMALTRIP1
1
7A
RW
2
1
The Entity for a given event varies according to what entity the environmental sensor is monitoring.
For example, a typical managed system board can have temperature monitoring associated with the
system board and with the main processor. Thus, the Entity IDs and Entity Instance values for these
would be Entity ID=7, Entity Instance=1 for ‘main system board’ and Entity ID=3, Entity Instance=1 for
‘processor 1’, respectively.
- 75 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
10.6.5 Remote Control Configuration Registers
MNEMONIC
BANK INDEX ATTR BIT 7 BIT 6 BIT 5
Remote Power On Command
1
7D
RW
Remote Power Down Command
1
7E
RW
Remote Reset Command
1
7F
RW
Remote Power on Control
1
7C
RW
BIT 4
BIT 3 BIT 2 BIT 1 BIT 0
11h
12h
AV
0
10h
AR ASF_TM DIS_RMC
0
0
0
PWR1T
0
Reset Condition: Resume Reset
These registers define the Remote control command for each remote control function.
When Remote Power on command received by W83792D, PWRBTN# will be asserted for 100ms
every 1sec if PWR1T is clear to 0, the process will continue until 5VCC is detected as high. If PWR1T
is set to 1, PWRBTN# will be asserted only once, no matter 5VCC is high or low.
ASF_TM is ASF test mode in production test. We strongly recommend you not to use this in normal
operation.
Notice: User should avoid continuously sending Remote Control Command. If last Remote Command
execution is not complete, and next remote command comes in. W83792D ignores (blocks) next
remote command, and complete the first one only.
- 76 -
W83792AD/AG/D/G
11. ELECTRICAL CHARACTERISTICS
11.1 Absolute Maximum Ratings
PARAMETER
Power Supply Voltage(Storage)
Power Supply Voltage(Operate)
Input Voltage
Operating Temperature
Storage Temperature
RATING
UNIT
-0.5 to 7.0
4.5 to 5.5
-0.5 to VDD+0.5
0 to +70
-55 to +150
V
V
V
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
11.2 DC Characteristics
(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Input High Leakage
ILIH
Input Low Leakage
ILIL
0.8
2.0
V
V
0.4
V
IOL = 12 mA
V
IOH = - 12 mA
+10
μA
VIN = VDD
-10
μA
VIN = 0V
2.4
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger
level input
Input Low Threshold
Voltage
Vt-
0.5
0.8
1.1
V
VDD = 5 V
Input High Threshold
Voltage
Vt+
1.6
2.0
2.4
V
VDD = 5 V
Hysteresis
VTH
0.5
1.2
V
VDD = 5 V
Output Low Voltage
VOL
V
IOL = 12 mA
Output High Voltage
VOH
V
IOH = - 12 mA
Input High Leakage
ILIH
+10
μA
VIN = VDD
Input Low Leakage
ILIL
-10
μA
VIN = 0V
0.4
2.4
- 77 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
DC Characteristics, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
OUT12t - TTL level output pin with source-sink capability of 12 mA
Output Low
Voltage
VOL
Output High
Voltage
VOH
0.4
2.4
V
IOL = 12 mA
V
IOH = -12 mA
OD8 - Open-drain output pin with sink capability of 8 mA
Output Low
Voltage
VOL
0.4
V
IOL = 8 mA
OD12 - Open-drain output pin with sink capability of 12 mA
Output Low
Voltage
VOL
0.4
V
IOL = 12 mA
OD48 - Open-drain output pin with sink capability of 48 mA
Output Low
Voltage
VOL
0.4
V
0.8
V
IOL = 48 mA
INt - TTL level input pin
Input Low Voltage
VIL
Input High Voltage
VIH
Input High Leakage
ILIH
+10
μA
VIN = VDD
Input Low Leakage
ILIL
-10
μA
VIN = 0 V
INts
2.0
V
- TTL level Schmitt-triggered input pin
Input Low
Threshold Voltage
Vt-
0.5
0.8
1.1
V
VDD = 5 V
Input High
Threshold Voltage
Vt+
1.6
2.0
2.4
V
VDD = 5 V
Hysteresis
VTH
0.5
1.2
V
VDD = 5 V
Input High Leakage
ILIH
+10
μA
VIN = VDD
Input Low Leakage
ILIL
-10
μA
VIN = 0 V
- 78 -
W83792AD/AG/D/G
11.3 AC Characteristics
11.3.1 Serial Bus Timing Diagram
t
SCL
t
t
R
R
SCL
t HD;SDA
t
t
SU;DAT
SU;STO
VALID DATA
SDA IN
t
HD;DAT
SDA OUT
Serial Bus Timing Diagram
Serial Bus Timing
PARAMETER
SYMBOL
-
MIN.
MAX.
UNIT
SCL clock period
t SCL
10
uS
Start condition hold time
tHD;SDA
4.7
uS
Stop condition setup-up time
tSU;STO
4.7
uS
DATA to SCL setup time
tSU;DAT
120
nS
DATA to SCL hold time
tHD;DAT
5
nS
SCL and SDA rise time
tR
1.0
uS
SCL and SDA fall time
tF
300
nS
MAX.
UNIT
0.8
uS
11.3.2 VID Input Skew
t skew
t hold
VIDA[5:0]/VIDB[5:0]
VALID VID
VALID VID
VID Input Timing
PARAMETER
SYMBOL
MIN.
-
VID Input Unstable Time
t Skew
VID Valid Input Hold Time
t-hold
- 79 -
4
uS
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
12. THE TOP MARKING
The top marking of W83792D
inbond
W83792D
2326952Z - 91
333GCSB
First Line
Winbond Logo.
Second Line
The chip part number: W83792D, D means LQFP package.
Third Line
Fourth Line
Serial number
Tracking Code: 3 33 G C SB For Package information
Package was made in 2003
3
33
G
C
Week: 33
Assembly house ID; G means Greatek; A means ASE; O means OSE
The IC version
SB
The Mask version
The top marking of W83792G
inbond
W83792G
2326952Z - 91
333GCSB
First Line
Winbond Logo.
Second Line
The chip part number: W83792G, G means Pb-free package.
Third Line
Fourth Line
Serial number
Tracking Code: 3 33 G C SB For Package information
Package was made in 2003
3
33
G
C
SB
Week: 33
Assembly house ID; G means Greatek; A means ASE; O means OSE
The IC version
The Mask version
- 80 -
W83792AD/AG/D/G
The top marking of W83792AD
inbond
W83792AD
2326952Z - 91
333GCSB
First Line
Winbond Logo.
Second Line
The chip part number: W83792AD, D means LQFP package.
Third Line
Serial number
Fourth Line
Tracking Code: 3 33 G C SB For Package information
3
Package was made in 2003
33
Week: 33
G
Assembly house ID; G means Greatek; A means ASE; O means OSE
C
The IC version
SB
The Mask version
The top marking of W83792AG
inbond
W83792AG
2326952Z - 91
333GCSB
First Line
Winbond Logo.
Second Line
The chip part number: W83792AG, G means Pb-free package.
Third Line
Serial number
Fourth Line
Tracking Code: 3 33 G C SB For Package information
3
Package was made in 2003
33
Week: 33
G
Assembly house ID; G means Greatek; A means ASE; O means OSE
C
The IC version
SB
The Mask version
- 81 -
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
13. ACKAGE SPECIFICATION
(48-pin LQFP)
HD
D
25
36
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
24
37
E
HE
13
48
1
e
b
12
0
Dimension in inch
Min.
Nom.
Max.
Dimension in mm
Min.
Nom.
Max.
---
---
1.60
0.05
---
0.15
1.35
1.40
1.45
0.17
0.20
0.27
0.09
---
0.20
7.00
7.00
0.50
9.00
9.00
0.45
0.60
---
0.08
---
0
3.5
7
Notes:
c
A2
Seating Plane
See Detail F
A1
y
A
L
L1
- 82 -
Detail F
0.75
1.00
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
W83792AD/AG/D/G
14. W83792AD/AG APPLICATION CIRCUIT
5VSB
3.3VSB
Select VID Table
R4
R3
4.7K
5VSB
100k
FANOUT3
Select I2C ADD
36
35
34
33
32
31
30
29
28
27
26
25
3VSB
VCOREA
VCOREB
VIN0
VIN1
VIN2
VIN3
VBAT
CASEOPEN
VRM_EN
GND
NC
THERMTRIP1#
5VCC
5VSB
100k
FAN_OUT1
R13
100k
FAN_OUT2
R11
R12
4.7K
4.7K VREF
VTIN3
VTIN2
VTIN1
SMI#
OVT#
FAN_OUT1(A0=1)
792D(0X5A)
T2(0x92)
T3(0x9A)
792D(0X5E)
T2(0x96)
T3(0x9E)
W 83792AD
+5VSB
PWRBTN#
SDA
SCL
FANIN1
FANIN2
FANIN3
CLK
FAN_OUT1/A0
FAN_OUT2/A1
FAN_OUT3/VID90_10
VDD
CSB Version
VIDA0/GPOA4
VIDA1/GPOA5
VIDA2/GPOA6
VIDA3/GPOA7
VIDA4/GPOB0
VIDA5/GPOB1
GPOB2
GPOB3
GPOB4
GPOB5
GPOB6
GPOB7
792D(0X5C)
T2(0x94)
T3(0x9C)
FANOUT4
FANIN4
FANOUT5
FANIN5
FANOUT6
FANIN6
VREF
VTIN3
VTIN2
VTIN1
SMI#/IRQ
OVT#
FAN_OUT4/GPIOA0
FANIN4/GPIOA1
FAN_OUT5/GPIOA2
FANIN5/GPIOA3
WDTRST#/FAN_OUT6
SY SRSTIN#/FANIN6
R9
4.7K
24
23
22
21
20
19
18
17
16
15
14
13
5VSB
SDA
SCL
FANIN1
FANIN2
FANIN3
14.318CLK
FANOUT1
FANOUT2
FANOUT3
PWRBTN#
C1
10u/16V
C2
0.1u
CPUDL1
5VCC
INDUCTOR
C3
10u/16V
C4
0.1u
CPUD-
1
2
3
4
5
6
7
8
9
10
11
12
FAN_OUT2(A1=1)
792D(0X58)
T2(0x90)
T3(0x98)
37
38
39
40
41
42
43
44
45
46
47
48
VIDA0
VIDA1
VIDA2
VIDA3
VIDA4
VIDA5
FAN_OUT1(A0=0)
FAN_OUT2(A1=0)
CPUD-
VCOREA
VCOREB
VIN0
VIN1
VIN2
VIN3
VABT
CASEOPEN
R8
10K
Pull High : Old table(VRM9.X)
Pull Low : New table(VRD10.0)
R10
SMSDA
330
CPUA_TTP#
R7
R5
VRM_EN
FANOUT3
4.7K
SMCLK
SCL
100k
R2
4.7K
SDA
5VSB
R6
R1
330
L2
INDUCTOR
Y1
OUT
8
14.318CLK
14.318M hz
CPUD-
Title
- 83 -
W83792AD Application Circuit
Size
Document Number
Date:
Thursday , Nov ember 10, 2005
Rev
0.6
Sheet
1
of
4
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Temperature
Sensing
T
10K 1%
THERMISTOR
R17
RT2
T
RT1
10K 1%
10K 1%
THERMISTOR
R19
RT3
10K 1%
THERMISTOR
VTIN1
VTIN2
VTIN3
R15
(for system)
10K 1%
T
VREF
Voltage Sensing
R14
R16
CPUB
(for cpu1)
10K 1%
10K
VCOREA
CPUA
R18
+3.3V
(for cpu2)
+5V
R20
10K
VCOREB
10K 1%
34K 1%
R21
VIN0
50K 1%
CPUD-
CPUD-
Case Open Circuits
VIN1
Measuring CPU temperature by either
thermistor or diode.
VBAT
S1
CASEOPEN
R22
10K 1%
R23
232K 1%
-12V
CASEOPEN SW
R24
VREF
R25
VIN2
15K 1%
(from CPU)
3300p
CPUD-
VREF
D+
VTIN2
D-
C5
10M
R26
10K 1%
R27
120K 1%
-5V
VIN3
VID Circuit
CPUAVID5
CPUAVID4
CPUAVID3
CPUAVID2
CPUAVID1
CPUAVID0
R28
R29
R30
R31
R32
R33
1K
1K
1K
1K
1K
1K
VIDA5
VIDA4
VIDA3
VIDA2
VIDA1
VIDA0
(From CPUA)
Title
- 84 -
W83792AD H/W Sensing Circuit
Size
Document Number
Date:
Thursday , Nov ember 10, 2005
Rev
0.6
Sheet
2
of
4
W83792AD/AG/D/G
+12V
R35
1K
PWM FAN OUTPUT
Q1
PNP
3906
FANOUT1
PWMOUT1
+
C6
Q2
MOSFET N
2N7002
510
LM358
R36
470K 2
R38
10K
U2A
Q3 P DGS TO-1
+
10u
1
FANOUT1
R37
DC FAN OUTPUT
+12V
3
4.7K
-
R34
DCOUT1
R39
6.49K
+12V
R40
4.7K
R41
1K
Q3
PNP
3906
+12V
PWMOUT2
C7
Q4
MOSFET N
2N7002
510
+
10u
FANOUT2
LM358
R43 470K
3
R42
-
FANOUT2
2
+
Q7 P DGS TO-1
R44
10K
1
U3A
DCOUT2
R45
6.49K
+3.3V
DCOUT1
R46
0
PWMOUT1
R48
0
D1
1N4148
R47
4.7K
JP1
FANIN1
3
2
1
HEADER 3
R63, R66 FOR DC FAN
R65, R68 FOR PWM FAN
+3.3V
DCOUT2
PWMOUT2
R49
R51
D2
1N4148
0
0
R50
4.7K
JP2
3
2
1
FANIN2
HEADER 3
Title
Size
Date:
- 85 -
W83792AD FAN OUTPUT CIRCUIT
Document Number
Thursday , Nov ember 10, 2005
Rev
0.6
Sheet
3
of
4
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
R59
FANOUT1
VCC12
1
100K
C8
0.1U
Q6
N DGS TO-252
2
3
C9
10n
R60
R61 10K
FANOUT2
DCOUT1
1
C11
C12
0.1U
0.1U
2
3
C13 0.1U
4
5
6
C15
7
U6
FAN1_IN
FAN1_DRV
FAN2_IN
FAN1_SEN
VCC12
FAN2_DRV
C1
FAN2_SEN
C2
FAN3_DRV
CHRPMP
FAN3_SEN
GND
FAN3_IN
W83391TS
C10
VCC12
13
12
Q7
N DGS TO-252
2
11
C14
10n
10
9
470u
R63 10K
8
DCOUT2
R64
6.49K
C16
VCC12
470u
1
0.1U
14
1
100K
R62
6.49K
3
VCC12
R65
Q8
N DGS TO-252
C17
10n
100K
3
2
FANOUT3
C18
0.1U
R66 10K
DCOUT3
R67
6.49K
C19
470u
Title
Size
B
Date:
- 86 -
W83792D with W83391TS FAN OUTPUT CIRCUIT
Document Number
<Doc>
Thursday , Nov ember 17, 2005
Rev
0.6
Sheet
4
of
4
W83792AD/AG/D/G
15. W83792D/G APPLICATION CIRCUIT
5VSB
Select VID Table
R3
R2
4.7K
4.7K
SMSDA
SDA
5VSB
R5
R1
330
100k
SMCLK
SCL
3.3VSB
R4
330
FANOUT3
R7
R6
4.7K
100k
FANOUT3
Select I2C ADD
5VSB
100k
FAN_OUT1
R12
100k
FAN_OUT2
R10
R11
4.7K
4.7K VREF
VTIN3
VTIN2
VTIN1
SMI#
OVT#
FAN_OUT1(A0=1)
792D(0X5A)
T2(0x92)
T3(0x9A)
792D(0X5E)
T2(0x96)
T3(0x9E)
+5VSB
PWRBTN#
SDA
SCL
FANIN1
FANIN2
FANIN3
CLK
FAN_OUT1/A0
FAN_OUT2/A1
FAN_OUT3/VID90_10
VDD
CSB Version
VIDA0/GPOA4
VIDA1/GPOA5
VIDA2/GPOA6
VIDA3/GPOA7
VIDA4/GPOB0
VIDA5/GPOB1
VIDB0/GPOB2
VIDB1/GPOB3
VIDB2/GPOB4
VIDB3/GPOB5
VIDB4/GPOB6
VIDB5/GPOB7
792D(0X5C)
T2(0x94)
T3(0x9C)
W83792D
R8
4.7K
24
23
22
21
20
19
18
17
16
15
14
13
5VSB
SDA
SCL
FANIN1
FANIN2
FANIN3
14.318CLK
FANOUT1
FANOUT2
FANOUT3
PWRBTN#
C1
10u/16V
C2
0.1u
CPUDL1
5VCC
INDUCTOR
C3
10u/16V
C4
0.1u
CPUD-
1
2
3
4
5
6
7
8
9
10
11
12
FAN_OUT2(A1=1)
792D(0X58)
T2(0x90)
T3(0x98)
FANOUT4
FANIN4
FANOUT5
FANIN5
FANOUT6
FANIN6
VREF
VTIN3
VTIN2
VTIN1
SMI#/IRQ
OVT#
FAN_OUT4/GPIOA0
FANIN4/GPIOA1
FAN_OUT5/GPIOA2
FANIN5/GPIOA3
WDTRST#/FAN_OUT6
SY SRSTIN#/FANIN6
VIDA0
VIDA1
VIDA2
VIDA3
VIDA4
VIDA5
VIDB0
VIDB1
VIDB2
VIDB3
VIDB4
VIDB5
FAN_OUT1(A0=0)
FAN_OUT2(A1=0)
37
38
39
40
41
42
43
44
45
46
47
48
VCOREA
VCOREB
VIN0
VIN1
VIN2
VIN3
VBAT
CASEOPEN
VRM_EN/FANOUT7
GND
THERMTRIP2#
THERMTRIP1#/FANIN7
36
35
34
33
32
31
30
29
28
27
26
25
3VSB
5VCC
R9
CPUDCPUB_TTP#
CPUA_TTP#
VCOREA
VCOREB
VIN0
VIN1
VIN2
VIN3
VABT
CASEOPEN
VRM_EN
Pull High : Old table(VRM9.X)
Pull Low : New table(VRD10.0)
L2
INDUCTOR
Y1
OUT
8
14.318CLK
14.318M hz
CPUD-
Title
- 87 -
W83792D Application Circuit
Size
Document Number
Date:
Thursday , Nov ember 10, 2005
Rev
0.6
Sheet
1
of
4
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
Voltage Sensing
Temperature
Sensing
THERMISTOR
RT2
10K 1%
THERMISTOR
R18
RT3
10K 1%
THERMISTOR
T
T
R13
10K 1%
R16
VTIN1
VTIN2
VTIN3
10K 1%
(for system)
10K 1%
T
VREF
RT1
R15
CPUB
(for cpu1)
10K 1%
R14
CPUA
R17
+3.3V
(for cpu2)
+5V
R19
10K
VCOREA
10K
VCOREB
10K 1%
34K 1%
R20
VIN0
50K 1%
CPUD-
CPUD-
Case Open Circuits
VIN1
Measuring CPU temperature by either
thermistor or diode.
VBAT
S1
CASEOPEN
R21
VREF
R22
232K 1%
-12V
CASEOPEN SW
R23
R24
15K 1%
10M
(from CPU)
3300p
C5
VIN2
VREF
D+
VTIN2
CPUD-
10K 1%
R25
D-
10K 1%
R26
120K 1%
-5V
VIN3
VID Circuit
CPUAVID5
CPUAVID4
CPUAVID3
CPUAVID2
CPUAVID1
CPUAVID0
(From CPUA)
R27
R29
R31
R33
R35
R37
1K
1K
1K
1K
1K
1K
VIDA5
VIDA4
VIDA3
VIDA2
VIDA1
VIDA0
CPUBVID5
CPUBVID4
CPUBVID3
CPUBVID2
CPUBVID1
CPUBVID0
R28
R30
R32
R34
R36
R38
1K
1K
1K
1K
1K
1K
VIDB5
VIDB4
VIDB3
VIDB2
VIDB1
VIDB0
(From CPUB)
Title
- 88 -
W83792D H/W Sensing Circuit
Size
Document Number
Date:
Thursday , Nov ember 10, 2005
Rev
0.6
Sheet
2
of
4
W83792AD/AG/D/G
+12V
Q1
PNP
3906
1K
FANOUT1
PWMOUT1
+
R42
510
LM358
R41
470K 2
R43
10K
U2A
Q3 P DGS TO-1
+
10u
1
FANOUT1
C6
Q2
MOSFET N
2N7002
DC FAN OUTPUT
+12V
3
R40
PWM FAN OUTPUT
4.7K
-
R39
DCOUT1
R44
6.49K
+12V
R45
4.7K
R46
1K
Q3
PNP
3906
+12V
PWMOUT2
C7
Q4
MOSFET N
2N7002
510
+
10u
FANOUT2
LM358
3
R47
-
FANOUT2
R48 470K
2
+
Q7 P DGS TO-1
R49
10K
1
U3A
DCOUT2
R50
6.49K
+3.3V
DCOUT1
R51
0
PWMOUT1
R53
0
D1
1N4148
R52
4.7K
JP1
FANIN1
3
2
1
HEADER 3
R63, R66 FOR DC FAN
R65, R68 FOR PWM FAN
+3.3V
DCOUT2
R54
0
PWMOUT2
R56
0
D2
1N4148
R55
4.7K
JP2
FANIN2
3
2
1
HEADER 3
Title
Size
Date:
- 89 -
W83792D FAN OUTPUT CIRCUIT
Document Number
Thursday , Nov ember 10, 2005
Rev
0.6
Sheet
3
of
4
Publication Release Date: April 26, 2006
Revision 0.9
W83792AD/AG/D/G
R57
FANOUT1
VCC12
1
100K
C8
0.1U
Q5
N DGS TO-252
2
3
C9
10n
R58
R59 10K
FANOUT2
DCOUT1
C12
0.1U
0.1U
2
3
C13 0.1U
4
5
6
C15
7
U4
FAN1_IN
FAN1_DRV
FAN2_IN
FAN1_SEN
VCC12
FAN2_DRV
C1
FAN2_SEN
C2
FAN3_DRV
CHRPMP
FAN3_SEN
GND
FAN3_IN
W83391TS
R60
6.49K
VCC12
13
12
C14
10n
10
8
470u
Q6
N DGS TO-252
2
11
9
C10
R61 10K
DCOUT2
R62
6.49K
C16
470u
VCC12
1
0.1U
14
1
C11
1
3
VCC12
100K
R63
Q7
N DGS TO-252
C17
10n
100K
C18
0.1U
3
2
FANOUT3
R64 10K
DCOUT3
R65
6.49K
C19
470u
Title
W83792D with W83391TS FAN OUTPUT CIRCUIT
Size
Document Number
Custom<Doc>
Date:
- 90 -
Thursday , Nov ember 17, 2005
Rev
0.6
Sheet
4
of
4
W83792AD/AG/D/G
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 91 -
Publication Release Date: April 26, 2006
Revision 0.9