WINBOND W39V040AP

W39V040A
512K × 8 CMOS FLASH MEMORY
WITH LPC INTERFACE
1. GENERAL DESCRIPTION
The W39V040A is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For
flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased
in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture
of the W39V040A results in fast program/erase operations with extremely low current consumption. This
device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in
the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs.
But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also
be programmed and erased using standard EPROM programmers.
2. FEATURES
•
Single 3.3-volt Operations:
• Hardware protection:
− 3.3-volt Read
− Optional 16K byte or 64K byte Top Boot Block
with lockout protection
− 3.3-volt Erase
− #TBL & #WP support the whole chip hardware
protection
− 3.3-volt Program
•
Fast Program Operation:
•
Flexible 4K-page size can be used as Parameter
Blocks
Fast Erase Operation:
− Chip erase 100 mS (max.)
− Sector erase 25 mS (max.)
− Page erase 25 mS (max.)
•
Low power consumption
•
Automatic program and erase timing with
internal VPP generation
•
Fast Read access time: Tkq 11 nS
•
End of program or erase detection
•
Endurance: 10K cycles (typ.)
− Toggle bit
•
Twenty-year data retention
− Data polling
•
8 Even sectors with 64K bytes each, which is
composed of 16 flexible pages with 4K bytes
•
Any individual sector or page can be erased
− Byte-by-Byte programming: 35 µS (typ.)
•
− Active current: 12.5 mA (typ. for LPC mode)
•
Latched address and data
•
TTL compatible I/O
•
Available packages: 32L PLCC, 32L STSOP
-1-
Publication Release Date: December 19, 2002
Revision A2
W39V040A
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
#WP
#TBL
CLK
LAD[3:0]
LPC
Interface
#LFRAM
MAIN MEMORY
SECTOR7,
64K BYTES
MODE
A
9
^
G
P
I
3
v
4 3
#
R
E
S
V
E N D
T C D
R
/
#
C
^
C
L
K
v
MAIN MEMORY SECTOR6, 64K BYTES
A
1
0
^
G
P
I
4
v
MAIN MEMORY SECTOR5, 64K BYTES
R/#C
A[10:0]
DQ[7:0]
2 1 32 31 30
A7(GPI1)
5
29
MODE
A6(GPI0)
6
28
Vss
A5(#WP)
7
A4(#TBL)
8
A3(RSV)
9
A2(RSV)
27
MAIN MEMORY SECTOR4, 64K BYTES
Programmer
Interface
NC
VDD
10
24
#OE(#INIT)
A1(RSV)
11
23
#WE(#LFRAM)
A0(RSV)
12
22
NC
DQ0(LAD0)
13
21
DQ7(RSV)
MAIN MEMORY SECTOR3, 64K BYTES
MAIN MEMORY SECTOR2, 64K BYTES
#OE
MAIN MEMORY SECTOR1, 64K BYTES
#WE
MAIN MEMORY SECTOR0, 64K BYTES
NC
26
25
32L PLCC
8K BYTES
7A000
PARAMETER BLOCK2, 79FFF
8K BYTES
MEMORY BLOCK,
32K BYTES
#RESET
A
8
^
G
P
I
2
v
7FFFF
7C000
PARAMETER BLOCK1, 7BFFF
BOOT BLOCK,
16K BYTES
78000
77FFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
5. PIN DESCRIPTION
14 15 16 17 18 19 20
D
Q
1
^
L
A
D
1
v
SYM.
D V D D D D
Q S Q Q Q Q
2 S 3 4 5 6
^
^ ^ ^ ^
L
L R R R
A
A S S S
D
D V V V
2
3 v v v
v
v
INTERFACE
LPC
MODE
*
*
Interface Mode Selection
#RESET
*
*
Reset
*
Initialize
*
Top Boot Block Lock
*
Write Protect
#INIT
#TBL
#WP
NC
32
#OE(#INIT)
NC
1
2
31
#WE(#LFRAM
NC
3
30
VSS
MODE
4
5
29
28
VDD
DQ7(RSV)
DQ6(RSV)
A10(GPI4)
6
27
DQ5(RSV)
R/#C(CLK)
VDD
7
26
25
DQ4(RSV)
NC
#RESET
9
10
24
23
VSS
DQ2(LAD2)
A9(GPI3)
22
DQ1(LAD1)
A8(GPI2)
11
12
21
DQ0(LAD0)
A7(GPI1)
13
20
A0(RSV)
A1(RSV)
A2(RSV)
8
32L STSOP
14
19
A5(#WP)
15
A4(#TBL)
16
18
17
A6(GPI0)
DQ3(LAD3)
A3(RSV)
-2-
PIN NAME
PGM
CLK
*
CLK Input
GPI[4:0]
*
General Purpose Inputs
ID[3:0]
*
Identification Inputs
LAD[3:0]
*
Address/Data Inputs
*
LPC Cycle Initial
#LFRAM
R/#C
*
Row/Column Select
A[10:0]
*
Address Inputs
DQ[7:0]
*
Data Inputs/Outputs
#OE
#WE
*
Output Enable
*
Write Enable
VDD
*
*
Power Supply
VSS
*
*
Ground
RSV
*
*
Reserve Pins
NC
*
*
No Connection
W39V040A
6. FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, and the other is
LPC interface mode. The MODE pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET. When
MODE pin is set to high position, the device is in the Programmer mode; while the MODE pin is set to
low position, it is in the LPC mode. In Programmer mode, this device just behaves like traditional flash
parts with 8 data lines. But the row and column address inputs are multiplexed. The row address is
mapped to the higher internal address A[18:11]. And the column address is mapped to the lower internal
address A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.0. Through
the LAD[3:0] and #LFRAM to communicate with the system chipset .
Read(Write) Mode
In Programmer interface mode, the read(write) operation of the W39V040A is controlled by #OE (#WE).
The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the
output control and is used to gate data from the output pins. The data bus is in high impedance state
when #OE is high. As in the LPC interface the "bit 1 of CYCLE TYPE+DIR" determines mode, the read
or write. Refer to the timing waveforms for further details.
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is
in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be
at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read
or standby mode, it depends on the control signals.
Boot Block Operation and Hardware Protection at Initial - #TBL and #WP
There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this
device can be locked as boot block, which can be used to store boot codes. It is located in the last
16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex).
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not
be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be
programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address 7FFF2(hex). If the DQ0/DQ1 output
data is "1," the 64Kbytes/16Kbytes boot block programming lockout feature will be activated; if the
DQ0/DQ1 output data is "0," the lockout feature will be inactivated and the boot block can be
erased/programmed. But the hardware protection will override the software lock setting, i.e., while the
#TBL pin is trapped at low state, the top boot block cannot be programmed/erased whether the output
data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL will lock the whole 64Kbytes top boot
-3-
Publication Release Date: December 19, 2002
Revision A2
W39V040A
block, it will not partially lock the 16Kbytes boot block. You can check the DQ2/DQ3 at the address
7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is "0", it means the #TBL pin
is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend
on software setting. On the other hand, if the DQ2 is "1", it means the #TBL pin is tied to low state, then
boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP
state. If the DQ3 is "0", it means the #WP pin is in high state, then all the sectors except the boot block
can be programmed/erased. On the other hand, if the DQ3 is "1", then all the sectors except the boot
block are programmed/erased inhibited.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
within fast 100 mS (max). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the other memory sectors
will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state
before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase
operation if the “boot block programming lockout feature” is not activated. The device will automatically
return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be
used to detect end of erase cycle.
Sector/Page Erase Operation
Sector/page erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing
the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase command.
The sector/page address (any address location within the desired sector/page) is latched on the rising
edge of R/C, while the command (30H/50H) is latched on the rising edge of #WE in programmer mode.
Sector/page erase does not require the user to program the device prior to erase. When erasing a
sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is
not required to provide any controls or timings during these operations.
The automatic sector/page erase begins after the erase command is completed, right from the rising
edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data on
DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be
performed at an address within any of the sectors/pages being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
Program Operation
The W39V040A is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot
block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50 µS max. TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be
used to detect end of program cycle.
-4-
W39V040A
Hardware Data Protection
The integrity of the data stored in the W39V040A is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation is inhibited when VDD is less
than 1.5V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the devices will automatically time-out 5
mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W39V040A includes a data polling feature to indicate the end of a program or erase cycle. When
the W39V040A is in the internal program or erase cycle, any attempts to read DQ7 of the last byte
loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7
will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical
"1" or true data when the erase cycle has been completed.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W39V040A provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
Multi-Chip Operation
Multiple devices can be wired on the single LPC bus. There are four ID pins can be used to support up to
16 devices. But in order not to violate the BIOS ROM memory space defined by Intel, Winbond
W39V040A will only used 3 ID pins to allow up to 8 devices, 4Mbytes for BIOS code and 4Mbytes for
registers memory space.
Register
There are two kinds of registers on this device, the General Purpose Input Registers and Product
Identification Registers. Users can access these registers through respective address in the 4Gbytes
memory map. There are detail descriptions in the sections below.
General Purpose Inputs Register
This register reads the states of GPI[4:0] pins on the W39V040A. This is a pass-through register, which
can be read via memory address FFBxE100(hex). The "x" in the addresses represents the ID [3:0] pin
straps. Since it is pass-through register, there is no default value.
-5-
Publication Release Date: December 19, 2002
Revision A2
W39V040A
GPI Register
BIT
FUNCTION
7−5
4
3
2
1
0
Reserved
Read GPI4 pin status
Read GPI3 pin status
Read GPI2 pin status
Read GPI1 pin status
Read GPI0 pin status
Product Identification Registers
There is an alternative software method (six commands bytes) to read out the Product Identification in
both the Programmer interface mode and the LPC interface mode. Thus, the programming equipment
can automatically matches the device with its proper erase and programming algorithms.
In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access
the product ID for programmer interface mode. A read from address 0000(hex) outputs the
manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 3D(hex).” The
product ID operation can be terminated by a three-byte command sequence or an alternate one-byte
command sequence (see Command Definition table for detail).
Identification Input Pins ID[3:0]
These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot
device should be 0000b. And all the subsequent parts should use the up-count strapping. Note that a 1M
byte ROM will occupy two Ids. For example: a 1MByte ROM's ID is 0000b, the next ROM's ID is 0010b.
These pins all are pulled down with internal resistor.
Memory Address Map
There are 8M bytes space reserved for BIOS Addressing. The 8M bytes are mapped into a single 4M
system address by dividing the ROMs into two 4M byte pages. For accessing the 4M byte BIOS storage
space, the ID[2:0] pins are inverted in the ROM and are compared to address lines [21:19]. ID[3] can be
used as like active low chip-select pin.
The 32Mbit address space is as below:
BLOCK
4M Byte BIOS ROM
LOCK
ADDRESS RANGE
None
FFFF, FFFFh: FFC0, 0000h
The ROM responds to 640K (top 512K + bottom 128K) byte pages based on the ID pins strapping
according to the following table:
ID[2:0] PINS
ROM BASED ADDRESS RANGE
000
FFFF, FFFFh: FFF8, 0000h & 000F, FFFFh: 000E, 00000h
001
FFF7, FFFFh: FFF0, 0000h
010
FFEF, FFFFh: FFE8, 0000h
011
FFE7, FFFFh: FFE0, 0000h
-6-
W39V040A
Continued
100
FFDF, FFFFh: FFD8, 0000h
101
FFD7, FFFFh: FFD0, 0000h
110
FFCF, FFFFh: FFC8, 0000h
111
FFC7, FFFFh: FFC0, 0000h
Table of Operating Modes
Operating Mode Selection - Programmer Mode
MODE
Read
Write
Standby
Write Inhibit
Output Disable
PINS
#OE
#WE
#RESET
ADDRESS
DQ.
VIL
VIH
VIH
AIN
Dout
VIH
VIL
VIH
AIN
Din
X
X
VIL
X
High Z
VIL
X
VIH
X
High Z/DOUT
X
VIH
VIH
X
High Z/DOUT
VIH
X
VIH
X
High Z
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is
not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory
Cycle Definition".
Standard LPC Memory Cycle Definition
FIELD
NO. OF
CLOCKS
DESCRIPTION
Start
1
"0000b" appears on LPC bus to indicate the initial
Cycle Type & Dir
1
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
TAR
2
Turned Around Time
Addr.
8
Address Phase for Memory Cycle. LPC supports the 32 bits address protocol.
The addresses transfer most significant nibble first and least significant nibble
last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.)
Sync.
N
Synchronous to add wait state. "0000b" means Ready, "0101b" means Short
Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error,
other values are reserved.
Data
2
Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on
LAD[3:0] last.)
-7-
Publication Release Date: December 19, 2002
Revision A2
W39V040A
Table of Command Definition
COMMAND
NO. OF
1ST CYCLE
2ND CYCLE
3RD CYCLE
4TH CYCLE
5TH CYCLE
6TH CYCLE
DESCRIPTION
Cycles
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Read
1
AIN
Chip Erase
6
5555 AA
DOUT
2AAA 55
5555 80
5555 AA
2AAA 55
5555 10
Sector Erase
6
5555 AA
2AAA 55
5555 80
5555 AA
2AAA 55
SA
(3)
30
Page Erase
6
5555 AA
2AAA 55
5555 80
5555 AA
2AAA 55
PA
(4)
50
Byte Program
4
5555 AA
2AAA 55
5555 A0
AIN
Top Boot Block Lockout
– 64K/16KByte
6
5555 AA
2AAA 55
5555 80
5555 AA
Product ID Entry
3
5555 AA
2AAA 55
5555 90
2AAA 55
5555 F0
Product ID Exit
(1)
3
5555 AA
Product ID Exit
(1)
1
XXXX F0
DIN
2AAA 55
5555 40/70
Notes:
1. The cycle means the write command cycle not the LPC clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]
3. Address Format: A14 − A0 (Hex); Data Format: DQ7 − DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address
SA = 7XXXXh for Unique Sector7 (Boot Sector)
SA = 3XXXXh for Unique Sector3
SA = 6XXXXh for Unique Sector6
SA = 2XXXXh for Unique Sector2
SA = 5XXXXh for Unique Sector5
SA = 1XXXXh for Unique Sector1
SA = 4XXXXh for Unique Sector4
SA = 0XXXXh for Unique Sector0
6. PA: Page Address
PA = 7FXXXh for Page 15 in Sector 7
PA =
PA =
PA =
PA =
PA =
PA =
PA =
PA = 7EXXXh for Page 14 in Sector 7
6FXXXh
5FXXXh
4FXXXh
3FXXXh
2FXXXh
1FXXXh
0FXXXh
PA = 7DXXXh for Page 13 in Sector 7
to
to
to
to
to
to
to
PA = 7CXXXh for Page 12 in Sector 7
60XXXh
50XXXh
40XXXh
30XXXh
20XXXh
10XXXh
00XXXh
PA = 7BXXXh for Page 11 in Sector 7
for
for
for
for
for
for
for
PA = 7AXXXh for Page 10 in Sector 7
Page 15
to
Page 15
to
Page 15
to
Page 15
to
Page 15
to
Page 15
to
Page 15
to
Page 0
PA = 79XXXh for Page 9 in Sector 7
Page 0
Page 0
Page 0
Page 0
Page 0
Page 0
PA = 78XXXh for Page 8 in Sector 7
In
In
In
In
In
In
In
PA = 77XXXh for Page 7 in Sector 7
Sector 6
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Sector 0
PA = 76XXXh for Page 6 in Sector 7
(Reference
to the
first
column)
(Reference
to the
first
column)
(Reference
to the
first
column)
(Reference
to the
first
column)
(Reference
to the
firs
column)
(Reference
to the
first
column)
(Reference
to the
first
column)
PA = 75XXXh for Page 5 in Sector 7
PA = 74XXXh for Page 4 in Sector 7
PA = 73XXXh for Page 3 in Sector 7
PA = 72XXXh for Page 2 in Sector 7
PA = 71XXXh for Page 1 in Sector 7
PA = 70XXXh for Page 0 in Sector 7
-8-
W39V040A
Embedded Programming Algorithm
Start
Write Program Command Sequence
(see below)
#Data Polling/ Toggle bit
Pause T BP
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
-9-
Publication Release Date: December 19, 2002
Revision A2
W39V040A
Embedded Erase Algorithm
Start
Write Erase Command Sequence
(see below)
#Data Polling or Toggle Bit
Successfully Completed
Pause T EC /TSEC/TPEC
Erasure Completed
(Address/Command):
Individual Sector Erase
Command Sequence
(Address/Command):
Individual Page Erase
Command Sequence
(Address/Command):
5555H/AAH
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
2AAAH/55H
Chip Erase Command Sequence
5555H/10H
Sector Address/30H
- 10 -
PageAddress/50H
W39V040A
Embedded #Data Polling Algorithm
Start
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during sector
erase operation
= Any of the page addresses within
the sector being erased during page
erase operation
= Any of the device addresses within
the chip being erased during chip
erase operation
Read Byte
(DQ0 - DQ7)
Address = VA
No
DQ7 = Data
?
Yes
Pass
Embedded Toggle Bit Algorithm
Start
Read Byte
(DQ0 - DQ7)
Address = Don't Care
No
DQ6 = Toggle
?
Yes
Fail
- 11 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product
Identification
Entry (1)
Load data AA
to
address 5555
Product
Product
Identification Exit (6)
Identification
and Boot Block
Lockout Detection
Mode (3)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Read address = 00000
data = DA
Load data 90
to
address 5555
Read address = 00001
data = 3D
Pause 10 µS
Read address = 00002
DQ0/DQ1 of data outputs
= 1/0
(2)
(2)
(4)
Load data 55
to
address 2AAA
Load data F0
to
address 5555
Pause 10 µS
(5)
Normal Mode
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7 − DQ0 (Hex); Address Format: A14 − A0 (Hex)
(2) A1 − A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in “identification and boot block lockout detection” mode if power down.
(4) The DQ[3:0] to indicate the sectors protect status as below:
DQ0
DQ1
DQ2
DQ3
0
64Kbytes Boot Block
Unlocked by Software
16Kbytes Boot Block
Unlocked by Software
64Kbytes Boot Block Unlocked
by #TBL hardware trapping
Whole Chip Unlocked by #WP hardware
trapping Except Boot Block
1
64Kbytes Boot Block
Locked by Software
16Kbytes Boot Block
Locked by Software
64Kbytes Boot Block Locked by
#TBL hardware trapping
Whole Chip Locked by #WP hardware
trapping Except Boot Block
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the “product identification/boot block lockout
detection.”
- 12 -
W39V040A
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Pause T BP
Load data 80
to
address 5555
Exit
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40/70
to
address 5555
40 to lock 64K Boot Block
70 to lcok 16K Boot Block
- 13 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
7. DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
-0.5 to +4.6
V
0 to +70
°C
-65 to +150
°C
D.C. Voltage on Any Pin to Ground Potential
-0.5 to VDD +0.5
V
Transient Voltage (<20 nS) on Any Pin to Ground Potential
-1.0 to VDD +0.5
V
Power Supply Voltage to VSS Potential
Operating Temperature
Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Programmer Interface Mode DC Operating Characteristics
(VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C)
PARAMETER
SYM.
Power Supply
Current
ICC
Input Leakage
Current
ILI
Output Leakage
Current
ILO
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
TEST CONDITIONS
In Read or Write mode, all DQs open
LIMITS
MIN. TYP.
MAX.
UNIT
mA
-
10
20
VIN = VSS to VDD
-
-
90
µA
VOUT = VSS to VDD
-
-
90
µA
-
-0.3
-
0.8
V
-
2.0
-
VDD +0.5
V
IOL = 2.1 mA
-
-
0.45
V
IOH = -0.1mA
2.4
-
-
V
Address inputs = 3.0V/0V, at f = 3 MHz
- 14 -
W39V040A
LPC Interface Mode DC Operating Characteristics
(VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C)
PARAMETER
SYM.
Power Supply Current
ICC
CMOS Standby
Current
Isb1
TTL Standby Current
Isb2
Input Low Voltage
VIL
Input Low Voltage of
#INIT Pin
TEST CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
-
12.5
20
-
5
25
-
3
10
-
-0.5
-
0.3 VDD
V
VILI
-
-0.5
-
0.2 VDD
V
Input High Voltage
VIH
-
0.5
VDD
-
VDD
+0.5
V
Input High Voltage of
#INIT Pin
VIHI
-
1.35V
-
VDD
+0.5
V
Output Low Voltage
VOL1 IOL = 1.5 mA
-
-
0.1
VDD
V
Output High Voltage
VOH1 IOH = -0.5 mA
0.9
VDD
-
VDD
V
All Iout = 0A, CLK = 33 MHz,
in LPC mode operation.
#LFRAM = 0.9 VDD, CLK = 33 MHz,
all inputs = 0.9 VDD / 0.1 VDD
#LFRAM = 0.1 VDD, CLK = 33 MHz,
all inputs = 0.9 VDD / 0.1 VDD
mA
µA
mA
Power-up Timing
PARAMETER
SYMBOL
TYPICAL
UNIT
Power-up to Read Operation
TPU. READ
100
µS
Power-up to Write Operation
TPU. WRITE
5
mS
Capacitance
(VDD = 3.3V, TA = 25° C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
I/O Pin Capacitance
CI/O
VI/O = 0V
12
pF
Input Capacitance
CIN
VIN = 0V
6
pF
- 15 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
8. PROGRAMMER INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 0.9 VDD
Input Rise/Fall Time
< 5 nS
Input/Output Timing Level
1.5V/1.5V
Output Load
1 TTL Gate and CL = 30 pF
AC Test Load and Waveform
+3.3V
1.8KΩ
DOUT
Input
30 pF
(Including Jig and
Scope)
Output
0.9VDD
1.3K Ω
1.5V
1.5V
0V
Test Point
- 16 -
Test Point
W39V040A
AC Characteristics
Read Cycle Timing Parameters
(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
W39V040A
MIN.
UNIT
MAX.
Read Cycle Time
TRC
300
-
nS
Row/Column Address Set Up Time
TAS
50
-
nS
Row/Column Address Hold Time
TAH
50
-
nS
Address Access Time
TAA
-
175
nS
Output Enable Access Time
TOE
-
75
nS
#OE Low to Act Output
TOLZ
0
-
nS
#OE High to High-Z Output
TOHZ
-
35
nS
TOH
0
-
nS
Output Hold from Address Change
Write Cycle Timing Parameters
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Reset Time
TRST
1
-
-
µS
Address Setup Time
TAS
50
-
-
nS
Address Hold Time
TAH
50
-
-
nS
R/#C to Write Enable High Time
TCWH
50
-
-
nS
#WE Pulse Width
TWP
100
-
-
nS
#WE High Width
TWPH
100
-
-
nS
Data Setup Time
TDS
50
-
-
nS
Data Hold Time
TDH
50
-
-
nS
#OE Hold Time
TOEH
0
-
-
nS
Byte Programming Time
TBP
-
35
50
µS
Sector/Page Erase Cycle Time
TPEC
-
20
25
mS
Chip Erase Cycle Time
TEC
-
75
100
mS
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
Data Polling and Toggle Bit Timing Parameters
PARAMETER
SYMBOL
W39V040A
MIN.
MAX.
UNIT
#OE to Data Polling Output Delay
TOEP
-
40
nS
#OE to Toggle Bit Output Delay
TOET
-
40
nS
- 17 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
9. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
Read Cycle Timing Diagram
#RESET
TRST
TRC
TAH
TAS
Column Address
Row Address
Column Address
A[10:0]
Row Address
TAH
TAS
R/#C
VIH
#WE
TAA
#OE
TOH
TOE
T OHZ
TOLZ
High-Z
DQ[7:0]
Data Valid
Write Cycle Timing Diagram
TRST
#RESET
A[10:0]
Column Address
TAS
TAH
Row Address
TAS
TAH
R/#C
TCWH
TOEH
#OE
TWP
TWPH
#WE
TDS
DQ[7:0]
Data Valid
- 18 -
TDH
High-Z
W39V040A
Timing Waveforms for Programmer Interface Mode, continued
Program Cycle Timing Diagram
Byte Program Cycle
A[10:0]
2AAA
5555
(Internal A[18:0])
DQ[7:0]
5555
55
AA
Programmed Address
A0
Data-In
R/#C
#OE
TWP
T WPH
TBP
#WE
Byte 1
Byte 0
Byte 2
Byte 3
Internal Write Start
Note: The internal address A[18:0] are converted from external Column/Row address
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
#DATA Polling Timing Diagram
A[10:0]
(Internal A[18:0])
An
An
An
An
R/#C
#WE
#OE
TOEP
DQ7
X
X
X
X
TBP or TEC
- 19 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
Timing Waveforms for Programmer Interface Mode, continued
Toggle Bit Timing Diagram
A[10:0]
R/#C
#WE
#OE
TOET
DQ6
T BP or T EC
Boot Block Lockout Enable Timing Diagram
SIX-byte code for Boot Block Lockout command
A[10:0]
(Internal A[18:0])
DQ[7:0]
5555
AA
2AAA
55
5555
5555
2AAA
5555
80
AA
55
40/70
R/#C
#OE
TWP
#WE
T WC
T WPH
SB0
SB1
SB2
SB3
SB4
SB5
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
When 40(hex) is loaded, the 64KByte are locked; while 70(hex) is loaded, the 16KByte is locked.
- 20 -
W39V040A
Timing Waveforms for Programmer Interface Mode, continued
Chip Erase Diagram
Six-byte code for 3.3V-only software chip erase
A[10:0]
(Internal A[18:0])
DQ[7:0]
2AAA
5555
AA
5555
5555
80
55
2AAA
AA
5555
55
10
R/#C
#OE
TWP
#WE
T EC
T WPH
SB0
SB2
SB1
SB3
SB4
SB5
Internal Erasure Starts
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
Sector/Page Erase Timing Diagram
Six-byte code for 3.3V-only
Sector/Page Erase
A[10:0]
(Internal A[18:0])
DQ[7:0]
5555
2AAA
5555
AA
55
80
5555
AA
2AAA
55
SA/PA
30/50
R/#C
#OE
TWP
#WE
TEC
TWPH
SB0
SB1
SB2
SB3
SB4
SB5
Internal Erase starts
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
SA = Sector Address and PA = Page Address, Please ref. to the "Table of Command Definition"
- 21 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
10. LPC INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0.6 VDD to 0.2 VDD
Input Rise/Fall Slew Rate
1 V/nS
Input/Output Timing Level
0.4 VDD / 0.4 VDD
Output Load
1 TTL Gate and CL = 10 pF
Read/Write Cycle Timing Parameters
(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
W39V040A
MIN.
MAX.
UNIT
Clock Cycle Time
TCYC
30
-
nS
Input Set Up Time
TSU
7
-
nS
Input Hold Time
THD
0
-
nS
Clock to Data Valid
TKQ
2
11
nS
Note: Minimum and Maximum time has different loads. Please refer to PCI specification.
Reset Timing Parameters
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
VDD Stable to Reset Active
TPRST
1
-
-
mS
Clock Stable to Reset Active
TKRST
100
-
-
µS
Reset Pulse Width
TRSTP
100
-
-
nS
Reset Active to Output Float
TRSTF
-
-
50
nS
Reset Inactive to Input Active
TRST
1
-
-
µS
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
- 22 -
W39V040A
11. TIMING WAVEFORMS FOR LPC INTERFACE MODE
Read Cycle Timing Diagram
TCYC
CLK
#RESET
#LFRAM
Start
LAD[3:0]
TSU THD
TKQ
Memory
Read
Cycle
0000b 010Xb
TAR
Address
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
A[7:4]
A[3:0]
2 Clocks
Load Address in 8 Clocks
1 Clock 1 Clock
Next Start
Data
Sync
D[3:0]
Tri-State 0000b
1111b
1 Clock
D[7:4]
TAR
Data out 2 Clocks
0000b
1 Clock
Write Cycle Timing Diagram
TCYC
CLK
#RESET
TSU THD
#LFRAM
Start
LAD[3:0]
Memory
Write
Cycle
0000b 011Xb
1 Clock 1 Clock
Address
A[31:28] A[27:24] A[23:20] A[19:16]
A[15:12]
Data
A[11:8]
Load Address in 8 Clocks
A[7:4]
A[3:0]
D[3:0]
D[7:4]
Load Data in 2 Clocks
- 23 -
TAR
1111b
Tri-State
2 Clocks
Sync
0000b
1 Clock
Next Start
TAR
0000b
1 Clock
Publication Release Date: December 19, 2002
Revision A2
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Program Cycle Timing Diagram
CLK
#RESET
#LFRAM
1st Start
LAD[3:0]
0000b
1 Clock
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1010b
1111b
Load Data "AA" in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock
1010b
2 Clocks
Start next
command
Sync
Tri-State
0000b
TAR
1 Clock
1 Clock
Sync
Start next
command
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
LAD[3:0]
0000b
1 Clock
011Xb
Data
Address
2nd Start Cycle
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
0101b
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1 Clock
TAR
1111b
Tri-State
2 Clocks
0000b
TAR
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
LAD[3:0]
0000b
1 Clock
011Xb
Data
Address
3rd Start Cycle
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1010b
Load Data "A0"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock
0000b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
Internal
program start
4th Start
LAD[3:0]
0000b
1 Clock
Memory
Write
Cycle
011Xb
1 Clock
Address
A[31:28]
A[27:24]
A[23:20]
A[19:16]
Data
A[15:12]
A[11:8]
A[7:4]
A[3:0]
D[3:0]
TAR
D[7:4]
Load Din in 2 Clocks
Load Ain in 8 Clocks
1111b
Tri-State
2 Clocks
Sync
0000b
1 Clock
Write the 4th command(target location to be programmed) to the device in LPC mode.
- 24 -
TAR
Internal
program start
W39V040A
Timing Waveforms for LPC Interface Mode, continued
#DATA Polling Timing Diagram
CLK
#RESET
#LFRAM
1st Start
LAD[3:0]
Memory
Write
Cycle
0000b 011Xb
Data
Address
A[31:28]
A[27:24]
A[23:20]
A[19:16]
An[15:12]
An[11:8]
An[7:4]
An[3:0]
Load Address "An" in 8 Clocks
1 Clock 1 Clock
Dn[3:0]
Dn[7:4]
Load Data "Dn"
in 2 Clocks
TAR
1111b
Start next
command
Sync
0000b
Tri-State
2 Clocks
TAR
1 Clock
0000b
1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Start
Memory
Read
Cycle
0000b
010Xb
TAR
Address
XXXXb
XXXXb
XXXXb
XXAn[17:16]
An[15:12]
An[11:8]
An[7:4]
An[3:0]
Tri-State
2 Clocks
Load Address in 8 Clocks
1 Clock 1 Clock
1111b
Sync
0000b
Next Start
Data
XXXXb
Dn7,xxx
TAR
1 Clock Data out 2 Clocks
0000b
1 Clock
Read the DQ7 to see if the internal write complete or not.
CLK
#RESET
#LFRAM
LAD[3:0]
Start
Memory
Read
Cycle
0000b
010Xb
1 Clock 1 Clock
TAR
Address
An[31:28]
An[27:24]
An[23:20]
An[19:16]
An[15:12]
An[11:8]
An[7:4]
Load Address in 8 Clocks
An[3:0]
1111b
Tri-State
2 Clocks
Sync
0000b
Next Start
Data
XXXXb
Dn7,xxx
1 Clock Data out 2 Clocks
TAR
0000b
1 Clock
When internal write complete, the DQ7 will equal to Dn7.
- 25 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Toggle Bit Timing Diagram
CLK
#RESET
#LFRAM
1st Start
LAD[3:0]
Memory
Write
Cycle
0000b 011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXAn[17:16]
An[15:12]
An[11:8]
An[7:4]
An[3:0]
Dn[7:4]
Load Data "Dn"
in 2 Clocks
Load Address "An" in 8 Clocks
1 Clock 1 Clock
Dn[3:0]
TAR
1111b
Start next
command
Sync
0000b
Tri-State
2 Clocks
TAR
1 Clock
1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Start
Memory
Read
Cycle
0000b
010Xb
TAR
Address
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
Tri-State
2 Clocks
Load Address in 8 Clocks
1 Clock 1 Clock
1111b
Sync
0000b
Next Start
Data
XXXXb
X,D6,XXb
TAR
1 Clock Data out 2 Clocks
0000b
1 Clock
Read the DQ6 to see if the internal write complete or not.
CLK
#RESET
#LFRAM
LAD[3:0]
Start
Memory
Read
Cycle
0000b
010Xb
1 Clock 1 Clock
TAR
Address
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
Load Address in 8 Clocks
XXXXb
XXXXb
1111b
Tri-State
2 Clocks
When internal write complete, the DQ6 will stop toggle.
- 26 -
Sync
0000b
1 Clock
Next Start
Data
XXXXb
X,D6,XXb
Data out 2 Clocks
TAR
0000b
1 Clock
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Boot Block Lockout Enable Timing Diagram
CLK
#RESET
#LFRAM
1st Start
0000b
LAD[3:0
]
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1010b
Load Data "AA"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock 1 Clock
1010b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
2nd Start Cycle
LAD[3:0
]
0000b
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
TAR
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1 Clock 1 Clock
0101b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clocks
1 Clock
Sync
Start next
command
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0
]
Memory
Write
3rd Start Cycle
0000b
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
0000b
1000b
Load Data "80"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock 1 Clock
TAR
1111b
Tri-State
2 Clocks
0000b
TAR
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
4th Start
LAD[3:0
]
0000b
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1010b
Load Data "AA"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock 1 Clock
1010b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0
]
Memory
Write
5th Start Cycle
0000b
011Xb
Data
Address
XXXXb
XXXX
XXXXb
XXXXb
X010b
1010b
1010b
1010b
0101b
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1 Clock 1 Clock
TAR
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
6th Start Cycle
LAD[3:0
]
0000b
011Xb
1 Clock 1 Clock
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
Load Address "5555" 8 Clocks
0101b
0000b
TAR
0100b
0111b
Load Data "40"
or "70" in 2 Clocks
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
1 Clock
TAR
1 Clock
Write the 6th command to the device in LPC mode.
- 27 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Chip Erase Timing Diagram
CLK
#RESET
#LFRAM
1st Start
0000b
LAD[3:0]
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1010b
Load Data "AA"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock 1 Clock
1010b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
2nd Start Cycle
LAD[3:0]
0000b
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
TAR
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1 Clock 1 Clock
0101b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
3rd Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
Load Data "80"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock 1 Clock
TAR
1000b
0000b
1111b
Start next
command
Sync
Tri-State
2 Clocks
0000b
TAR
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
4th Start
0000b
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1010b
Load Data "AA"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock 1 Clock
1010b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
5th Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
1 Clock 1 Clock
XXXXb
XXXXb
X010b
1010b
1010b
1010b
0101b
TAR
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1111b
Start next
command
Sync
Tri-State
2 Clocks
0000b
TAR
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
6th Start
LAD[3:0]
0000b
Internal
erase start
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address
XXXXb
XXXXb
XXXXb
XXXXb
Data
X101b
0101b
Load Address "5555" in 8 Clocks
0101b
0101b
0000b
0001b
Load Data "10"
in 2 Clocks
Write the 6th command to the device in LPC mode.
- 28 -
TAR
1111b
Tri-State
2 Clocks
Sync
0000b
1 Clock
TAR
Internal
erase start
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Sector Erase Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
1st Start Cycle
0000b
LAD[3:0]
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1010b
Load Data "AA"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock 1 Clock
1010b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
2nd Start Cycle
0000b
LAD[3:0]
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
TAR
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1 Clock 1 Clock
0101b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
3rd Start Cycle
LAD[3:0]
0000b
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1000b
Load Data "80"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clocks1 Clocks
0000b
1111b
Start next
command
Sync
Tri-State
2 Clocks
0000b
TAR
1 Clocks
1 Clocks
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
4th Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
1 Clock 1 Clock
XXXXb
XXXXb
X101b
0101b
0101b
0101b
1010b
TAR
1010b
Load Data "AA"
in 2 Clocks
Load Address "5555" in 8 Clocks
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
5th Start Cycle
LAD[3:0]
0000b
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1 Clock 1 Clock
TAR
0101b
1111b
Start next
command
Sync
Tri-State
2 Clocks
0000b
TAR
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
Internal
erase start
#LFRAM
6th Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address
XXXXb
XXXXb
XXXXb
SA[18:16]
Data
XXXXb
XXXXb
XXXXb
Load Sector Address in 8 Clocks
XXXXb
0000b
0011b
Load Data "30"
in 2 Clocks
TAR
1111b
Tri-State
2 Clocks
Sync
0000b
TAR
Internal
erase start
1 Clock
Write the 6th command(target sector to be erased) to the device in LPC mode.
- 29 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Page Erase Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
1st Start Cycle
0000b
LAD[3:0]
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1010b
Load Data "AA"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clock 1 Clock
1010b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
2nd Start Cycle
LAD[3:0]
0000b
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
TAR
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1 Clock 1 Clock
0101b
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
3rd Start Cycle
LAD[3:0]
0000b
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
TAR
1000b
Load Data "80"
in 2 Clocks
Load Address "5555" in 8 Clocks
1 Clocks1 Clocks
0000b
1111b
Start next
command
Sync
Tri-State
2 Clocks
0000b
TAR
1 Clocks
1 Clocks
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
4th Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
Data
Address
XXXXb
XXXXb
1 Clock 1 Clock
XXXXb
XXXXb
X101b
0101b
0101b
0101b
1010b
TAR
1010b
Load Data "AA"
in 2 Clocks
Load Address "5555" in 8 Clocks
1111b
Tri-State
2 Clocks
Start next
command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
5th Start Cycle
LAD[3:0]
0000b
011Xb
Data
Address
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
TAR
0101b
Load Data "55"
in 2 Clocks
Load Address "2AAA" in 8 Clocks
1 Clock 1 Clock
0101b
1111b
Start next
command
Sync
Tri-State
2 Clocks
0000b
TAR
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
6th Start
LAD[3:0]
0000b
Internal
erase start
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address
XXXXb
XXXXb
XXXXb
PA[18:16]
Data
PA[15:12]
XXXXb
XXXXb
Load Page Address in 8 Clocks
XXXXb
0000b
TAR
0101b
Load Data "50"
in 2 Clocks
1111b
Tri-State
2 Clocks
Write the 6th command(target page to be erased) to the device in LPC mode.
- 30 -
Sync
0000b
1 Clock
TAR
Internal
erase start
W39V040A
Timing Waveforms for LPC Interface Mode, continued
GPI Register Readout Timing Diagram
CLK
#RESET
#LFRAM
LAD[3:0]
Start
Memory
Read
Cycle
0000b
010Xb
TAR
Address
1111b
1 Clock 1 Clock
1111b
1011b
XXXXb
1110b
0001b
0000b
Load Address "FFBXE100(hex)" in 8 Clocks
0000b
1111b
Tri-State
2 Clocks
Next Start
Data
Sync
0000b
D[3:0]
D[7:4]
1 Clock Data out 2 Clocks
TAR
0000b
1 Clock
Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved bits.
Reset Timing Diagram
VDD
TPRST
CLK
TKRST
TRSTP
#RESET
TRST
TRST
F
LAD[3:0]
#LFRAM
- 31 -
Publication Release Date: December 19, 2002
Revision A2
W39V040A
12. ORDERING INFORMATION
PART NO.
ACCESS
TIME
POWER SUPPLY
CURRENT MAX.
STANDBY VDD
CURRENT MAX.
PACKAGE
(nS)
(mA)
(mA)
W39V040AP
11
20
10
32L PLCC
W39V040AQ
11
20
10
32L STSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
13. HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin STSOP W39V040AQ
W39V040AQ
2138977A-A12
149OBSA
1st line: Winbond logo
2nd line: the part number: W39V040AQ
3rd line: the lot number
4th line: the tracking code: 149 O B SA
149: Packages made in '01, week 49
O: Assembly house ID: A means ASE, O means OSE, ... etc.
B: IC revision; A means version A, B means version B, ... etc.
SA: Process code
- 32 -
W39V040A
14. PACKAGE DIMENSIONS
32L PLCC
Symbol
HE
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
θ
E
4
1
32
30
5
29
GD
D HD
Dimension in Inches
Dimension in mm
Min. Nom. Max.
Min. Nom. Max.
0.140
0.020
3.56
0.50
0.105
0.110
0.115
2.67
2.80
2.93
0.026
0.028
0.032
0.66
0.71
0.81
0.016
0.018
0.022
0.41
0.46
0.56
0.008
0.010
0.014
0.20
0.25
0.35
0.547
0.550
0.553
13.89
13.97
14.05
0.447
0.450
0.453
11.35
11.43
11.51
0.044
0.050
0.056
1.12
1.27
1.42
0.490
0.510
0.530
12.45
12.95
13.46
0.390
0.410
0.430
9.91
10.41
10.92
0.585
0.590
0.595
14.86
14.99
15.11
0.485
0.490
0.495
12.32
12.45
12.57
0.075
0.090
0.095
1.91
2.29
2.41
0.10
0.004
0
0
10
10
21
13
Notes:
14
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusio
3. Controlling dimension: Inches
4. General appearance spec. should be based on final
visual inspection sepc.
c
20
L
A2
θ
e
A1
b
b1
Seating Plane
A
y
GE
32L STSOP
HD
D
c
Dimension in Inches Dimension in mm
Symbol
Min. Nom. Max.
e
E
b
θ
L
L1
A1
A2
A
- 33 -
Y
A
A1
A2
b
c
D
E
HD
e
L
L1
Y
θ
Min. Nom. Max.
0.047
0.002
1.20
0.006
0.05
0.15
0.035
0.040
0.041
0.95
1.00
1.05
0.007
0.009
0.010
0.17
0.22
0.27
0.004
-----
0.008
0.10
-----
0.21
0.488
12.40
0.315
8.00
0.551
14.00
0.020
0.020
0.024
0.50
0.028
0.50
0.031
0.000
0
3
0.60
0.70
0.80
0.004
0.00
5
0
0.10
3
5
Publication Release Date: December 19, 2002
Revision A2
W39V040A
15. VERSION HISTORY
VERSION
DATE
PAGE
A1
October 8, 2002
-
A2
Dec. 19, 2002
14
Modify PGM mode power supply current (Icc)
parameter from 20 mA (typ.) to 10 mA (typ.)
and 30 mA (max.) to 20 mA (max.)
1, 15, 32
Modify LPC mode power supply current (Icc)
parameter from 40 mA (typ.) to 12.5 mA (typ.)
and 60 mA (max.) to 20 mA (max.)
15
DESCRIPTION
Initial Issued
Modify CMOS standby current (Isb1) parameter
from 20 µA (typ.) to 5 µA (typ.) and 100 µA (max.)
to 25 µA (max.)
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 34 -