1 MHz - 3 GHz VGA with 60dB Gain Control Range a Preliminary Technical Data ADL5330 FEATURES Voltage-Controlled Amplifier/Attenuator Operating Frequency 1 MHz to 3 GHz Optimized for Controlling Output Power High Linearity: OIP3 31 dBm @ 900 MHz Output Noise Floor -150 dBm/Hz @ 900 MHz Fully-Balanced Differential Signal Path Differential Input at 50 Ω Wide Gain-Control Range: -34 dB to +22 dB @ 900 MHz Linear-in-dB Gain Control Function, 20 mV/dB Single Supply 4.75 – 6 V GAIN ENBL Output Power Control for Wireless Infrastructure VPS2 VPS2 COM1 VPS2 VPS2 GAIN CONTROL INHI RF I/P RF input, 50Ω INLO Input gm Stage COM2 Continuously Variable Attenuator O/P OPHI (TZ) Stage OPLO RF to PA BALUN COM1 APPLICATIONS VPS2 VPS1 COM2 BIAS & VREF VPS2 VPS1 VREF IPBS OPBS COM2 COM2 COM2 Figure 1. Functional Block Diagram PRODUCT DESCRIPTION The ADL5330 is a high-performance voltage-controlled variablegain amplifier/attenuator, for use up to 3 GHz. The signal path is fully differential; the balanced structure minimizes distortion, and reduces the risk of spurious feed-forward at low gains and high frequencies due to substrate coupling. While operation between a balanced source and load is recommended, a single-sided input is internally converted to differential from. The input impedance is 50-Ω from INHI to INLO. The outputs will usually be coupled into a 50-Ω grounded load via a 1:1 balun. However, the output pins, OPHI and OPLO, may also be used separately, with some noise degradation. A single supply of 4.75 to 6 V is required. With a 2140 MHz W-CDMA 3GPP forward path signal, the ADL5330 is capable of producing greater than –3 dBm output power while maintaining ACPR greater than 55 dB, and an output noise floor less than -144 dBm/Hz. Three cascaded sections are used. The 50-Ω input system converts the applied voltage to a pair of differential currents with high linearity and good common rejection if driven by a single-sided source. The signal currents are then applied to a proprietary voltage-controlled attenuator, which provides precise definition of the overall gain, under the control of the Linear-in-dB interface. Pin GAIN accepts a voltage from 0 V at minimum gain to 1.4 V at full gain. The scaling factor is 20 mV/dB. Optional external control of the input-stage and/or output-stage biasing is provided using pins IPBS and OPBS respectively. The output of the high-accuracy wideband attenuator is applied to a differential trans-impedance output stage. Higher output power is attainable at the lower operating frequencies by raising the supply voltage to 6 V. When powered-down by a logic LO input on the ENBL pin, the current consumption is < TBD µA. The ADL5330 is available in a 24-lead (4 x 4mm) CSP package and is specified for operation from ambient temperatures of −40°C to +85°C. Multiple Patents Pending Rev. PrK Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 World Wide Web Site: http://www.analog.com ©2004 Analog Devices, Inc. All Rights Reserved Preliminary Technical Data ADL5330 ADL5330 SPECIFICATIONS Table 1. VS = 5 V; TA = 25°C; 800 MHz < f < 2.2GHz.1:1 balun at input and output for single-ended 50 Ω match Parameter General Usable Frequency Range Nominal Input Impedance Nominal Output Impedance 100 MHz Gain Control Span Max Gain Min Gain Gain Control Slope Input Compression Point Output Compression Point - P1dB Third-Order Intercept - OIP3 900 MHz Gain Control Span Max Gain Min Gain Gain Control Slope Input Compression Point Output Compression Point - P1dB Third-Order Intercept - OIP3 Output Noise Floor 1900 MHz Gain Control Span Max Gain Min Gain Gain Control Slope Input Compression Point Output Compression Point - P1dB Third-Order Intercept - OIP3 Output Noise Floor 2200 MHz Gain Control Span Max Gain Min Gain Gain Control Slope Input Compression Point Output Compression Point - P1dB Third-Order Intercept - OIP3 GAIN CONTROL INPUT Gain Control Voltage Range Incremental Input Resistance Full-Scale Response Time POWER SUPPLIES Voltage Current, Nominal Active Current, Disabled Conditions Min Typ 0.001 via 1:1 Single-Sided to Differential Balun via 1:1 Differential to Single-Sided Balun GHz Ω Ω dB dB dB mV/dB dBm dBm dBm 52 22 -34 20 +3 +22 +31 -144 +/-3 dB Gain Law Conformance VGAIN = 1.4 V VGAIN = 0.1 V VGAIN = 1.3 V VGAIN = 1.3 V VGAIN = 1.3 V 20 MHz Carrier Offset, VGAIN = 1.3 V, Pout = -2 dBm dB dB dB mV/dB dBm dBm dBm dBm/Hz 47 19 -27 18 +1 +17 +24 -148 +/-3 dB Gain Law Conformance VGAIN = 1.4 V VGAIN = 0.5 V VGAIN = 1.3 V VGAIN = 1.3 V VGAIN = 1.3 V 20 MHz Carrier Offset, VGAIN = 1.3 V, Pout = -7 dBm dB dB dB mV/dB dBm dBm dBm dBm/Hz 48 17 -31 17 +1 +14 +20 +/-3 dB Gain Law Conformance VGAIN = 1.4 V VGAIN = 0.5 V VGAIN = 1.3 V VGAIN = 1.3 V VGAIN = 1.3 V Pin GAIN 0 TBD dB dB dB mV/dB dBm dBm dBm 1.4 V MΩ ns 6 V TBD mA mA µA 500 4.75 5 TBD 240 TBD REV. PrK | Page 2 of 5 3 58 +23 -35 21 +2 +22 +36 VGAIN = 1.3 V VGAIN = 1.3 V VGAIN = 1.3 V VGN = 0 V VGN = 1.4 V ENBL = LO Unit 50 50 +/-3 dB Gain Law Conformance VGAIN = 1.4 V VGAIN = 0.1 V Pin GAIN to COM1 VGN 0 - 1.6V, to within 0.25 dB of final gain Pins VPS1, VPS2, COM1, COM2, ENBL Max Preliminary Technical Data ADL5330 Table 2. Pin Function Description Pin 1,6 2,5 3, 4 7 8 Name VPS1 COM1 INHI,INLO VREF IPBS 9 OPBS 10,11,12,14, 17 13,18,19,20, 21,22 15 16 23 24 COM2 Description Positive Supply for input stage. Nominally equal to 5 V Common for input stage Differential inputs Voltage reference output of 1.5 volts Input bias, normally no connection. This function is subject to change. PCB designs should include the possibility to connect a capacitor between Pin 8 and Pin 9. Output bias, normally no connection. This function is subject to change. PCB designs should include the possibility to connect a capacitor between Pin 8 and Pin 9. Common for output stage VPS2 Positive Supply for output stage. Nominally equal to 5 V OPLO OPHI ENBL GAIN Low side of differential output, bias to VP with RF chokes High side of differential output, bias to VP with RF chokes Device enable, apply logic high for normal operation. Enable Threshold = 1.6 V Gain-control voltage input. Nominal Range 0 to 1.4 V. VPOS GND VPOS J1 Enable SW1 R3 0 25 ohm microstrip (both sides of caps) VPOS C3 0.1 uF J4 VREF J5 IPBS J6 OPBS R12 0 C1 100 pF C13 100 pF VPS2 VPS2 VPS2 VPS2 INHI 50 ohm microstrip L2 120 nH VPS2 C11 100 pF T2 COM2 COM1 C5 100 pF J7 Output OPHI ADL5330 C6 100 pF INLO OPLO COM1 COM2 VPS1 R4 0 C4 100 pF VREF COM2 T1 VPS1 COM2 J3 Input R2 0 L1 120 nH GAIN OPBS 50 ohm microstrip C7 100 pF IPBS VPOS R5 0 R13 10k ENBL J2 Gain C14 0.1 uF C2 0.1 uF R1 0 C8 0.1 uF VPOS VP C12 100 pF 25 ohm microstrip VPOS VPS2 COM2 C10 100 pF R6 0 R15 R8 R14 open open 0 R7 0 R9 0 R10 1nF R11 1nF Figure 2. ADL5330 Evaluation Board Schematic REV. PrK | Page 3 of 5 C9 0.1 uF Preliminary Technical Data ADL5330 Typical Performance Characteristics . 20.00 50 30 15.00 40 20 10.00 30 10 5.00 20 0 0.00 Gain 100 MHz -10 -5.00 Gain 900 MHz OIP3 40 Error - dB Gain - dB . 100 MHz 900 MHz 1900 MHz 2200 MHz 10 0 Gain 1900 MHz 2200 MHz -20 Error 100 MHz Gain Error 900 MHz -30 Error 1900 -10.00 -10 -15.00 -20 -20.00 -30 Error 2200 MHz -40 0 0.2 0.4 0.6 0.8 1 Vgain - Volts 1.2 1.4 0 1.6 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Vgain - V Figure 3. Gain and Gain Law Conformance vs. Vgain Figure 5. OIP3 vs. Gain 30 5 4 20 3 10 1 Output P1dB - dBm Input Referred P1dB - dB 2 100 MHz 900 MHz 1900 MHz 2200 MHz 0 -1 0 100Mhz 900Mhz 1900Mhz 2200Mhz -10 -2 -20 -3 -4 -30 -5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -40 Vgain - V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Vgain - V Figure 4. Input Referred Compression Point vs. Gain -90.00 Pout vs. Vin 0.00 0.00 Pout vs. Vin -100.00 -10.00 -110.00 -20.00 -120.00 -30.00 -130.00 -40.00 -140.00 -50.00 -150.00 0.20 0.40 0.60 0.80 VGAIN 1.00 1.20 1.40 -110.00 Noise - 20 MHz offset O u tp u t P o w e r - d B m -10.00 . N o is e - 2 0 M H z C a rrie r O ffs e t - d B m /H z O u tp u t P o w e r - d B m Noise - 20 MHz offset -60.00 0.00 -100.00 -20.00 -120.00 -30.00 -130.00 -40.00 -140.00 -50.00 -150.00 . N o is e - 2 0 M H z C a r r ie r O ffs e t - d B m /H z 10.00 Figure 7. Output Referred Compression Point vs. Gain -160.00 1.60 -60.00 0.00 Figure 8. Pout and Noise Floor vs. Gain, 900 MHz. Pin = 21 dBm 0.20 0.40 0.60 0.80 VGAIN 1.00 1.20 1.40 -160.00 1.60 Figure 8. Pout and Noise Floor vs. Gain 1.9 GHz. Pin = -22 dBm REV. PrK | Page 4 of 5 Preliminary Technical Data ADL5330 PR05134-0-12/04(PrK) OUTLINE DIMENSIONS REV. PrK | Page 5 of 5