White Electronic Designs W3E16M72S-XBX 16Mx72 DDR SDRAM FEATURES DDR SDRAM Rate = 200, 250, 266 Package: • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm BENEFITS 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CLK Four internal banks for concurrent operation Two data mask (DM) pins for masking write data Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military Temperature Ranges Organized as 16M x 72 Weight: W3E16M72S-XBX – 3.55 grams typical 40% SPACE SAVINGS Reduced part count Reduced I/O count • 34% I/O Reduction Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match Upgradeable to 32M x 72 density (W3E32M72S-XBX) GENERAL DESCRIPTION The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 268,435,456 bits. Each chip is internally configured as a quad-bank DRAM. Each of the chip’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. The 128 MB DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, * This product is subject to change without notice.. Actual Size W3E16M72S-XBX Monolithic Solution 11.9 11.9 11.9 66 22.3 TSOP 66 TSOP 66 TSOP 11.9 11.9 66 TSOP White Electronic Designs W3E16M72S-XBX 32 Area I/O Count February 2005 Rev. 7 5 x 265mm2 = 1328mm2 5 x 66 pins = 330 pins 1 25 S A V I N G S 800mm2 40% 219 Balls 34% White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX FIGURE 1 – PIN CONFIGURATION Top View 1 A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DQ0 DQ14 DQ15 VSS VSS A9 A10 A11 A8 VCCQ VCCQ DQ16 DQ17 DQ31 VSS B DQ1 DQ2 DQ12 DQ13 VSS VSS A0 A7 A6 A1 VCC VCC DQ18 DQ19 DQ29 DQ30 C DQ3 DQ4 DQ10 DQ11 VCC VCC A2 A5 A4 A3 VSS VSS DQ20 DQ21 DQ27 DQ28 D DQ6 DQ5 DQ8 DQ9 VCCQ VCCQ A12 DNU DNU DNU VSS VSS DQ22 DQ23 DQ26 DQ25 E DQ7 DQML0 VCC DQMH0 DQSH3 DQSL0 DQSH0 BA0 BA1 DQSL1 DQSH1 VREF DQML1 VSS NC DQ24 F CAS0# WE0# VCC CLK0 DQSL3 RAS1# WE1# VSS DQMH1 CLK1 G CS0# RAS0# VCC CKE0 CLK0# CAS1# CS1# VSS CLK1# CKE1 H VSS VSS VCC VCCQ VSS VCC VSS Vss VCCQ VCC J VSS VSS VCC VCCQ VSS VCC VSS VSS VCCQ VCC K CLK3# CKE3 VCC CS3# DQSL4 CLK2# CKE2 VSS RAS2# CS2# L NC CLK3 VCC CAS3# RAS3# DQSL2 CLK2 VSS WE2# CAS2# M DQ56 DQMH3 VCC WE3# DQML3 CKE4 DQMH4 CLK4 CAS4# WE4# RAS4# CS4# DQMH2 VSS DQML2 DQ39 N DQ57 DQ58 DQ55 DQ54 DQSH4 CLK4# DQ73 DQ72 DQ71 DQ70 DQML4 DQSH2 DQ41 DQ40 DQ37 DQ38 P DQ60 DQ59 DQ53 DQ52 VSS VSS DQ75 DQ74 DQ69 DQ68 VCC VCC DQ43 DQ42 DQ36 DQ35 R DQ62 DQ61 DQ51 DQ50 VCC VCC DQ77 DQ76 DQ67 DQ66 VSS VSS DQ45 DQ44 DQ34 DQ33 T VSS DQ63 DQ49 DQ48 VCCQ VCCQ DQ79 DQ78 DQ65 DQ64 VSS VSS DQ47 DQ46 DQ32 VCC NOTE: DNU = Do Not Use; to be left unconnected for future upgrades. NC = Not Connected Internally. February 2005 Rev. 7 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM WE0# RAS0# CAS0# WE# RAS# CAS# VREF VREF A0-12 A0-12 BA0-1 CLK0 CLK0# CKE0 CS0# DQML0 DQMH0 BA0-1 CLK CLK# CKE CS# DQML DQMH DQSL0 DQSH0 DQSL DQSH U0 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ0 = Y = Y = Y = Y = Y = Y DQ15 WE1# RAS1# CAS1# WE# RAS# CAS# VREF A0-12 CLK1 CLK1# CKE1 CS1# DQML1 DQMH1 BA0-1 CLK CLK# CKE CS# DQML DQMH DQSL1 DQSH1 DQSL DQSH U1 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ16 = Y = Y = Y = Y = Y = Y DQ31 WE2# RAS 2# CAS 2# WE# RAS# CAS# VREF A0-12 CLK2 CLK2# CKE2 CS2# DQML2 DQMH2 DQSL2 DQSH2 BA0-1 CLK CLK# CKE CS# DQML DQMH DQSL DQSH U2 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ32 = Y = Y = Y = Y = Y = Y DQ47 WE3# RAS 3# CAS 3# WE# RAS# CAS# VREF A0-12 CLK3 CLK3# CKE3 CS3# DQML3 DQMH3 DQSL3 DQSH3 BA0-1 CLK CLK CKE CS DQML DQMH DQSL DQSH U3 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ48 = Y = Y = Y = Y = Y = Y DQ63 WE4# RAS 4# CAS 4# WE# RAS# CAS# VREF A0-12 February 2005 Rev. 7 CLK4 CLK4# CKE4 CS4# DQML4 DQMH4 BA0-1 CLK CLK# CKE CS# DQML DQMH DQSL4 DQSH4 DQSL DQSH 3 U4 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ64 = Y = Y = Y = Y = Y = Y DQ79 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte. starting column location for the burst access. The 128MB DDR SDRAM operates from a differential clock (CLK and CLK#); the crossing of CLK going HIGH and CLK# going LOW will be referred to as the positive edge of CLK. Commands (address and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CLK. INITIALIZATION Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VCC and VCCQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VCCQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VCC is applied. Maintaining an LVCMOS LOW level on CKE during powerup is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access. Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. The pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a powersaving power-down mode. FUNCTIONAL DESCRIPTION Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the February 2005 Rev. 7 Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation. 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs BURST TYPE REGISTER DEFINITION MODE REGISTER Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 3. The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. (Except for bit A8 which is self clearing). The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1. READ LATENCY The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks. Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. Reserved states should not be used as unknown operation or incompatibility with future versions may result. TABLE 2 – CAS LATENCY BURST LENGTH ALLOWABLE OPERATING FREQUENCY (MHz) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. SPEED CAS LATENCY = 2 CAS LATENCY = 2.5 -200 ≤ 75 ≤ 100 -250 ≤ 100 ≤ 125 -266 ≤ 100 ≤ 133 OPERATING MODE When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four (where Ai is the most significant column address for a given configuration); and by A3-Ai when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. February 2005 Rev. 7 W3E16M72S-XBX The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 3 – MODE REGISTER DEFINITION BA1 A12 A11 A10 A9 BA0 A8 A7 A6 A5 A3 A4 A2 A1 A0 W3E16M72S-XBX TABLE 1 – BURST DEFINITION Burst Length Address Bus Starting Column Address Mode Register (Mx) 0* 0* Operating Mode CAS Latency BT 2 Burst Length * M14 and M13 (BA0 and BA1 must be "0, 0" to select the base mode register (vs. the extended mode register). Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved 4 Reserved 8 Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M12 M11 M10 M9 M8 M7 M6-M0 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Operating Mode All other states reserved EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 5. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. February 2005 Rev. 7 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 4 – CAS LATENCY T0 T1 T2 READ NOP NOP T2n T3 W3E16M72S-XBX FIGURE 5 – EXTENDED MODE REGISTER DEFINITION T3n BA1 BA0 A12 A11 A10 A9 CLK A8 A7 A6 A3 A2 A5 A4 A1 A0 Address Bus CLK COMMAND NOP 01 CL = 2 11 QFC# DS Operating Mode Extended Mode Register (Ex) DLL DQS DQ T0 T1 T2 T2n T3 E0 DLL 0 Enable 1 T3n Disable CLK E1 CLK COMMAND READ NOP NOP NOP CL = 2.5 E22 DQS DQ DATA TRANSITIONING DATA 0 Normal 1 Reduced QFC# Function 0 Disabled - Reserved E8 E7 E6 E5 E4 E3 E2, E1, E0 Operating Mode 0 0 0 0 0 0 0 0 0 0 Valid Reserved - - - - - - - - - - - Reserved E12 E11 E10 E9 Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ Drive Strength 1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register) 2. The QFE# function is not supported. DON'T CARE OUTPUT DRIVE STRENGTH DESELECT The normal full drive strength for all outputs are specified to be SSTL2, Class II. The DDR SDRAM supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. The DESELECT function (CS# HiGH) prevents new commands from being executed by the DDR SDRAM. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to the selected DDR SDRAM (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. DLL ENABLE/DISABLE The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. LOAD MODE REGISTER The Mode Registers are loaded via inputs A0-12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. COMMANDS ACTIVE The Truth Table provides a quick reference of available commands. This is followed by a written description of each command. The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided February 2005 Rev. 7 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX TRUTH TABLE – COMMANDS (NOTE 1) NAME (FUNCTION) DESELECT (NOP) (9) NO OPERATION (NOP) (9) ACTIVE (Select bank and activate row) ( 3) READ (Select bank and column, and start READ burst) (4) WRITE (Select bank and column, and start WRITE burst) (4) BURST TERMINATE (8) PRECHARGE (Deactivate row in bank or banks) ( 5) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) LOAD MODE REGISTER (2) CS# H L L L L L L L L RAS# X H L H H H L L L CAS# X H H L L H H L L WE# X H H H L L L H L ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code TRUTH TABLE – DM OPERATION NAME (FUNCTION) DM DQs WRITE ENABLE (10) L Valid WRITE INHIBIT (10) H X NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. A0-12 provide row address, and BA0, BA1 provide bank address. 4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. 7. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data. on inputs A0-12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the D/Qs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-8 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-8 February 2005 Rev. 7 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs is nonpersistent, so it must be issued each time a refresh is required. allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. Each DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125µs (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. AUTO PRECHARGE AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. The device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later. SELF REFRESH* The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “Don’t Care” during SELF REFRESH. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an explicit precharge command was issued at the earliest possible time, without violating tRAS (MIN).The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN). BURST TERMINATE The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR, because time is required for the completion of any internal refresh in progress. The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains open. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. AUTO REFRESH AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command February 2005 Rev. 7 W3E16M72S-XBX * Self refresh available in commercial and industrial temperatures only. 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on VCC, VCCQ Supply relative to Vss Voltage on I/O pins relative to VSS Operating Temperature TA (Mil) Operating Temperature TA (Ind) Storage Temperature, Plastic -1 to 3.6 -1 to 3.6 -55 to +125 -40 to +85 -55 to +150 W3E16M72S-XBX CAPACITANCE (NOTE 13) Unit V V °C °C °C Parameter Symbol Max Unit Input Capacitance: CLK CI1 8 pF Addresses, BA0-1 Input Capacitance CA 30 pF Input Capacitance: All other input-only pins CI2 9 pF Input/Output Capacitance: I/Os CIO 12 pF NOTE: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. BGA THERMAL RESISTANCE Description Symbol Max Units Notes Junction to Ambient (No Airflow) Theta JA 13.7 °C/W 1 Junction to Ball Theta JB 10.3 °C/W 1 Junction to Case (Top) Theta JC 3.9 °C/W 1 Note 1: Refer to PBGA Thermal Resistance Correllation application note at www.wedc.com in the application notes section for modeling conditions. February 2005 Rev. 7 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX DC Electrical Characteristics And Operating Conditions (Notes 1, 6) VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C Parameter/Condition Supply Voltage I/O Supply Voltage Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V) Input Leakage Address Current (All other pins not under test = 0V) Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC Output Levels: Full drive option High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) Output Levels: Reduced drive option High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) I/O Reference Voltage (6) I/O Termination Voltage (53) Symbol VCC VCCQ II II IOZ Min 2.3 2.3 -2 -10 -5 Max 2.7 2.7 2 10 5 Units V V µA µA µA IOH -12 – mA IOL 12 – mA IOHR -9 – mA IOLR 9 – mA VREF VTT 0.49 x VCCQ VREF - 0.04 0.51 x VCCQ VREF + 0.04 V V Max – VREF - 0.310 Units V V AC Input Operating Conditions (Notes 14, 28, 40) VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C Parameter/Condition Input High (Logic 1) Voltage: Input Low (Logic 0) Voltage: Symbol VIH (AC) VIL (AC) Min VREF + 0.310 – ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14) VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C Max 250Mbps Symbol 266Mbps 200Mbps Parameter/Condition Units OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 48) ICC0 625 600 mA OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle (22, 48) ICC1 850 775 mA PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; (23, 32, 50) ICC2P 20 20 mA IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (51) ICC2F 225 225 mA ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW (23, 32, 50) ICC3P 150 150 mA ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle (22) ICC3N 250 250 mA OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48) ICC4R 925 925 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22) ICC4W 800 800 mA AUTO REFRESH CURRENT SELF REFRESH CURRENT: CKE ≤ 0.2V tREF = tRC (MIN) (27, 50) ICC5 1225 1225 mA tREF = 7.8125µs (27, 50) ICC5A 30 30 mA Standard (11) ICC6 20 20 mA ICC7 2000 2000 mA OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 49) February 2005 Rev. 7 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS (NOTES 1-5, 14-17, 33) Parameter Access window of DQs from CLK/CLK# Symbol tAC 266Mbps CL2.5 200Mbps CL2 Min Max -0.75 +0.75 250Mbps CL2.5 200Mbps CL2 Min Max -0.8 +0.8 200Mbps CL2.5 150Mbps CL2 Min Max -0.8 +0.8 Units ns CLK high-level width (30) tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CLK low-level width (30) tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCK (2.5) 7.5 13 8 13 10 13 ns tCK (2) 10 13 10 13 13 15 tDH 0.5 0.6 0.6 ns ns Clock cycle time CL = 2.5 (45, 52) CL = 2 (45, 52) DQ and DM input hold time relative to DQS (26, 31) DQ and DM input setup time relative to DQS (26, 31) ns tDS 0.5 0.6 0.6 tDIPW 1.75 2 2 Access window of DQS from CLK/CLK# tDQSCK -0.75 DQS input high pulse width tDQSH 0.35 0.35 0.35 DQS input low pulse width tDQSL 0.35 0.35 0.35 DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26) tDQSQ Write command to first DQS latching transition tDQSS 0.75 DQS falling edge to CLK rising - setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CLK rising - hold time tDSH 0.2 0.2 0.2 tCK Half clock period (34) tHP tCH, tCL tCH, tCL tCH, tCL Data-out high-impedance window from CLK/CLK# (18, 42) tHZ Data-out low-impedance window from CLK/CLK# (18, 43) tLZ -0.75 -0.8 -0.8 ns Address and control input hold time (fast slew rate) (14) tIHF 0.90 1.1 1.1 ns Address and control input setup time (fast slew rate) (14) tISF 0.90 1.1 1.1 ns Address and control input hold time (slow slew rate) (14) tIHS 1 1.1 1.1 ns Address and control input setup time (slow slew rate) (14) tISS 1 1.1 1.1 ns LOAD MODE REGISTER command cycle time tMRD 15 16 16 ns DQ and DM input pulse width (for each input) (31) DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26) tQH Data hold skew factor tQHS +0.75 -0.8 0.5 1.25 ns -0.8 0.6 0.75 +0.75 1.25 0.75 +0.8 tHP - tQHS tCK 0.6 ns 1.25 tCK ns ns 1 ns 120,000 ns ACTIVE to PRECHARGE command (35) tRAS 40 tRAP 20 20 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 70 70 ns AUTO REFRESH command period (50) tRFC 75 80 80 ns ACTIVE to READ or WRITE delay tRCD 20 20 20 ns tRP 20 DQS read preamble (42) tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK ACTIVE bank a to ACTIVE bank b command tRRD 15 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 tCK DQS write preamble setup time (20, 21) tWPRES 0 DQS write postamble (19) tWPST 0.4 Write recovery time tWR 15 15 15 ns Internal WRITE to READ command delay tWTR 1 1 1 tCK Data valid output window (25) na 20 40 ns ACTIVE to READ with Auto precharge command PRECHARGE command period 120,000 ns tCK tHP - tQHS 1 40 +0.8 +0.8 tHP - tQHS 0.75 120,000 +0.8 20 0 0.6 tQH - tDQSQ 0.4 0 0.6 tQH - tDQSQ 0.4 ns 0.6 tQH - tDQSQ ns tREFC REFRESH to REFRESH command interval (Military temp only) (23) tREFC 35 Average periodic refresh interval (Commercial & Industrial temp only) (23) tREFI 7.8 Average periodic refresh interval (Military temp only) (23) tREFI 3.9 3.9 Terminating voltage delay to VCC (53) tVTD 0 0 0 ns Exit SELF REFRESH to non-READ command tXSNR 75 80 80 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK 12 70.3 tCK REFRESH to REFRESH command interval (Commercial & Industrial temp only) (23) February 2005 Rev. 7 70.3 ns 70.3 µs 35 35 µs 7.8 7.8 µs 3.9 µs White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs NOTES: 1. All voltages referenced to VSS. 2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 15. The CLK/CLK# input reference level (for timing referenced to CLK/CLK#) is the point at which CLK and CLK# cross; the input reference level for signals other than CLK/CLK# is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for ICC measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15 of each chip. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). VTT 50Ω Reference Point 30pF Output (VOUT) 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. W3E16M72S-XBX AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CLK/CLK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. VID is the magnitude of the difference between the input level on CLK and the input level on CLK#. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of the same. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open. Enables on-chip refresh and address counters. ICC specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. This parameter is not tested but guaranteed by design. tA = 25°C, f = 1 MHz Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. FIGURE A – PULL-DOWN CHARACTERISTICS FIGURE B – PULL-UP CHARACTERISTICS 0 160 Maximum 140 -20 Minimum -40 120 Nominal high IOUT (mA) 100 IOUT (mA) Nominal low -60 80 Nominal low 60 Minimum -80 -100 Nominal high -120 -140 40 -160 20 -180 0 Maximum -200 0.0 0.5 1.0 1.5 2.0 2.5 0.0 February 2005 Rev. 7 0.5 1.0 1.5 2.0 2.5 VCCQ - VOUT (V) VOUT (V) 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CLK and CLK# input slew rate must be ≥ 1V/ns (≥2V/ns differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VCC must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CLK and CLK# inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. FIGURE C – PULL-DOWN CHARACTERISTICS W3E16M72S-XBX d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V. The voltage levels used are derived from a minimum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VCC and VCCQ must track each other. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ(MAX) and the last DVW. tHZ(MAX) will prevail over tDQSCK(MAX) + tRPST(MAX) condition. tLZ(MIN) will prevail over tDQSCK(MIN) + tRPRE(MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. Reserved for future use. Reserved for future use. Random addressing changing 50% of data changing at every transfer. Random addressing changing 100% of data changing at every transfer. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. ICC2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.” Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles before any READ command. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. VCCQ, VTT and VREF must be equal to or less than VCC + 0.3V. Alternatively VTT may be 1.35V max during power-up even if VCC/VCCQ are 0V, provided a minimum of 42 Ω of series resistance is used between the VTT supply and the input pin. Once initialized, VREF must always be powered within the specified range. FIGURE D – PULL-UP CHARACTERISTICS 0 80 Maximum -10 70 60 Nominal high 40 IOUT (mA) IOUT (mA) 50 Nominal low -20 Minimum -30 Nominal low -40 -50 30 Minimum Nominal high 20 -60 10 -70 0 -80 Maximum 0.0 0.5 1.0 1.5 2.0 0.0 2.5 February 2005 Rev. 7 0.5 1.0 1.5 2.0 2.5 VCCQ - VOUT (V) VOUT (V) 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA) Bottom View 32.1 (1.264) MAX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T R P N M L K J H G F E D C B A 19.05 (0.750) NOM 1.27 (0.050) NOM 25.1 (0.988) MAX 0.61 (0.024) NOM 219 X Ø 0.762 (0.030) NOM 2.03 (0.080) MAX 19.05 (0.750) NOM ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES February 2005 Rev. 7 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX ORDERING INFORMATION W 3E 16M 72 S - XXX B X WHITE ELECTRONIC DESIGNS CORP. DDR SDRAM CONFIGURATION, 16M x 72 2.5V Power Supply DATA RATE (MHz) 200 = 200Mbps 250 = 250Mbps 266 = 266Mbps PACKAGE: B = 219 Plastic Ball Grid Array (PBGA) DEVICE GRADE: M = Military I = Industrial C = Commercial February 2005 Rev. 7 -55°C to +125°C -40°C to +85°C 0°C to +70°C 16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72S-XBX Document Title 16M x 72 DDR SDRAM Multi-Chip Package Revision History Rev # History Release Date Status Rev 0 Initial Release April 2002 Advanced Rev 1 Changes (Pg. 1, 10) 1.1 Add Currents to data sheet in place of TBD September 2002 Advanced Rev 2 Changes (Pg. 1, 8, 9, 10, 11, 12) 2.1 Change product status from Advanced to Preliminary November 2002 Preliminary Rev 3 Changes (Pg. 1, 10, 14, 15, 16) 3.1 Change ICCI to 825 mA @ 250/266 MHz 3.2 Change ICC1 to 775 mA @ 200 MHz 3.3 Change ICC4R to 1250 mA @ 250/266 MHz 3.4 Change ICC4R to 1075 mA @ 200 MHz 3.5 Change ICC4W to 1250 mA @ 250/266 MHz 3.6 Change ICC4W to 1075 mA @ 200 MHz 3.7 Change ICC6A to ICC6 3.8 Change ICC8 to ICC7 3.9 Change ICC7 to 2000 mA @ 250/266 MHz 3.10 Change ICC7 to 1875 mA @ 200 MHz 3.11 Add Thermal Resistance Table December 2002 Preliminary Rev 4 Changes (Pg. 1, 14, 15) 4.1 Change mechanical drawing to new style 4.2 Change part number to new style November 2003 Preliminary Rev 5 Changes (Pg. 1, 10, 11, 12, 14, 15) 5.1 Change TREF from 70.3µs max to 35µs max for Military temperature only 5.2 Change TREFI from 7.8µs max to 3.9µs max for Military temperature only 5.3 Change Thermal Resistance Table ΘJC, ΘJB, ΘJA 5.4 Add Note 53 for VTT, pg. 14 April 2004 Preliminary Rev 6 Changes (Pg. 1, 10, 11, 12, 13, 16, 17) 6.1 Change status to Final 6.2 Correct typographical errors September 2004 Final Rev 7 Changes (Pg. 1, 11, 17) 7.1 Update ICC Specifications table February 2005 Final February 2005 Rev. 7 17 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com