AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL (Positive ECL) is nothing more than supplying any ECL device with a positive power supply (VCC = +5.0 V, VEE = 0 V). In addition, ECL uses differential data transmission technology, which results in better noise immunity. Since the common mode noise is coupled onto the differential interconnect, it will be seen as a common mode modulation and will be rejected. With the trend towards low voltage systems, a new generation of ECL circuitry has been developed. The Low Voltage NECL (LVNECL) devices work using negative –3.3 V or –2.5 V power supply, or more popular positive power supplies, VCC = +3.3 V or +2.5 V and VEE = GND as LVPECL. LVECL maintains 750 mV output swing with a 0.9 V offset from VCC, which makes them ideal as peripheral components. The temperature compensated (100EL, 100LVEL, 100EP, 100LVEP) output DC levels for the different supply levels are shown in Table 1. ECL outputs are designed as an open emitter, requiring a DC path to a more negative supply than VOL. (see AND8020 for ECL Termination information). ECL standard DC input levels are also relative to VCC. Many devices are available with Voltage Input HIGH Common Mode Range (VIHCMR). These differential inputs allow processing signals with small VINPPMIN (down to 200 mV, 150 mV or even 50 mV signal levels) within an appropriate offset range. The VIHCMR ranges of ECL devices are listed in each respective data sheets. Introduction Recent growth in high−speed data transmission between high−speed ICs demand more bandwidth than ever before while still maintaining high performance, low power consumption and good noise immunity. Emitter Coupled Logic (ECL) recognized the challenge and provided high performance and good noise immune devices. ECL migrated toward low voltages to reduce the power consumption and to keep up with current technology trends by offering 3.3 V and 2.5 V Low Voltage ECL (LVECL) devices. LVDS (Low Voltage Differential Signaling) technology also addresses the needs of current high performance applications. LVDS as specified in ANSI/TIA/EIA−644 by Data Transmission Interface committee TR30.2 and IEEE 1596.3 SCI−LVDS by IEEE Scalable Coherent Interface standard (SCI) is a high speed, low power interface that is a solution in many application areas. LVDS provides an output swing of 250 mV to 400 mV with a DC offset of 1.2 V. External resistor components are required for board−to−board data transfer or clock distribution. LVECL and LVDS are both differential voltage signals, but with different output amplitude and offset. The purpose of this documentation is to show the interfacing between LVECL and LVDS. In addition, it gives interface recommendations to and from 5.0 V supplied PECL devices and negative supplied ECL or NECL Semiconductor Components Industries, LLC, 2003 October, 2003 − Rev. 8 1 Publication Order Number: AN1568/D AN1568/D Table 1. MC100EXXX/MC100ELXXX/LVELXXX/EPXXX/LVEPXXX (TA = 0°C to +85°C) Symbol Parameter 2.5 V LVPECL (Note 1) 3.3 V LVPECL (Note 1) 5.0 V PECL (Note 1) NECL Unit VCC Positive Supply Voltage +2.5 +3.3 +5 GND V VEE Negative Supply Voltage GND GND GND −5.2, −4.5, −3.3 or −2.5 V VOH Maximum Output HIGH Level 1.680 2.480 4.180 −0.820 V VOH Typical Output HIGH Level 1.555 2.355 4.055 −0.945 V VOH Minimum Output HIGH Level 1.430 2.230 3.930 −1.070 V VOL Maximum Output LOW Level 0.880 1.680 3.380 −1.620 V VOL Typical Output LOW Level 0.755 1.555 3.255 −1.745 V VOL Minimum Output LOW Level 0.630 1.430 3.130 −1.870 V 1. All levels vary 1:1 with VCC and loaded with 50 to VCC − 2.0 V. Z = 50 SIGNAL VOLTAGE LVDS Levels As the name indicates, the LVDS main attribute is the low voltage amplitude levels compared to other data transmission standards, as shown in Figure 1. The LVDS specification states 250 mV to 400 mV output swing for driver/transmitter (VOUTPP). The low voltage swing levels result in low power consumption while maintaining high performance levels required by most users. In addition, LVDS uses differential data transmission technology equivalent to ECL. Furthermore, LVDS technology is not dependent on specific power supply levels like ECL technology. This signifies an easy migration path to lower supply voltages such as 3.3 V, 2.5 V, or lower voltages while still maintaining the same signaling levels and high performance. ON Semiconductor currently provides a 2.5 V 1:5 dual differential LVDS Clock Driver/Receiver (MC100EP210S). LVDS 100 Figure 2. LVDS Output Definition LVDS receivers require 200 mV minimum input swing within the input voltage range of 0 V to 2.4 V and can tolerate a minimum of 1.0 V ground shift between the driver’s ground and the receiver’s ground, since LVDS receivers have a typical driver offset voltage of 1.2 V. The common mode range of the LVDS receiver is 0.2 V to 2.2 V, and the recommended LVDS receiver input voltage range is from 0 V to 2.4 V. Common mode range of LVDS is similar to the theory of Voltage Input HIGH Common Mode Range (VIHCMR) of ECL devices. Currently more LVDS standards are being developed as LVDS technology gains in popularity. BLVDS PECL Bus LVDS (BLVDS) was developed for multipoint applications. This standard is targeted at heavily loaded back planes, which reduces the impedance of the transmission line by 50% or more. By providing increased drive current, the double termination seen by the driver will be compensated. 3.3 V LVPECL 2.5 V LVPECL Z = 50 LVDS 3.3 V LVTTL/LVCMOS M−LVDS NECL/LVNECL TIA TR30.2 standards group is developing another multipoint LVDS application called Multipoint LVDS (M−LVDS). The maximum data rate is 500 Mbps. Figure 1. Comparison of Output Voltage Levels Standards (Figure not to Scale) LVDS require a 100 load resistor between the differential outputs to generate the Differential Output Voltage (VOD) with a maximum current of 2.5 mA flowing through the load resistor. This load resistor will terminate the 50 controlled characteristic impedance line, which prevent reflections and reduces unwanted electromagnetic emission (Figure 2). http://onsemi.com 2 AN1568/D GLVDS and SLVS Interfacing Common mode range inputs are capable of processing signals with 150 mV to 400 mV amplitude. The ECL input processes signals up to 1.0 V amplitude. The DC voltage levels should be within the voltage input HIGH common mode range (VIHCMR). To interface between these two voltage levels, capacitive coupling can be used. Only clock or coded signals should be capacitively coupled. A capacitive coupling of NRZ signals will cause problems, which can require a passive or active interfacing. Ground referenced LVDS (GLVDS) is similar to LVDS except the driver output voltage offset is nearer to ground. The advantage of GLVDS is the use of very low power supply voltages (0.5 V). Similar standard to GLVDS is SLVS (Scalable Low−Voltage Signaling for 400 mV) by JEDEC. The interface is terminated to ground with 400mV swing and a minimum supply voltage of 0.8 V. LVDM LVDM is designed for double 100 −terminated applications. The driver’s output current is two times the standard LVDS, thus producing LVDS characteristic levels. Table 2. LVDS LEVELS LVDS Specification BLVDS Specification M−LVDS Specification GLVDS Specification LVDM Specification Parameter Min Max Min Max Min Max Min Max Min Max Unit VPP Output Differential Voltage 250 400 240 500 480 650 150 500 247 454 mV VOS Output Offset Voltage 1125 1275 1225 1375 300 2100 75 250 1.125 RL Load Resistor 27 50 IOD Output Differential Current Symbol Condition Transmitter 100 50 Internal To Rx 2.5 4.5 9 17 9 13 0 2400 0 2400 −1000 3800 Adjustable mV 50 6 mA Receiver Input Voltage Range Differential HIGH Input Threshold Differential LOW Input Threshold +100 −100 +100 −100 −500 +50 −50 2. Vgpd is the voltage of Ground Potential Delta across or between boards. http://onsemi.com 3 1000 0 +100 −100 −100 2400 MV Vgpd < 950 mV (Note 2) +100 mV Vgpd < 950 mV (Note 2) mV Vgpd < 950 mV (Note 2) AN1568/D Capacitive Coupling LVDS to ECL In the layout for both interfaces, the resistors and the capacitors should be located as close as possible to the ECL input to insure reduced reflection and increased signal integrity. Capacitive Coupling LVDS to ECL Using V BB Several ECL devices provide an externally accessible VBB (VBB ≈ VCC –1.3V) reference voltage. This ECL reference voltage can be used for differential capacitive coupling. The 10 nF capacitor can be used to decouple VBB to GND. (Figure 3) Z = 50 LVDS Z = 50 Capacitive Coupling ECL to LVDS The ECL output requires a DC current path to VEE; therefore, the pulldown termination resistors, RT, are connected to VEE. The Thevenin resistor pair represent the termination of the transmission line Z = R1 || R2 and generates an appropriate DC offset level of 1.2 V. (Figure 5) 10 pF 100 ECL 3.3 V VBB 10 pF 1 k R1 130 Z = 50 10 pF 1 k 10 nF ECL Figure 3. Capacitive Coupling LVDS to ECL Using VBB An example of capacitive coupled LVPECL (ECLinPS Plus Device) to LVDS is shown below. (Figure 6) 2.5 V or 3.3 V VCC = GND VEE = −5.0 V R1 = 1.2 k R2 = 3.4 k VCC = GND VEE = −3.3 V R1 = 680 R2 = 1.0 k VCC = GND VEE = −2.5 V R1 = 100 R2 = 90 Z = 50 LVPECL R1 R1 237 10 pF 100 ECL R2 43 R1 237 R3 3.9 k 3.3 V R3 3.9 k 10 pF 10 pF R4 2 k LVDS R4 2 k Figure 6. Capacitive Coupling LVPECL to LVDS 10 pF R2 3.3 V R2 43 VCC R1 R2 80 VEE Table 3. Examples: LVDS 10 pF R2 80 RT Figure 5. Capacitive Coupling ECL to LVDS If VBB reference voltage is not available, equivalent DC voltage can be generated using a resistor divider network. The resistor values depend on VCC and VEE voltages (Table 3). Stability is enhanced during null signal conditions if a 50 mV differential voltage is maintained between the divider networks. (Figure 4) Z = 50 LVDS Z = 50 RT Capacitive Coupling LVDS to ECL with External Biasing R1 130 Capacitive Coupling ECL to LVDS Using VOS Reference Voltage R2 Some LVDS devices supply external offset reference voltage (VOS), which can be used for capacitive coupling. When the transmission line is very short, a parallel VEE Figure 4. Capacitive Coupling LVDS to ECL with External Biasing http://onsemi.com 4 AN1568/D 2.5 V termination should be used and placed as close as possible to the coupling capacitors. (Figure 7) VCC ZO 3.3 V 100 LVPECL Z = 50 LVDS ZO 100 k 10 pF RT ECL RT LVDS Z = 50 10 pF 1 k 50 50 Figure 9. Interfacing 2.5 V LVPECL to LVDS with Internal 100 Termination Resistor VOS= 1.2 V 1 k VTT 1.50 V 2.5 V LVPECL Output Figure 7. Capacitive Coupling ECL to LVDS Using VOS Reference Voltage LVDS Input 720 mV 0.78 V Direct Interfacing Where RT = 75 Interfacing from 2.5 V LVPECL to LVDS Figure 10. PSPICE Simulation Levels of 2.5V LVPECL to LVDS Interface with Example Resistor Values Provided that the LVDS receiver can tolerate large input voltage peak to peak amplitude, 2.5 V LVPECL can be directly interfaced to LVDS receiver using proper ECL termination. 2.5 V LVPECL will be able to drive LVDS receiver with and without internal 100 termination resistor. (See Figures 8, 9 and 10). 2.5 V Furthermore, sreies termination can be used to reduce the amplitude of the signal as described in AND8020 application note, by placing RS resistor between the driver and the transmission line. (See Figures 11, 12 and 13). VCC 2.5 V VCC ZO LVPECL ZO RT 100 LVDS RS ZO RS ZO LVPECL RT RT Figure 8. Interfacing 2.5 V LVPECL to LVDS with External 100 Termination Resistor 100 LVDS RT Figure 11. Interfacing 2.5 V LVPECL to LVDS with Series RS and External 100 Termination Resistor http://onsemi.com 5 AN1568/D 2.5 V VCC RS ZO RS ZO 100 LVPECL equations may give non−standard resistor values and when choosing resistors off the shelf, to avoid cutoff condition under worst−case scenario. 3.3 V LVDS ZO RT VCC RT LVPECL ZO ZO Figure 12. Interfacing 2.5 V LVPECL to LVDS with Series RS and Internal 100 Termination Resistor R1 ZO 1.30 V 2.5 V LVPECL Output 100 LVDS R1 R2 LVDS Input 430 mV R2 Figure 14. Interfacing 3.3 V LVPECL to LVDS 0.87 V Where RT = 75 RS = 43 3.3 V Figure 13. PSPICE Simulation Levels of 2.5V LVPECL to LVDS Interface with Series RS Resistor ZO VCC LVPECL Interfacing from 3.3 V LVPECL to LVDS ZO Since the output levels VOH and VOL of 3.3 V LVPECL are more positive than the input range of LVDS receiver, special interface is required. (See Figures 14 and 15). Furthermore, the open emitter design of the ECL output structure need proper termination, which can be incorporated with the resistor divider network to generate a proper LVDS DC levels (eq. 1). R1 R2 RT ZO R1 LVDS ZO R2 R2 (eq. 1) Figure 15. Interfacing LVPECL to LVDS with Internal 100 Termination Resistor The resistor divider network will divide the output common mode voltage of LVPECL (VCM(LVPECL)) to input common mode voltage of LVDS (VCM(LVDS)). VCM(LVDS) R2 R1 R2 VCM(LVPECL) 100 R1 Examples: For 50 controlled impedance, the resistor values for 3.3V LVPECL converted to LVDS voltage levels are as follows: (eq. 2) Where: RT = Termination Resistor VCM(LVPECL) = Common Mode Voltage VCM(LVDS) = Common Mode Voltage R1 = 55 R2 = 95 RT = 150 VCM(LVPECL) = 1.9 V VCM(LVDS) = 1.2 V 3.3 V LVPECL will be able to drive LVDS receiver with and without internal 100 termination resistor. The above http://onsemi.com 6 AN1568/D 3.3 V LVPECL Interfacing from PECL to LVDS LVDS Since the output levels VOH and VOL of 5 V PECL are more positive than the input range of LVDS receiver, special interface is required. (See Figure 18). Furthermore, the open emitter design of the ECL output structure need proper termination, which can be incorporated with the resistor divider network to generate a proper LVDS DC levels (eq. 3). 2.37 V 850 mV VCM(LVPECL) 1.39 V 1.52 V 320 mV VCM(LVDS) R1 R2 RT 1.07 V The resistor divider network will divide the output common mode voltage of PECL (VCM(PECL)) to input common mode voltage of LVDS (VCM(LVDS)). Figure 16. PSPICE Simulated Voltage Levels of 3.3 V LVPECL to LVDS Interface with Example Resistor Values V (LVDS) R2 CM R1 R2 VCM(PECL) Interfacing from LVDS to LVPECL The input common mode range of the low voltage ECL line receivers are wide enough to process LVDS signals. (Figure 17) 3.3 V The above equations may give non—standard resistor values and when choosing resistors off the shelf, to avoid cutoff condition under worst−case scenario. Z = 50 100 Z = 50 (eq. 4) Where: RT = Termination Resistor VCM(PECL) = Common Mode Voltage VCM(LVDS) = Common Mode Voltage 2.5 V or 3.3 V LVDS (eq. 3) LVPECL 5V ZO VCC Figure 17. Interfacing LVDS to LVPECL PECL ZO This direct interface is possible for all ECL devices with sufficiently low minimum differential input HIGH common mode range inputs. A differentially operated receiver’s VIHCMR minimum must be 1.2 V or less (see device data sheet). ZO R1 R1 LVDS ZO Table 4. LVDS Input Compatible Devices R2 R2 EP14 LVEP210S LVEL37 EL56 EP809 LVE222 LVEL39 EL91 LVEP11 LVEL05 LVEL40 SG11 Figure 18. Interfacing 5 V PECL to LVDS LVEP14 LVEL11 LVEL51 SG14 LVEP16 LVEL13 LVEL56 SG16 LVEP17 LVEL14 LVEL92 SG16M Examples: For 50 controlled impedance, the resistor values for 5V PECL converted to LVDS voltage levels are as follows: LVEP34 LVEL16 EL13 SG16VS LVEP56 LVEL17 EL14 SG53A LVEP91 LVEL29 EL17 SG72A LVEP111 LVEL32 EL29 SG86A LVEP210 LVEL33 EL39 SG111 R1 = 134 R2 = 66 RT = 200 VCM(PECL) = 3.65 V VCM(LVDS) = 1.2 V http://onsemi.com 7 AN1568/D 5 V PECL LVDS 3.3 V 5V Z = 50 4.05 V 800 mV VCM(PECL) LVDS Z = 50 100 PECL 1.34 V 3.25 V RT 270 mV VCM(LVDS) Figure 20. Interfacing LVDS to PECL 1.07 V Figure 19. PSPICE Simulated Voltage Levels of 5 V PECL to LVDS Interface with Example Resistor Values Interfacing Between NECL to LVDS ON Semiconductor has developed level translators to interface between the different voltage levels. The MC100EP90 translates from negative supplied ECL to LVPECL. The interface from LVPECL to LVDS inputs is described above. (Figure 21) Interfacing from +3.3 V LVDS to +5.0 V PECL To translate LVDS signals to PECL a differential ECL device with extended common mode range inputs (See Table 4) can be used to process and translate LVDS signals when supplied with 5.0 V 5% supply voltage. (See Figure 20) GND RT 3.3 V 3.3 V LVPECL Interface LVPECL to LVDS MC100EL90 or MC100EP90 NECL LVDS LVPECL RT RT −3.3 V, −4.5 V or −5.2 V −3.3 V, −4.5 V or −5.2 V Figure 21. Interfacing from NECL to LVDS If VCC = +5 V 5% supply and a VEE = –5.2 V ± 5% supply is available the MC10E1651 can be used. To interface from LVDS to negative supplied ECL the common mode range (VIHCMR) of the MC100LVEL91 for –3.3 V supply and the MC100EL91 for –4.5 V/–5.2 V supply is wide enough to process LVDS signals. (See Figure 22) 3.3 V 3.3 V GND Z = 50 LVDS Z = 50 100 LVEL91 or LVEP91 LVEL91: −3.3 V, EL91: −4.5 V, −5.2 V NECL RT Figure 22. Interfacing from LVDS to NECL http://onsemi.com 8 RT −3.3 V, −4.5 V, or −5.2 V AN1568/D Notes http://onsemi.com 9 AN1568/D ECLinPS Plus is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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