www.fairchildsemi.com Application Note AN4129 Green Current Mode PWM Controller FAN7601 1. Introduction This application note describes the operation and features of the FAN7601. This device is a BCDMOS programmable frequency current mode PWM controller which is designed for off-line adapter applications and auxiliary power supplies. To reduce power loss at light and no load, the FAN7601 operates in burst mode and it includes a start-up switch to reduce the losses in the start-up circuit. Because of the internal start-up switch and burst mode operation, it is possible to supply an output power of 0.5W with under 1W input power when the input line voltage is 265V. On no load condition, input power is under 0.3W. The FAN7601 offers a latch protection pin for the protection of the system e.g. over voltage protection and/or thermal shutdown. The internal over voltage protection function shuts down the IC operation when the supply voltage reaches 19V. In addition, a soft start function is provided, and the soft start time can be varied. Figure 1 shows a block diagram for the FAN7601. It contains the following blocks. • Start-up circuit and reference • Oscillator • Soft start and latch • Current sense and feed back • Burst mode • Output drive Vref 8 Vstr 1 7 Vcc 5V Ref Rt/Ct 4 Enable OSC Start-up Circuit UVLO Vref + − OVP + − 19V 12V/8V 12uA 1.5V Latch/SS 3 S Q R 6 OUT OVP + − S Q R 2.5V 1V GND 5 + − Start-up Circuit Reset Circuit + − Delay Circuit 0.97V/0.9V + − − 2 CS/FB Latch/SS 1V Figure 1. Internal Block Diagram of the FAN7601 Rev. 1.0.1 ©2003 Fairchild Semiconductor Corporation AN4129 APPLICATION NOTE 2. Device Block Description 1. Start-up Circuit And Reference The FAN7601 contains a start-up switch to reduce power loss in the external start-up circuit of conventional PWM converters. The internal start-up circuit charges the Vcc capacitor with a 1mA current source if the line is connected until the soft start is completed as shown in Fig. 2. The soft start function starts when the Vcc voltage reaches the start threshold voltage(typically 12V) and it ends when the LATCH/SS pin voltage reaches 1V. The internal start-up circuit starts charging the Vcc capacitor again if the Vcc voltage is lowered to the minimum operating voltage (typically 8V). In such a case the UVLO block shuts down the output drive circuit and some other blocks to reduce the IC current, and the soft start capacitor is discharged to zero voltage. If the Vcc voltage reaches the start threshold voltage, the IC starts switching again and the soft start capacitor is charged from zero voltage. The internal start-up circuit supplies current until the soft start is completed . current is supplied to the Vcc capacitor from the Vcc winding. Therefore the Vcc capacitor must be large enough to supply sufficient current during the soft start time when starting up. The value of the Vcc capacitor is determined by (1) where 4V is the UVLO hysteresis and 2mA is the IC operating current and 1mA is the start-up current. Tss ⋅ ( 2mA – 1mA + Q g ⋅ f sw ) C Vcc > -----------------------------------------------------------------------------4V Figure 4 shows the Vcc voltage when starting up with a 47uF capacitor and a FQPF7N60 MOSFET. The input line voltage is 265V and the soft start time is about 40ms. VTH Vcc VTL Start-up Current Soft Start Voltage Vcc 1.5V 1V VTH Soft Start Time VTL Start-up Current 1.5V 1V (1) t Figure 3. Typical Start-up Sequence for FAN7601 Soft Start Voltage Soft Start Time t Figure 2. Start-up Current and Vcc Voltage Figure 3 shows a typical start-up sequence for the FAN7601. The Vcc voltage should be higher than the minimum operating voltage at start-up to enter a steady state. If the Vcc voltage is higher than 19V, the over voltage protection function works. There is some delay in the over voltage protection circuit. The Vcc capacitor can be selected according to the soft start time and total gate charge(Qg) of the MOSFET. In the data sheet, the operating supply current is measured with a 1nF capacitor connected at the OUT pin. Therefore the real operating current necessary for the IC operation excluding the MOSFET drive is typically 2mA. During the soft start period (Tss), the Vcc capacitor is charged by a 1mA start-up current from the Vstr pin and the Vcc capacitor is discharged by a 2mA IC operating current and the MOSFET gate drive current. The MOSFET gate drive current is Qg×fsw. Qg increases according to the MOSFET drain source voltage, therefore the drive current is maximum when the input line voltage is highest. During the soft start period , the converter output voltage is very low, so few 2 Figure 4. Vcc Voltage Waveform at Start-up The FAN7601 provides the Vref pin. The reference output voltage is 5V. Because this voltage is the reference of the IC operation, a 100nF ceramic capacitor must be connected between the Vref pin and the GND pin to filter the switching noise as close as possible to the IC. ©2003 Fairchild Semiconductor Corporation APPLICATION NOTE AN4129 2. Oscillator The oscillator frequency is programmed by selecting the values of Rt and Ct. The capacitor Ct is charged from the 5V reference through the resistor Rt to approximately 2.5V and discharged to 1.25V by an internal current sink. Figure 5 shows the oscillator frequency characteristics according to the variation of Rt and Ct. The values of Rt and Ct can be chosen with reference to Fig. 5. 1 R1 3 Latch NTC Frequency (kHz) 8 7 2 PNP 6 /SS 5 4 Css R2 1000 Vref Ct= 680pF 820pF 1nF 2.2nF 3.3nF 4.7nF 8.2nF 10nF 100 10 Figure 6. Thermal Protection Circuit Figure 7 shows an output over voltage protection circuit. If the output voltage exceeds the sum of the zener diode voltage and the photo coupler forward voltage drop, then the capacitor Css is charged. In parallel with Css, a 1MΩ resistor is connected because of the leakage current of the photo coupler. If a 1MΩ is not connected the leakage current of the photo coupler charges the Css up, and the latch protection operates abnormally. 1 0 10 20 30 40 50 Vcc Rt (kΩ) Vout 1 Figure 5. Oscillator Frequency Characteristics 3. Soft Start and Latch The 12uA current source charges the soft start capacitor Css when the Vcc voltage reaches the start threshold voltage. The soft start ends when the Latch/SS pin voltage becomes 1V and the Latch/SS pin is charged up to 1.5V. The soft start capacitor is reset when the Vcc voltage is lower than the minimum operating voltage. The soft start time Tss is calculated by (2). Tss = Css/12µA (2) The latch protection is provided to protect the system. The latch protection pin can be used for output over voltage protection and/or thermal protection etc. If the Latch/SS pin voltage is made greater than 2.5V by the external circuit, then the IC is shut down. The latch protection is reset when the Vcc voltage is lower than 5V. Figure 6 shows a thermal protection circuit which uses an NTC thermistor. As the temperature rises the resistance of the NTC drops so the base voltage of the PNP transistor drops. Then the PNP transistor turns on and charges the Css. When the Latch/SS pin voltage is higher than 2.5V, the IC goes to the shut down mode. The exact values of resistors and NTC must be selected by an experiment because the VBE(sat) of PNP transistors and the leakage current of Css vary according to the temperature. ©2003 Fairchild Semiconductor Corporation 2 4 1 Latch 3 /SS 3 2 4 Css 1M Zener Diode Figure 7. Output Over Voltage Protection Circuit 4. Current Sense and Feedback The FAN7601 performs current sensing and output voltage feedback with only one pin. To achieve the two functions with one pin, an internal LEB(Leading Edge Blanking) circuit for filtering current sensing noise is not included because an external RC filter is necessary to add output voltage feedback and current sensing information. Figure 8 shows the current sensing and feedback circuits. Rs is the current sensing resistor for sensing the switch current. The current sensing information is filtered by an RC filter composed of Rf and Cf. The current Ifb flowing through the photo transistor varies according to the feedback information and add an offset voltage on the sensed current information as shown in Fig. 8 and Fig. 9. When the CS/FB pin voltage touches 1V, the output drive circuit turns the MOSFET off. The higher the DC offset is, the shorter the switch-on time is. By varying the Ifb, the duty cycle is con- 3 AN4129 APPLICATION NOTE trolled. 8 Vcc Rfb Current Sense Comparator + − − 3 Latch/SS CS/FB 7 Out Ifb 5 Rf PN2907 Isw Cf Rs 1V Figure 10. Circuit for Improving the Turn-Off Characteristic Figure 8. Current Sensing and Feedback Circuit 1V 3. Design Example 1V CS/FB CS/FB On Time To MOSFET Gat 6 DC Offset DC Offset On Time A 50W adapter is designed to illustrate the design procedure. The system parameters are as follows. - Maximum output power(Po) : 50W - Input voltage range : 85Vrms~265Vrms - Output voltage(Vo) : 12.1V - AC line frequency(fac) : 60Hz 5. Burst Mode - Adapter efficiency(η) : > 80% The FAN7601 contains a burst mode block to reduce power loss at light and no load. A hysteresis comparator senses the CS/FB offset voltage for the burst mode. The FAN7601 enters burst mode when the offset voltage of the CS/FB pin is higher than 0.97V and exits the burst mode while the offset voltage is lower than 0.9V. The offset voltage is sensed during the switch-off time. In the burst mod block, there are about 4~8 switching cycles delay to filter the noise. By this burst mode, a power consumption of less than 1W can be achieved in standby mode. - Switching frequency(fsw) : 91kHz GND GND (a) Heavy Load Condition (b) Light Load Condition Figure 9. CS/FB Pin Voltage Waveforms 6. Output Drive The FAN7601 contains a single totem-pole output stage, designed specifically for a direct drive of a power MOSFET. The drive output is capable of up to 100mA peak current with typical rise and fall times of 45ns, 35ns respectively with a 1.0nF load. Additional circuitry has been added to keep the drive output in a sinking mode whenever the UVLO is active. This characteristic eliminates the need for an external gate pull-down resistor. The output drive capability can be improved by adding one PNP bipolar transistor as shown in Fig. 10. In general, the on-resistance is high to prevent voltage spike at turn-on, only the turn-off characteristic is improved. 4 1. DC Link Capacitor and Bridge Diode The DC link voltage becomes minimum when the output power is maximum and input line voltage is lowest. The minimum DC link voltage can be calculated using (3). Vdc_min = 2 Po_max 2 ⋅ Vac_min – -------------------------------η ⋅ Cdc ⋅ fac (3) If the minimum voltage is chosen then the capacitance can be calculated by (4). Po_max Cdc > ------------------------------------------------------------------------------------------2 2 η ⋅ fac ⋅ ( 2Vac_min – Vdc_min ) (4) If we choose the minimum voltage to be 70% of the peak line voltage( 2 ⋅ 85V ) then Cdc must be larger than 142uF. The selected value is 150uF. Figure 11 shows an experimental result for a 50W demo board with a 150uF capacitor. Because the measured efficiency is 84%, the minimum voltage is about 90V. ©2003 Fairchild Semiconductor Corporation APPLICATION NOTE AN4129 The bridge diode conduction time can be calculated by (5) and the diode RMS current can be calculated by (6). Vdc_min 1 tc = -------------------- × arc cos -------------------------------------- 2π ⋅ fac 2 ⋅ Vac_min Vdc_link (5) 2 ⋅ fac I BD ( RMS ) = 2 ⋅ ( 2 ⋅ Vac_min – Vdc_min ) ⋅ Cdc ⋅ ---------------3 ⋅ tc (6) Vac Iac The calculated value is 1.3A and the selected bridge diode is KBP206(600V/2A). 2. Transformer Design Since 2001, the European Commission has been regulating no load losses for AC adapters, battery chargers and external power supplies under 75W. Table 1 shows the regulation target specification. Figure 11. DC Link Voltage and Current Waveforms Table 1: European Commission Regulation Specification No Load Power Consumption Rated Input Power Phase 1 1.1.2001 Phase 2 1.1.2003 Phase 3 1.1.2005 ≥ 0.3W and < 15W 1.0W 0.75W 0.30W ≥ 15W and < 50W 1.0W 0.75W 0.50W ≥ 50W and < 75W 1.0W 0.75W 0.75W At light and no load, the FAN7601 operates in burst mode to reduce the power loss. To meet the regulation specification the most important thing is to minimize the number of MOSFET switchings. The flyback converter transfers energy during the switch-off time. As the primary inductance of the flyback transformer increases, the energy transferred to the secondary side increases during one switching cycle. Therefore it is better to use a higher inductance transformer, but inductance is restricted by the size and cost of the transformer. In this design example, a 600uH transformer is selected and the ferrite core is EER2828. The transformer turns ratio is calculated when the input line voltage is lowest and the output power is maximum. The maximum duty ratio must be lower than 0.45 to prevent subharmonic oscillation. In this design example, the turns ratio must be higher than 0.174 by (7). 1 – D max Vo + V Diode n > ----------------------- ⋅ -------------------------------Vdc_min D max (7) Once the minimum turns ratio is determined, then the numbers of primary and secondary turns is calculated when input line voltage is highest and the output power is maximum. If the converter operates in the CCM (Continuous Conduction Mode) then the turn-on time can be calculated ©2003 Fairchild Semiconductor Corporation by (8). Vo + V Diode 1 t on = ------------------------------------------------------------------------ ⋅ --------n ⋅ Vdc_max + Vo + V Diode fsw (8) Then the number of primary turns can be obtained as in (9). Ae is the effective cross sectional area of the core and Bmax is the maximum flux density. Ae of EER2828 is 82.1mm2 and Bmax is 0.15T. The calculated number of primary turns is 54. Then the number of secondary turns can be calculated by (10). The calculated number of secondary turns is 10. The air gap length can be calculated by (11). Vdc_max ⋅ t on Np = --------------------------------------- Ae ⋅ Bmax (9) Vo + V Diode 1 – D max Ns = Np -------------------------------- ⋅ ----------------------Vdc_min D max (10) lg = 4π ⋅ 10 –7 2 N P ⋅ Ae ⋅ ---------L (11) If the primary inductance is not high enough, the converter can operate in the DCM(Discontinuous Conduction Mode) when the input line voltage is highest and the output power is maximum. For the DCM, the turn-on time can be calculated as in (12). 5 AN4129 t on APPLICATION NOTE 2 ⋅ L ⋅ Io ⋅ n = ---------------------------Vdc_max (12) Then the number of primary turns and secondary turns can be calculated by (9) and (10), respectively. An adequate IC supply voltage is 12V considering the minimum operating voltage and the over voltage protection level. In this design example, the number of Vcc windings is selected so as to be the same as that of the secondary windings, namely 10 turns. If the number of windings is too small, the supply voltage can touch minimum operating voltage at no load; then the UVLO circuit comes into operation, increasing the power loss. If the number of windings is too large, the supply voltage can reach the over voltage protection level. If it proves difficult to prevent over voltage protection operation in normal mode, the circuit as shown in Fig. 12 is recommended for the Vcc circuit. The maximum average current of the output diode is the same as the maximum load current. In this case, 4.167A is the maximum load current. For better efficiency, two 100V, 20A schottky diodes are used. The diode is reverse biased when MOSFET is turned on. The reverse voltage depends on the MOSFET switching characteristic. If the MOSFET switching is fast, the diode junction capacitance and transformer leakage inductance resonate. Then the diode reverse voltage can exceed the diode rating. Therefore the MOSFET gate drive on resistance must be high enough to limit diode reverse voltage. Figure 13 shows the output diode voltage and MOSFET gate voltage waveforms when input line voltage is 265V and output power is 50W. The gate drive on resistance is 75Ω. As shown in the figure, the diode reverse voltage exceeds the diode rating, 100V. To reduce the diode reverse voltage, gate drive resistance is changed to 150Ω. Figure 14 shows the output diode voltage and MOSFET gate voltage waveforms with a 150Ω resistor. The diode reverse voltage is lowered because of MOSFET's slow turn-on characteristic. Vcc 18V Figure 12. Zener Clamped Vcc Circuit Vdiode 3. MOSFET Current Sensing Resistor Selection Once the turns ratio of the transformer is determined, peak MOSFET current can be calculated. The sensed current information must be lower than 1V. If the resistance is too high, the output power can not be delivered because the MOSFET current is limited to the lower value. The resistance can be determined as in (13). In this design example, a 0.5Ω resistor has been selected. 1 Rs < --------------------------------------------------------------------------------------D max Ns Io -------- ⋅ ----------------------- + Vdc_min ------------------------- ⋅ -------------fsw Np 1 – D max 2⋅L Vgate Figure 13. Diode Reverse Voltage and MOSFET Gate Voltage With 75Ω (13) 4. Output Capacitor Design The value of the output capacitor depends on the output voltage ripple and noise specification. In this design example two 1000uF capacitors are used. 5. MOSFET and Diode Selection Vdiode Vgate The current of MOSFET is highest when the input line voltage is lowest and the output power is at maximum. The MOSFET RMS current can be approximated as in (14). The calculated value is 0.94A. A 600V, 2.7A(Tc=100°C) MOSFET FQPF7N60 has been selected. n ⋅ Io I MOSFET ( RMS ) ≈ ----------------------- D max 1 – D max 6 (14) Figure 14. Diode Reverse Voltage and MOSFET Gate Voltage With 150Ω ©2003 Fairchild Semiconductor Corporation APPLICATION NOTE AN4129 6. Output Voltage Sensing Resistor and Feedback Loop Design The output voltage sensing circuits cause power loss if the impedance is too low. The values of the output voltage sensing resistors are selected so that that power loss is under 10mW. The designed values are 27kΩ for the upper resistor and 7kΩ for the bottom resistor. To control output voltage, a KA431 and an optocoupler are used as shown in Fig. 15. Equation (15) is the compensator transfer function. In this equation, k is the current transfer ratio of the optocoupler and this value is nonlinear. current peak of the blue line is higher than that of the red line, more energy is transferred to the secondary side. Therefore standby power is lower with the higher resistance. But if the resistance is too high, the system can become unstable. The selected values are 10pF for Cf and 1kΩ for Rf . High resistance Low resistance 1V Filtered informations CS/FB Figure 16. Current Sense Waveforms Rf V fb 1 1 -------- = k ⋅ -------- ⋅ --------------------------------- ⋅ 1 + ---------------------------- R3 R f ⋅ C f ⋅ s + 1 VO R1 ⋅ C1 ⋅ s (15 For the stability of the system, capacitor C1 must be high enough. C1 can be selected as in (16). The selected value is 1nF. 1 10 C1 > --------- ⋅ ------------------fsw 2π ⋅ R1 Vo R3 Vcc C1 R1 (16) R3 determines the control loop gain. If the value is too low, the system can become unstable. And if the value is too high, the output voltage regulation characteristics may be poor. The selected value is 1.5kΩ. If the value of Rfb is too high then the output voltage is not regulated at no load because the offset voltage of the CS/FB pin is lower than necessary. If the value is too low the audible noise increases. Because the current transfer ratio of the photocoupler is nonlinear, the value of Rfb has to be selected by experiment at no load. The selected value is 3.9kΩ. 7. Transformer Audible Noise Rfb CS/FB Cf Rf R2 RS Figure 15. Output Voltage Compensation Circuit The FAN7601 does not contain an LEB(Leading Edge Blanking) circuit, but the parasitic capacitance and resistance of the internal circuit work as an RC filter which filters switching noise. The parasitic capacitance is about 10pF and the parasitic resistance is about 20kΩ. These values are sufficient to filter switching noise; therefore a small capacitor can be used for Cf . The value of Rf should be 1000~2000 times higher than that of Rs. The filter resistor Rf causes some sensing delay so that the peak value of the filtered information is less than that of the real current information. The higher resistance causes a greater difference as shown in Fig. 16. The black line is the CS/FB voltage and the red and blue lines are the real current waveforms before filtering . The red line is the current waveform when the resistance is low and the blue line is the current waveform when the resistance is high. Because the ©2003 Fairchild Semiconductor Corporation Because the FAN7601 operates in burst mode at light load and no load, it has a switching period and a non-switching period. Figure 17 shows the gate and output voltage at no load. Burst operation frequency is about 114Hz. The burst operation frequency varies according to load condition and the frequency is in the range of the audible frequency. Therefore the transformer may generate audible noise. The audible noise level depends on the control loop characteristic. If the loop speed is fast, audible noise increases but power loss decreases. If the loop speed is slow, audible noise decreases but power loss increases. There has to be a compromise between power loss and audible noise. Varnishing the transformer helps in reducing audible noise. 7 AN4129 APPLICATION NOTE greater than 0.5 for CCM, the slope compensation is necessary. Figure 18 shows the slope compensation circuit. Vout Vref Rt Rt/Ct Ct Vgate 2k CS/FB Rf Figure 17. Burst Mode Operation Waveforms 8. How to Reduce Standby Power 1) Make the transformer inductance sufficiently high . 2) Make the control loop speed fast. 3) Use a higher resistor for Rf. But too high resistance makes the system unstable. 9. Slope Compensation Cf Figure 18. Slope Compensation Circuit Figure 19 shows the designed application circuit diagram, table 2 shows the test results and table 3 shows the 50W adapter demo board components list. As can be seen in the table, the input power is less than 0.3W in the whole input voltage range at no load. The power was measured with a power meter from Voltech, PM3000. To prevent subharmonic oscillation when the duty ratio is 10. On/Off Control The Latch/SS pin can be used for the On/Off control with an NPN transistor. Figure 19 shows the On/Off control circuit. Latch/SS On/Off Control Signal Figure 19. On/Off Control Circuit 8 ©2003 Fairchild Semiconductor Corporation APPLICATION NOTE AN4129 Table 2: Experimental Results Input Power Output Power 85Vac 110Vac 220Vac 240Vac 265Vac No Load 0.129W 0.136W 0.220W 0.245W 0.252W 0.5W 0.687W 0.703W 0.783W 0.796W 0.878W 50W 59.2W 58W 57.8W 57.6W 57.8W ©2003 Fairchild Semiconductor Corporation 9 AN4129 APPLICATION NOTE R206 C204 D202 1 C103 D201 R103 C108 BD101 T1 12 L201 C202 C201 D101 9 Q101 3 6 D102 R108 C222 C107 R107 C110 C111 5 R201 1 2 R101 RT101 C101 F101 C105 C109 R109 C106 Vstr Vref CS/FB 3 Latch /SS 4 Rt/Ct FAN7601 LF101 C102 Vcc OUT GND 8 4 C112 IC301 3 R202 R204 1 C203 2 7 R105 6 5 R110 IC201 R205 D103 IC101 AC INPUT R112 4 3 R111 R113 IC302 TR101 R114 Thermal Protection R106 1 R207 2 ZD201 Over Voltage Protection Figure 20. Application Circuit Diagram 10 ©2003 Fairchild Semiconductor Corporation APPLICATION NOTE AN4129 Table 3: 50W Adapter Demo Board Part List PART# VALUE NOTE PART# FUSE F101 250V 1A VALUE NOTE CAPACITOR - NTC C101 220nF/275V Box Cap. C102 100nF/275V Box Cap. RT101 5D-9 - C103 150uF/400V Electrolytic R111 8k - C105 10pF Ceramic C106 272 Miler RESISTOR R101 - - C107 47uF/25V Electrolytic R103 56k 1/2W C108 103 Film R105 150 - C109 0.47uF Electrolytic R106 10k - C110, 111 102/1kV Ceramic R107 0.5 1/2W C112 104 Ceramic R108 1k - C201, 202 1000uF/25V Electrolytic R109 8k - C203 102 Ceramic R110 3.9k - C222 222/1kV Ceramic R112 1k - R113 36k - R114 1M - R201 1.5k - LF101 23mH - R202 1.2k - L201 9uH - R203 0 - R204 27k - D101,102 UF4007 - R205 7k - D103 1N4148 - R206 10 1/2W D202, 204 MBRF20100CT - R207 10k - ZD201 15V Zener/1W - BD101 KBP206 - IC IC101 FAN7601 Fairchild IC201 KA431 Fairchild IC301, 302 H11A817B Fairchild ©2003 Fairchild Semiconductor Corporation MOSFET Q101 FQPF7N60 Fairchild INDUCTOR DIODE TRANSISTOR TR101 2N3906 Fairchild 11 AN4129 APPLICATION NOTE 4. Transformer Specification 1 12 3mm 3mm Ns 9 Np 2 NVcc Np 3 Ns 5 Np NVcc 6 Winding Specification Pin (S → F) Wire Turns Winding Method NP 1→2 0.35φ × 2 27 NS 9 → 12 0.65φ × 3 10 NP 2→3 0.35φ × 2 27 NVCC 5→6 0.2φ × 1 10 Pin Value Remarks Inductance 1-3 600uH 100kHz, 1V Leakage 1-3 15uH 2nd shorted Electrical Specification Core EER2828 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPROATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/22/03 0.0m 002 Stock#ANxxxxxxxxx 2003 Fairchild Semiconductor Corporation