MICRONAS AMU2481

MICRONAS
INTERMETALL
AMU 2481
Audio Mixer
MICRONAS
Edition August 3, 1992
6251-324-3E
AMU 2481
Contents
Page
Section
Title
3
3
1.
1.1.
Introduction
Application of the AMU 2481
5
5
5
6
6
6
6
6
7
8
9
9
9
9
9
2.
2.1.
2.1.1.
2.1.2.
2.1.2.1.
2.1.2.2.
2.1.3.
2.1.3.1.
2.1.3.2.
2.1.4.
2.2.
2.2.1.
2.2.2.
2.2.3.
2.3.
Architecture of the AMU 2481 and Functional Description
I/O Blocks
Digital Decimation Filters
S Bus Interface and S Bus
Description of the S Bus
The S Bus Interface
IM Bus Interface and IM Bus
Description of the IM Bus
The IM Bus Interface
Digital/Analog Converter (DAC) and Volume 2
DSP Block
C–RAM, C–ROM and Data RAM
Program ROM, Program Counter and Control Block
Arithmetic Logic Unit (ALU)
System Clock ΦM and PDM Sampling Rate
10
10
10
10
11
11
11
12
12
12
13
13
13
14
3.
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
3.9.
3.10.
3.11.
3.12.
3.13.
Functions Solved by DSP Software
Representation of Numbers
DC Offset Suppression (for PDM–Data only)
50 µs Digital Deemphasis (for PDM–Data only)
J17 Deemphasis (for S–Data only)
Medium Quality Oversampling Filter
Audio Mixing Section
Sin x/x Compensation
Volume Control
Matrix 2
50 µs Digital Preemphasis
Oversampling Filter for Ch1 and Ch2
AMU 2481 Initialization
Complete Coefficient Table
16
16
16
16
17
17
18
19
19
19
21
4.
4.1.
4.2.
4.2.1.
4.2.2.
4.3.
4.4.
4.5.
4.5.1.
4.5.2.
4.5.3.
Specifications
Outline Dimensions
Pin Connections
24–Pin DIL Package
44–Pin PLCC Package
Pin Descriptions
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
22
5.
Appendix 1: Application Circuit
23
6.
Appendix 2: Program Structure
2
MICRONAS INTERMETALL
AMU 2481
Audio Mixer
1.1. Application of the AMU 2481
Note:
If not otherwise designated the pin numbers mentioned refer to the 24–pin DIL package.
The AMU 2481 Audio Mixer is designed to interface with
INTERMETALL’s ADC 2311 E Audio A/D Converter,
DMA 2271 D2–MAC Decoder on the input side, and with
the APU 2471 or the ACP 2371 Audio Processors on the
output side. It can receive digital audio data in two different formats:
1. Introduction
The AMU 2481 Audio Mixer is a digital real–time signal
processor in NMOS technology, housed in a 24–pin Dil
plastic package or in a 44–pin PLCC package. It is designed to perform digital processing of both TV audio information and digital audio data supplied by the
DMA 2271 D2–MAC Decoder. The architecture of the
AMU 2481 combines two main blocks:
Via the PDM inputs, the AMU 2481 is supplied with two
1–bit PDM data streams produced by the ADC 2311 E
Audio A/D Converter which receives analog audio information either from the SCART interface (Euro connector), which is used, e.g., for video recorder connection,
or from any terrestrial TV transmission. For this input format, decimation filters are provided in the AMU 2481,
which convert each PDM stream into a 16–bit word at
a sampling rate of approximately 32 kHz.
– I/O blocks
– DSP block
Via the S bus interface the AMU 2481 receives serial
audio data, provided, e.g., by the DMA 2271 D2–MAC
Decoder.
The I/O blocks are used to manage the input and output
of audio information. The DSP block consists of a mask–
programmable digital signal processor, whose software
can be controlled by a microprocessor (CCU) via the IM
bus. So parameters like coefficients can be modified
during performance. By means of the DSP software, audio functions, such as deemphasis, oversampling mixing and volume control are performed. Fig. 1–1 gives an
overview over the AMU’s functions.
Fig. 1–2 shows how the AMU 2481 can be used together with the mentioned ICs of INTERMETALL to realize
multistandard audio processing with PAL and D2–MAC
signals. In the following descriptions data coming from
the ADC will be called “PDM data” and data coming from
the DMA will be called “S data”.
AMU 2481
Deemphasis
J17
S Bus
S–C I/O
8
Deemphasis
J17
S
B
u
s
S–DIN
9
Deemphasis
J17
Oversampling
Channel 3
S–I I/O
15
Deemphasis
J17
PDM 1
17
M
i
x
e
r
Oversampling
Channel 4
Deemphasis
50 µs
Channel 1
S
H
A
L
Channel 2
S
H
A
L
Channel 3
S
H
A
L
Channel 4
S
H
A
L
sin x
x
dig.
Vol.
DAC 1
Vol 2
sin x
x
M
a
t
r
i
x
sin x
x
dig.
Vol.
DAC 2
sin x
x
–3 dB
Channel 1
22
–3 dB
Channel 2
23
–3 dB
Channel 3
19
–3 dB
Channel 4
20
CF
PDM 2
16
Deemphasis
50 µs
Preemphasis
par.
Preemphasis
S Bus
6
Preemphasis
IM Bus Interface
D
A
VSUP VISB RESET
ΦM
IREF2 IREF1
Preemphasis
D
12
24
3
ID
4
ser.
CL
5
14
10
11
13
1
21
Fig. 1–1: Functional block diagram of the AMU 2481
MICRONAS INTERMETALL
3
AMU 2481
18.432 MHz
18.432 MHz
ΦM
DOUT
AUXDIN
Analog
Sound IF
DMA
2271
S Bus
AMU
2481
DAC1
AUXIN
ACP
2371
S Bus
DAC2
TVIN
AUXOUT
PILOTIN
IM Bus
CCU
Fig. 1–2: Multistandard audio system with AMU 2481
IM Bus
ID CL D
AMU 2481
DAC 1 +
VOL 2
IM Bus
Interface
16
16
Separator
DAC 2
CH1
CH2
Iref1
Iref2
CH3
CH4
16
5 Address
Address
M
U
X
6
Coeff.
Memory
RAM
32 x 8
Data RAM
50 x 16
ALU
MUL
16 x 8
ADD/SUB
20
ACCU
20
8
ROM
28 x 8
16
S RAM
4 x 16
S Bus
Interface
PDM RAM
2 x 16
SDATA
SCLOCK
SIDENT
SDATA
S Bus
Ident
1 x 16
Address
6
PC
Program
ROM
256 x 14
14
Digital
Decimation
Filters
Control
Main Clock
Reset
PDM1 PDM2
Fig. 1–3: AMU 2481 architecture
4
MICRONAS INTERMETALL
AMU 2481
2. Architecture of the AMU 2481 and Functional Description
As already mentioned in section 1., the AMU 2481 architecture combines two main parts, the I/O blocks and the
DSP core. Fig. 1–3 shows a block diagram of the architecture.
2.1. I/O Blocks
2.1.1. Digital Decimation Filters
The digital decimation filters are cascades of transversal
and recursive lowpass filters. They are required to con-
vert the two 1–bit PDM data streams by stepwise reduction of bandwidth and word rate (sampling rate) into two
PCM data streams with 16 bit word length and a sampling rate of approximately 32 kHz, which in the following
are called PCM data 1 and 2. They are temporarily
stored in the corresponding locations of the AMU’s data
RAM.
As the two PDM data streams at the input of the decimation filters have no separate clock signal, the decimation
filters are equipped with a synchronization facility. This
feature also supplies the AMU software with the sampling clock (approx. 32 kHz), which is called ”I/O Sync”
or IOSYNC. More details on data/clock timing can be
found in section 2.3.
H
S–Ident
L
H
S–Clock
64 Clock Cycles
L
H
S–Data
16 Bit Sound 1
L
16 Bit Sound 2
16 Bit Sound 3
16 Bit Sound 4
A
B
Section A
Section B
tS6
H
S–Ident
L
tS1
tS2
tS3
H
S–Clock
L
tS4
tS5
H
LSB of Sound 1
S–Data
MSB of Sound 4
L
Fig. 2–1: S bus waveforms
MICRONAS INTERMETALL
5
AMU 2481
2.1.2. S–Bus Interface and S–Bus
2.1.2.1. Description of the S–Bus
The S–bus was designed to connect the digital sound
output of the DMA 2271 D2/MAC Decoder to audio–
processing ICs such as the AMU 2481 Audio Mixer or
the APU 2471 Audio Processor etc., and to connect
these ICs with each other. The S–bus is an unidirectional, digital bus which transmits the sound information
in one direction only, so that it is not necessary to solve
priority problems on the bus.
The S–bus consists of the three lines S–Clock, S–Ident
and S–Data. The DMA 2271 generates the signals S–
Clock and S–Ident, which control the data transfer to and
between the various processors which follow the DMA
2271. For this, the S–Clock and S–Ident inputs of all
processors in the system are connected to the S–Clock
and S–Ident outputs of the DMA 2271. S–data output of
the DMA 2271 is connected to the S–Data input of the
next following AMU, the AMU’s S–Data output is connected to the APU’s S–Data input and so on.
The sound information is transmitted in frames of 64 bits,
divided into four successive 16–bit samples. Each sample represents one sound channel. The timing of a complete transmission of four samples is shown in Fig. 2–1,
the times are specified in “Recommended Operating
Conditions”. The transmission starts with the LSB of the
first sample. The S–Clock signal is used to write the data
into the receiver’s input register. The S–Ident signal
marks the end of one frame of 64 bits and is used as
latch pulse for the input register. The repetition rate of
the S–Ident pulses is identical to the sampling rate of the
D2–MAC sound signal; thus it is possible to transfer four
sound channels simultaneously.
2.1.2.2. The S–Bus Interface
The S–bus interface of the AMU 2481 mainly consists of
an input and an output register, each 64–bit wide. The
timing to write or read bit by bit is supplied by the S–
Clock signal. In the case of an S–Ident pulse, the contents of the input register are transferred to the data
RAM (see section 2.2.1.) and the contents of the output
register are written to the S–Data output.
The S–Ident is also used as the sampling rate reference
for the DSP software in the case of digital source mode.
In this mode the IOSYNC generated by the decimation
filters is locked to the S–Ident. This allows a mixed
mode: S–Data and PDM Data can be processed simultaneously. In this case, however, there must be the same
audio sample rate of PDM data and S–bus data (see
2.3.). If this is not the case, the S–Ident line has to be disabled.
By means of coefficient k33 (see section 3.13.) the AMU
2481 can be switched to an S–bus slave mode (bit 4 = 0)
6
or to an S–bus master mode (bit 4 = 1). The slave mode
is required in an application as shown in Fig. 1–2 where
the DMA 2271 D2–MAC Decoder acts as master on the
S–bus, i.e. the DMA 2271 supplies the S–Clock and S–
Ident signals as well as the S–Data input signal.
To enable parallel cascading of AMUs without external
switches, (e.g. NICAM to SCART and D2MAC to TV) in
the 44–PLCC package, the SBUS signals S–Ident and
S–Clock, (and the Main Clock, see section 2.3.) can be
passed through the AMU 2481. The corresponding
open–drain outputs can be switched to high impedance,
which is the default status after power–on reset. To
switch them on or off (high imp.), use the same bit that
controls the SBUS data output:
k33 bit3 = 0 outputs = active
= 1 outputs = high impedance
2.1.3. IM Bus Interface and IM Bus
2.1.3.1. Description of the IM Bus
The INTERMETALL Bus (IM Bus for short) was designed to control the DIGIT 2000 ICs by the CCU Central
Control Unit. Via this bus the CCU can write data to the
ICs or read data from them. This means the CCU acts
as a master whereas all controlled ICs are slaves.The IM
bus consists of three lines for the signals Ident (ID),
Clock (CL) and Data (D). The clock frequency range is
50 Hz to 170 kHz. Ident and clock are unidirectional from
the CCU to the slave ICs, Data is bidirectional. Bidirectionality is achieved by using open–drain outputs with
On–resistances of 150 Ohm maximum. The 2.5 kOhm
pull–up resistor common to all outputs is incorporated in
the CCU.The timing of a complete IM bus transaction is
shown in Fig. 2–2 and in the “Recommended Operating
Conditions”. In the non–operative state the signals of all
three bus lines are High. To start a transaction the CCU
sets the ID signal to Low level, indicating an address
transmission, then sets the CL signal to Low level and
switches the first bit on the Data line.Then eight address
bits are transmitted, beginning with the LSB. Data takeover in the slave ICs occurs at the positive edge of the
clock signal. At the end of the address byte the ID signal
goes High, initiating the address comparison in the slave
circuits. In the addressed slave the IM bus interface
switches over to Data read or write, because these functions are correlated to the address.
Also controlled by the address the CCU now transmits
eight or sixteen clock pulses, and accordingly one or two
Bytes of data are written into the addressed IC or read
out from it, beginning with the LSB. The completion of
the bus transaction is signalled by a short Low state
pulse of the ID signal. This initiates the storing of the
transferred data.
It is permissible to interrupt a bus transaction for up to 10
ms.
MICRONAS INTERMETALL
AMU 2481
an 8–bit address to the IM bus interface of the AMU
2481, addressing a certain register or C–RAM location
of the AMU. The IM bus interface has to check this address and if necessary, to store it and the following 8 data
bits into special IM bus interface registers. Transfer of
the data bits to the corresponding C–RAM locations is
then performed by the AMU hardware at the sampling
rate. Transmission of one Byte (8 bits) takes 100 µs. A
spacing of 30 µs must be provided between the end of
one transmission and the start of the next one.
For future software compatibility, the CCU must write a
zero into all bits not used at present. When reading undefined or unused bits, the CCU must adopt “don’t care”
behavior.
2.1.3.2. IM Bus Interface
To write coefficient value(s) into the AMU2481 registers
the following steps have to be taken:
1. addressing the AMU2481 (allows multiprocessor system)
In the case of addressing the AMU 2481 (step 1 above),
the address transmitted first is 102 (= select register). If
the following 8–bit data is identical to 15, the AMU 2481
will accept further IM bus data. This kind of selective addressing allows controlling of different AMU and APU
types (e.g. “selectword” of APU 2471 = 00, “selectword
of AMU 2481 VS = 14) in a multi–APU system without
using different address ranges. Each APU/AMU type will
have its own mask–programmed “selectword”.
2. writing of 8 bit data into the IM bus interface registers
After having completed step 1, step 2 can be performed
as often as the communication between AMU 2481 and
CCU is required, on the condition that the processor address has not been changed by the CCU.
Comments to the steps mentioned above: The syntax of
step 1 is identical to that of step 2. The CCU transmits
H
Ident
L
H
Clock
1
2
3
4
5
6
7
8
9
10
11
12
13
16
or 24
L
H
Data
Address
LSB
MSB LSB
Data
MSB
L
A
B
Section A
C
Section B
Section C
tIM10
H
Ident
L
tIM1
tIM3
tIM4
tIM6
tIM5
tIM2
H
Clock
L
tIM7
tIM8
tIM9
H
Address LSB
Data
Address MSB
Data MSB
L
Fig. 2–2: IM bus waveforms
MICRONAS INTERMETALL
7
AMU 2481
2.1.4. Digital/Analog Converter (DAC) and Volume 2
+12 V
I REF1
Digital to analog conversion is performed by four special
conversion circuits. The channels 1 and 2 are assigned
to DAC 1, channels 3 and 4 to DAC 2. At any time, the
current level of the output signals depends on the value
of the reference currents, which are fed to pin 21 (for
DAC 1) and to pin 1 (for DAC 2). Fig. 2–3 gives application diagrams for the DAC circuits. The RC network connected to the outputs is required for suppressing the
clock from the D/A conversion (1 nF). To achieve an analog deemphasis of 50 µs, the 1 nF capacitors must be
enlarged to the 10 nF. To improve the signal–to–noise
ratio of the AMU 2481 (especially for low volume settings) an additional volume control facility (Vol 2) is provided after the DAC 1 D/A converters. A digitally–adjusted attenuator acts in 29 steps of 1 dB each.
R
C
4.7 k
10 µ
21
AMU 2481
Ch1
22
DAC 1
Vol. 2
RI > 100 k
23
Ch2
1 n*
a)
Note:
There is an application restriction with these converters:
The clock rate of the AMU must meet the following clock
condition:
+12 V
I REF2
R
C
Clock rate = sampling rate n 16
n must be an integer value. In section 2.3. all clocks relevant for the AMU application are listed. They fulfill that
condition.
68 k
+
68 k
+
10 µ
4.7 k
1
AMU 2481
Ch3
19
DAC 2
RI > 100 k
20
Ch4
b)
1 n*
Fig. 2–3: DAC application diagrams
a) DAC 1 Interface
b) DAC 2 Interface
*) optionally 10 nF for 50 µs analog deemphasis
8
MICRONAS INTERMETALL
AMU 2481
2.2. DSP Block
2.2.3. Arithmetic Logic Unit (ALU)
The AMU 2481 contains a complete mask–programmable digital signal processor with the blocks as described
in the following sections.
The core of the DSP block is the ALU. Multiplication of
16 8 bit, addition using a 20–bit accumulator, and shift
operations are performed in the ALU. Accumulation is
done according to a saturation characteristic (see section 3.1.).
2.2.1. C–RAM, C–ROM and Data RAM
2.3. System Clock ΦM and PDM Sampling Rate
Coefficients and control parameters for digital processing of audio data are either fixed or variable by means
of the CCU. The coefficient (C) memory is therefore divided into two parts:
The clock at the AMU’s ΦM input is dependent on the
current TV standard. The AMU is mainly provided for the
German TV stereo system PAL and digital source standard (e.g. D2–MAC). In all cases, the physical source of
the AMU’s system clock is the DMA 2271 D2–MAC Decoder (Fig.1–2):
C–RAM, containing 32 locations of 8 bits each, which
can be loaded by the CCU via the IM bus interface. The
AMU software needs 32 variable parameters, and for
proper processing all locations must be loaded with the
corresponding values.
C–ROM, containing 28 locations of 8 bits each, which
are loaded with fixed values, required for the DSP software. For the user there is no possibility to change coefficients in the C–ROM. Input data and intermediate results can be stored in the AMU’s Data RAM whose
locations have 16 bits each. This RAM is arranged in the
following way:
– 50 locations for intermediate results and output data
– 4 locations for S bus input channels
– 2 locations for 2 PDM channels from the decimation filters
2.2.2. Program ROM, Program Counter and Control
Block
The DSP software of the AMU 2481 is stored in the program ROM. Its size is 256 14 bits, and its content cannot be modified by the user because it is mask–programmed. Program ROM is addressed by the program
counter (P.C.), which is a preset table counter.
Instruction decoding and coordinating of all time functions is performed by the control block. Multiplexing of
the two busses, addressing the coefficient memory and
controlling the separator are also tasks of the control
block. By means of the separator, data are transferred
to the DACs.
Table 2–1: Selection of operation mode by k33
Mode
k 33, Bit 6
PAL
D2–MAC
0
1
1. For PAL mode, the system clock ΦM is derived from
the color carrier frequency, for example in the MCU 2600
Clock Generator IC, and transferred to the DMA 2271 to
be passed on to the AMU. In the ADC, as well as in the
AMU, the ΦM clock is divided by four to produce the
PDM rate, and by 128 to generate the sampling rate.
2. For digital source (S bus) operation, the AMU system clock ΦM is generated in the DMA 2271 in such a
way that it is a multiple of the D2–MAC typical audio
sampling frequency. The S bus signals S–Clock and S–
Ident are then derived from this clock.
Table 2–2 gives details about the clock requirements of
the above operation modes. Selection of the operation
mode (clock dividers) has to be transmitted by the CCU
by means of coefficient k33, Bit 6 (see table 2–1, also
section 3.13.).
To enable parallel cascading of AMUs without external
switches, (e.g. NICAM to SCART and D2MAC to TV) in
the 44–PLCC package, the main clock (the S–Clock and
the S–Ident, see section 2.1.2.2.) can be passed
through the AMU 2481. The push–pull output can be
switched to high impedance, which is the default status
after power–on reset. To switch it on or off, use the same
bit that controls the SBUS output:
k33 bit3 = 0 outputs = active
= 1 outputs = high impedance
Table 2–2: AMU system clock ΦM and derived sampling rates
TV Standard
AMU ΦM
PDM Rate
Sampling Rate
PAL
D2–MAC
17.73 MHz
18.432 MHz
:4 = 4.43 MHz
–
:128 = 34.63 kHz
:576 = 32 kHz
MICRONAS INTERMETALL
9
AMU 2481
3. Functions Solved by DSP Software
3.3. 50 µs Digital Deemphasis (for PDM–Data Only).
3.1. Representation of Numbers
A digital deemphasis is applied to the PDM inputs in order to process preemphasized audio signals (e.g. FM
TV). So it is not necessary to realize the 50 µs deemphasis by analog networks at the AMU’s outputs as
shown in Fig. 2–3 (or at the APU’s output with complete
systems, as shown in Fig. 1–2). In the case of processing SCART signals or if an analog deemphasis at the
DAC outputs is preferred, the digital deemphasis can be
switched off (linear frequency response). Fig. 3–1
shows the 50 µs deemphasis frequency response. The
control procedure is:
The AMU 2481 has a two’s complement, fixed point
arithmetic with decimal point being left-hand and the
MSB being the sign bit. The word lengths are defined as
follows:
coefficients:
8 bits including sign bit
data at multiplier input:
16 bits including sign bit
intermediate results:
20 bits including sign bit
Table 3–1 shows as an example the range of the 8–bit
coefficients, resulting from the conditions mentioned
above. From the view of the CCU programmer this might
be the most interesting case. Three formats are used to
express the coefficient values: Integer decimal, integer
hexadecimal and normalized.
50 µs deemphasis on:
Coefficient values must be transferred from the CCU to
the AMU via the IM bus in binary format; therefore in
most tables of this data sheet the values will be presented in HEX and additionally in the normalized format,
to make the digital signal processing background more
understandable. To save space the normalized values
will be rounded.
50 µs deemphasis off:
3.2. DC Offset Suppression (only for PDM–Data)
To avoid audible distortions caused by volume changes
the DC part of the signals coming from the decimation
filters has to be minimized. Therefore DC suppression
for both channels is performed by the following steps:
Φ Main Clock
18.432 MHz
17.732 MHz
KRDEEM (k26)
69 (0.5390)
73 (0.5703)
Φ Main Clock
18.432 MHz
17.732 MHz
KRDEEM (k26)
0 (0.0)
0 (0.0)
dB
5.0
0.0
–5.0
1. calculation of the DC levels in two separate measure
paths, i.e. down–sampling of both channels to about
1 kHz
–10.0
2. lowpass filtering
–15.0
3. subtracting the resulting DC signals from the original
channels ( = DC compensation)
–20.0
100.0
Note: The feature DC offset suppression is not controllable by the CCU, e.d. all coefficients are fixed and
stored in the AMU’s C–ROM.
1000.0
10000.0
Hz
Fig. 3–1: 50 µs digital deemphasis frequency response
Table 3–1: Range of an 8–bit coefficient value
Coefficient
AMU Internal Presentation
HEX
DEC
Normalized
Max. Value
Min. Positive Number
0111 1111
0000 0001
7F
01
127
001
0.9921875
0.0078125
Max. Negative Number
Min. Number
1111 1111
1000 0000
FF
80
255
128
–0.0078125
–1.0
Note: Coefficients kij have to be determined such that
any overflow in the AMU arithmetic is excluded. Nevertheless, if overflow occurs, the ALU will deal it according
10
to a saturation characteristic. Considering this restriction, for good S/N ratio the digital range must be optimally used.
MICRONAS INTERMETALL
AMU 2481
one filter is switched on channel 3:
KOVERS (k30) = 0 (0.0)
3.4. J17 Digital Deemphasis (Only for S–Data)
A J17 digital deemphasis is included in all S bus channels. This is important in the case of D2–MAC mode. For
test purposes or for future digital sources without J17
preemphasis this function can be switched off (linear frequency response). Fig. 3–2 shows the frequency response. The control procedure is:
dB
10
0
–10
–20
J17 deemphasis on:
–30
Φ Main Clock
18.432 MHz
17.732 MHz
–40
KRJ17 (k28)
116 (0.90625)
117 (0.9140625)
–50
KNJ17 (k29)
11 (0.0859375)
10 (0.078125)
–60
0
J17 deemphasis off:
2.5
5
7.5
10
12.5
15 kHz
Fig. 3–3: Oversampling filter frequency response
Φ Main Clock
18.432 MHz
17.732 MHz
KRJ17 (k28)
0 (0.0)
0 (0.0)
KNJ17 (k29)
118 (0.921875)
118 (0.921875)
3.6. Audio Mixing Section
dB
5.0
This basic feature allows to route any input to every output and of course to mix different–weighted input channels. Due to the three shift–left (SHAL) at the matrix output a coefficient of 16 (= 0.125) corresponds to a 1:1 ratio
of input to output. Table 3–2 shows the coefficients and
their meaning.
Table 3–2: Output matrix coefficients
0.0
–5.0
–10.0
Output
Channel
Coefficient
Connection
to Source
Ch1:
KS1L1 (k02)
KS2L1 (k03)
KS3L1 (k04)
KS4L1 (k05)
KP1L1 (k06)
KP2L1 (k07)
S bus channel 1
S bus channel 2
S bus channel 3
S bus channel 4
PDM 1
PDM 2
Ch2:
KS1R1 (k08)
KS2R1 (k09)
KS3R1 (k10)
KS4R1 (k11)
KP1R1 (k12)
KP2R1 (k13)
S bus channel 1
S bus channel 2
S bus channel 3
S bus channel 4
PDM 1
PDM 2
Ch3:
KS1L2 (k14)
KS2L2 (k15)
KS3L2 (k16)
KS4L2 (k17)
KP1L2 (k18)
KP2L2 (k19)
S bus channel 1
S bus channel 2
S bus channel 3
S bus channel 4
PDM 1
PDM 2
Ch4:
KS1R2 (k20)
KS2R2 (k21)
KS3R2 (k22)
KS4R2 (k23)
KP1R2 (k24)
KP2R2 (k25)
S bus channel 1
S bus channel 2
S bus channel 3
S bus channel 4
PDM 1
PDM 2
–15.0
–20.0
100.0
1000.0
10000.0
Hz
Fig. 3–2: J17 deemphasis frequency response
3.5. Medium Quality Oversampling Filter
Two oversampling filters in the S bus channels 3 and 4
allow to mix the D2–MAC medium–quality signals (16
kHz sampling rate) with the high–quality signals (32 kHz
sampling rate). It is a third–order Cauer–type lowpass
with a stopband attenuation of 40 dB. The frequency response is shown in Fig. 3–3. There are three selection
modes regarding the oversampling filters:
both filters switched on:
KOVERS (k30) = 129 (–0.992 1875)
both filters switched off:
KOVERS (k30) = 127 (0.992 187 5)
MICRONAS INTERMETALL
11
AMU 2481
3.7. Sin x/x Compensation
The sin x/x compensation results in an improved frequency response. It is a precompensation of the 4 dB
loss at half the sampling rate, that happens due to the
D/A conversion. Fig.3–4 shows the frequency response
of the sin x/x compensation. This function is always active, and no controller activity is required.
dB
4.0
2.0
trolled by a digitally–adjusted attenuator, which is controlled by k34 in steps of 1 dB each, and the total number
of steps is 29.
range: k34 = 0 to 29 (0.0 to 0.265 625)
The adjustment procedure for the channels 3 and 4
(DAC 2) is performed by means of coefficient k1 and results in a dynamic range of 42 dB, too. There is no analog
Vol 2 adjustment for the channels 3 and 4 (DAC 2) outputs.
range: KVOL34 (k1) = 0 to 127 (0.0 to 0.992 187 5)
mute condition: KVOL34 (k1) = 0
(0.0)
0.0
3.9. Matrix
–2.0
–4.0
–6.0
–8.0
–10.0
100.0
1000.0
10000.0
Hz
Fig. 3–4: Frequency response of the sin x/x
compensation
The matrix defines the configuration between the four input channels and the D/A converter section. This means
that channels 1 and 2 can be allocated to the DAC1 converters or to the DAC2 D/A converters and the same for
channels 3 and 4. The matrix allows no mixing. The matrix feature is important to have a freely programmable
selection of main speaker, headphones and SCART output. Control coefficient is k31:
KOUT (k31) = 127 (0.992 187 5) selects:
3.8. Volume Control
Matrix Input
The volume control facility works on the DAC 1 and
DAC 2 analog outputs only.
Channel 1
Channel 2
Channel 3
Channel 4
The adjustment procedure for the output channels 1 and
2 (DAC 1) is performed by means of coefficient k0 and
gives a dynamic range of 42 dB:
to
Matrix Output
Channel 1
Channel 2
Channel 3
Channel 4
KOUT (k31) = 128 (–1.0) selects:
range: KVOL12 (k0) = 0 to 127 (0.0 to 0.992 187 5)
Matrix Input
mute condition: KVOL12 (k0) = 0
(0.0)
In addition to this volume control, there is an additional
analog volume adjustment (Vol 2) after the DAC 1 (see
section 2.1.4.). The output channels 1 and 2 are con-
12
Channel 1
Channel 2
Channel 3
Channel 4
to
Matrix Output
Channel 3
Channel 4
Channel 1
Channel 2
MICRONAS INTERMETALL
AMU 2481
3.10. 50 µs Digital Preemphasis
fact that it is a software oversampling, the clock frequency must be fixed at 18.432 MHz.
The 50 µs digital preemphasis feature has been implemented to get compatibility to the former concept using
the analog deemphasis network connected to the DAC
outputs of the AMU or APU. In the case of D2–MAC operation mode, this analog deemphasis has to be
precompensated. In the combined system shown in Fig.
1–2, the 50 µs deemphasis is now realized in the ACP
2371 by digital means, so that the preemphasis is not
needed. For this case, it is possible to switch off the
preemphasis by means of coefficient k27:
dB
10
0
–10
–20
–30
–40
50 µs preemphasis on:
–50
–60
Φ Main Clock
18.432 MHz
17.732 MHz
KPRE (k27)
187 (–0.5390625)
183 (–0.5703125)
0
50 µs preemphasis off:
5000
10000
15000
20000
25000
30000 Hz
Fig. 3–6: Frequency response of the oversampling
filter
3.12. AMU 2481 Initialization
Φ Main Clock
18.432 MHz
17.732 MHz
KPRE (k27)
0 (0.0)
0 (0.0)
– After switching–on the power or after reset, the AMU
2481 requires a certain startup time (Fig. 3–7) to accept coefficients and valid audio data.
– Immediately after a reset the volume (k0 and k1) is
automatically set to zero.
dB
5.0
– After a delay of another 0.5 s (or 0.6 s after power–on)
a complete set of coefficients is transferred by the
CCU via the IM bus, keeping volume (k0, k1) to zero.
0.0
– 20 ms later the mute function is switched off by the
CCU.
–5.0
Power
On
–10.0
VSUP
–15.0
t
≥100 ms
–20.0
100.0
1000.0
10000.0
Reset
2V
Hz
AMU works for sure
k0, k1 = 0 autonomous
in Interface
>0.5 s
Fig. 3–5: 50 µs digital preemphasis frequency
response
3.11. Oversampling Filter for Ch1 and Ch2
Two oversampling filters in channels 1 and 2 are implemented. The oversampling factor is two. Fig.3–6
shows the frequency response of the filters. Due to the
MICRONAS INTERMETALL
Data
from
CCU
t
k 0 , k1 ≠ 0
from
CCU
Coeff. into
C RAM
k0, k1 = 0
Mute
≥ 20 ms
t
Fig. 3–7: Initialization of the AMU 2481
13
AMU 2481
3.13. Complete Coefficient Table
Table 3–3 details all coefficients and control words which
can be influenced by the CCU. Notes see page following
Table 3–3.
Table 3–3: Available addresses in the AMU’s C–RAM and their applications
Address
Coefficient
64
65
KVOL12
KVOL34
k00
k01
digital volume DAC1
digital volume DAC2
66
67
68
69
70
71
KS1L1
KS2L1
KS3L1
KS4L1
KP1L1
KP2L1
k02
k03
k04
k05
k06
k07
channel 1 source switch
channel 1 source switch
channel 1 source switch
channel 1 source switch
channel 1 source switch
channel 1 source switch
72
73
74
75
76
77
KS1R1
KS2R1
KS3R1
KS4R1
KP1R1
KP2R1
k08
k09
k10
k11
k12
k13
channel 2 source switch
channel 2 source switch
channel 2 source switch
channel 2 source switch
channel 2 source switch
channel 2 source switch
78
79
80
81
82
83
KS1L2
KS2L2
KS3L2
KS4L2
KP1L2
KP2L2
k14
k15
k16
k17
k18
k19
channel 3 source switch
channel 3 source switch
channel 3 source switch
channel 3 source switch
channel 3 source switch
channel 3 source switch
84
85
86
87
88
89
KS1R2
KS2R2
KS3R2
KS4R2
KP1R2
KP2R2
k20
k21
k22
k23
k24
k25
channel 4 source switch
channel 4 source switch
channel 4 source switch
channel 4 source switch
channel 4 source switch
channel 4 source switch
90
91
92
93
KRDEEM
KPRE
KRJ17
KNJ17
k26
k27
k28
k29
deemphasis for PDM input
preemphasis for S bus output
deemphasis for S bus input
deemphasis for S bus input
94
KOVERS
k30
oversampling switch
95
KOUT
k31
output changing switch
96
97
k32
k33
ADC coefficient (see ADC data sheet)
control word for standard selection
98
k34
VOL2; analog volume control
102
14
Select Reg.
Description
processor selection
MICRONAS INTERMETALL
AMU 2481
Notes to Table 3–3:
Cascading of two or more AMUs for future applications
need additional control information concerning the S
bus. This is done by means of k33 and to ensure upward
compatibility all bits are defined as follows:
k33: Bit 7
= 0* clock divider = 4 (section 2.3.)
= 1 clock divider = 3 (section 2.3.)
Bit 6
= 0* sampling rate is derived from
system clock (section 2.3.)
= 1 sampling clock according to
digital source (section 2.3.)
Bit 5
= 0* normal mode
= 1 test mode
concerning the S bus the AMU 2481 is:
Bit 4
= 0* slave
= 1 master
Bit 3
= 0
S bus data output active
(section 2.3.)
= 1* S bus data output = high
impedance (section 2.3.)
Bit 2
= 0* Pal mode
= 1 D2MAC/NICAM mode
Bit 1
= 0* normal S bus operation
= 1 S bus access to conversion filter
for MSP FM mode
Bit 0
= 0
not used, for compatibility must
be set to 0.
*) reset status
MICRONAS INTERMETALL
15
AMU 2481
4. Specifications
4.1. Outline Dimensions
Fig. 4–1: AMU 2481 in 24–pin Dil Plastic Package,
20 B 24 according to DIN 41 870
Dimensions in mm
2.4
1.2 x 45°
40
17
29
18
28
17.4
+0.25
2.4
0.254
0.711
17.4+0.25
39
1.27± 0.1
2
7
16.5 ± 0.1
1
0.45 +0.1
6
10 x 1.27 = 12.7 ± 0.1
1.27± 0.1
1.2 x 45°
10 x 1.27 = 12.7 ± 0.1
Weight approx. 4.5 g
1.9 1.5
4.05
4.75 ± 0.15
16.5 ± 0.1
0.1
Fig. 4–2: AMU 2481 in 44–pin PLCC Package,
Weight approx. 2.2 g
Dimensions in mm
4.2. Pin Connections
9
S–Data Input
4.2.1. 24–Pin DIL Package
10
VISB Internal Substrate Bias Voltage
1
IREF2 Reference Current Input (for DAC 2)
11
Reset Input
2
Leave Vacant
12
Ground (Digital)
3
IM Bus Data Input/Output
13
ΦM Clock Input
4
IM Bus Ident Input
14
VSUP
5
IM Bus Clock Input
15
S–Ident Input/Output
6
S–Data Output
16
PDM2 Digital Input (R)
7
Leave Vacant
17
PDM1 Digital Input (L)
8
S–Clock Input/Output
18
Leave Vacant
16
MICRONAS INTERMETALL
AMU 2481
19
DAC2 Output Ch3
25
Leave Vacant
20
DAC 2 Output Ch 4
26
Leave Vacant
21
IREF1 Reference Current Input (for DAC1)
27
IM Bus Data Input/Output
22
DAC1 Output Ch1
28
Leave Vacant
23
DAC1 Output Ch2
29
IM Bus Ident Input
24
Ground (Analog)
30
Leave Vacant
31
IM Bus Clock Input
32
Leave Vacant
33
S–Data Output
34
Leave Vacant
35
VSUP
36
Ground Supply
37
S–Clock Input/Output
38
Leave Vacant
39
S–Data Input
40
Leave Vacant
41
Leave Vacant
42
Reset Input
43
S–Clock Output 2**
44
ΦM Main Clock Output**
4.2.2. 44–Pin PLCC Package
1
ΦM Main Clock Input
2
Leave Vacant
3
Leave Vacant
4
Leave Vacant
5
Leave Vacant
6
Leave Vacant
7
S–Ident Input/Output
8
S–Ident Output 2**
9
PDM2 Digital Input (R)
10
Leave Vacant
11
PDM1 Digital Input (L)
12
Vacant*
13
DAC2 Output Ch3
14
Vacant*
15
DAC2 Output Ch4
16
Vacant*
17
IREF1 Reference Current Input (for DAC1)
18
DAC1 Output Ch1
19
Vacant*
20
DAC1 Output Ch2
21
Leave Vacant
22
Ground (Analog)
23
VISB Internal Substrate Bias Voltage
24
IREF2 Reference Current Input (for DAC2)
MICRONAS INTERMETALL
* = In order to minimize crosstalk, these pins should be
appropriately grounded.
** = additional outputs compared to 24–pin Dil package
pins 8, 43 see section 2.1.2.2.; pin 44 see section 2.3.
4.3. Pin Descriptions (pin numbers for 24–pin DIL
package)
Pins 1 and 21 – Reference Current Inputs (Fig. 4–3)
These inputs require a current of 150 µA called reference current IREF and serving for volume adjustment in
the DAC interfaces.
Pin 12 – Digital Ground, 0
This pin must be connected to the negative of the supply.
It must be used for ground connections in conjunction
with digital signals.
Pin 3 – IM Bus Input/Output (Fig. 4–8)
Via this pin, the AMU 2481 is connected to the IM bus
and communicates with the CCU.
17
AMU 2481
Pins 4 and 5 – IM Bus Inputs (Fig. 4–4)
Via these pins, the AMU 2481 is connected to the IM bus
and receives instructions from the CCU.
Pins 6, 8, 9 and 15 – Serial Audio Interface (S Bus)
Pin 9 is the S– Data input (Fig. 4–7) and pin 6 the S– Data
output (Fig. 4–9). Pins 8 and 15 are S–Clock and S–
Ident inputs/outputs (Fig. 4–10), the status depending
on bit 4 in coefficient k33 (see sections 2.1.2.2. and
3.13.).
VSUP
E
E
GND
VSUP
Pin 14 – VSUP Supply Voltage
This pin must be connected to the positive of the supply.
D
Pin 10 – VISB Internal Substrate Bias Voltage
The AMU 2481 has an on–chip substrate bias generator
which produces a negative bias voltage of about 3.4 V.
Pin 10 should have a 0.1 µF capacitor to ground.
Pin 11 – Reset Input (Fig. 4–4)
In the steady state, high level is required at pin 11. A low
level normalizes the AMU 2481. Initialization is described in section 3.12.
Pin 13 – ΦM Main Clock Input (Fig. 4–5)
This pin receives the required main clock signal from the
MCU 2600 or MCU 2632 Clock Generator IC or from the
DMA 2271 D2–MAC Decoder or the MSP 2410 Multistandard Sound Processor.
Pins 16 and 17 – PDM2 and PDM1 Digital Input (Fig.
4–6)
These pins receive the pulse–density modulated output
signals of the ADC 2311 E.
Pins 19 and 20 – DAC2 Outputs Ch3 and Ch4 (Fig. 4–9)
These pins supply the audio output signals as output
currents whose amplitude is determined by the reference current IREF2 fed to pin 1. The output signal of pins
19 and 20 is only influenced by the VOL1 volume control.
Pins 22 and 23 – DAC 1 Outputs Ch1 and Ch2 (Fig. 4–9)
These pins supply the audio output signals as output
currents whose amplitude is determined by the reference current IREF1 fed to pin 21. The output signal of pins
22 and 23 is influenced by the VOL 1 and VOL 2 volume
control facilities.
E
BIAS
VSUP
D
D
D
E
GND
Fig. 4–5:
Input Pin 13
VSUP
D
D
E
E
BIAS
GND
Fig. 4–6:
Input Pins 16, 17
VSUP
D
E
BIAS
GND
4.4. Pin Circuits (pin numbers for 24–pin DIL package)
D
18
Fig. 4–4:
Input Pins 4, 5, 11
GND
Pin 24 – Analog Ground 0
This pin must be connected to the negative of the supply.
It serves as ground connection for analog signals.
The following figures schematically show the circuitry at
the various pins. The integrated protection structures
are not shown. The letter “ E” means enhancement, the
letter “D” depletion.
Fig. 4–3:
Input Pins 1, 21
Fig. 4–7:
Input Pin 9
VSUP
E
E
GND
Fig. 4–8:
Input/Output Pin 3
MICRONAS INTERMETALL
AMU 2481
VSUP
VSUP
D
E
BIAS
E
Fig. 4–9:
Output Pin 6,19, 20, 22
GND
E
Fig. 4–10:
Input/Output Pins 8, 15
GND
4.5. Electrical Characteristics (pin numbers for 24–pin DIL package)
All voltages are referred to ground.
4.5.1. Absolute Maximum Ratings
Symbol
Parameter
Pin No.
Min.
Max.
Unit
TA
Ambient Operating Temperature
–
0
65
°C
TS
Storage Temperature
–
–40
+125
°C
VSUP
Supply Voltage
14
–
6
V
VI
Input Voltage, all Inputs
–
–0.3 V
VSUP
–
VDO
DAC Output Voltage
19, 20,
22, 23
–0.3
+12
V
VSO
S–Bus Output Voltage
6, 8, 15
–0.3 V
VSUP
–
IDSO
DAC and S–Bus Output Current
6, 8, 15,
19, 20,
22, 23
–
10
mA
4.5.2. Recommended Operating Conditions at TA = 0 to 65 °C, fΦM = 14.3 to 18.4 MHz
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
VSUP
Supply Voltage
14
4.75
5.0
5.25
V
VΦMIDC
ΦM Clock Input D.C. Voltage
13
1.5
–
3.5
V
VΦMIAC
ΦM Clock Input A.C. Voltage (p–p)
0.8
–
2.5
V
tΦMIH
tΦMIL
ΦM Clock Input
High/Low Ratio
0.9
1.0
1.1
–
tΦMIHL
ΦM Clock Input High to Low
Transition Time
–
–
0.15
fΦM
–
VREIL
Reset Input Low Voltage
–
–
1.2
V
VREIH
Reset Input High Voltage
2.4
–
–
V
IREF
Reference Input Current
1, 21
–
0.15
–
mA
VIMIL
IM Bus Input Low Voltage
3 to 5
–
–
0.8
V
VIMIH
IM Bus Input High Voltage
2.4
–
–
V
fΦI
ΦI IM Bus Clock Frequency
0.05
–
170
kHz
MICRONAS INTERMETALL
11
19
AMU 2481
Recommended Operating Conditions, continued
20
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
tIM1
ΦI Clock Input Delay Time
after IM Bus Ident Input
3 to 5
0
–
–
–
tIM2
ΦI Clock Input Low Pulse Time
3.0
–
–
µs
tIM3
ΦI Clock Input High Pulse Time
3.0
–
–
µs
tIM4
ΦI Clock Input Setup Time
before Ident Input High
0
–
–
–
tIM5
ΦI Clock Input Hold Time
after Ident Input High
1.5
–
–
µs
tIM6
ΦI Clock Input Setup Time
before Ident End–Pulse Input
6.0
–
–
µs
tIM7
IM Bus Data Input Delay Time
after ΦI Clock Input
0
–
–
–
tIM8
IM Bus Data Input Setup Time
before ΦI Clock Input
0
–
–
–
tIM9
IM Bus Data Input Hold Time
after ΦI Clock Input
0
–
–
–
tIM10
IM Bus Ident End–Pulse Low Time
3.0
–
–
µs
VSIL
S Bus Input Low Voltage
–
–
0.4
V
–ISIH
S Bus Input High Current
–
–
20
µA
fIS
ΦS Clock Input Frequency
–
fΦM
4
–
–
tS2
tS1
ΦS Clock Input
High/Low Ratio
0.8
1
1.2
–
tS3
ΦS Clock Input Setup Time
before Ident End–Pulse Input
8, 15
150
–
–
ns
tS4
S Bus Data Input Setup Time
before ΦS Clock Input
8, 9
50
–
–
ns
tS5
S Bus Data Input Hold Time
after ΦS Clock Input
50
–
–
ns
tS6
S Bus Ident End–Pulse
Input Low Time
15
150
–
–
ns
VDIL
Digital Input Low Voltage
16, 17
–
–
0.5
VSUP
–0.3 V
–
VDIH
Digital Input High Voltage
0.5
VSUP
+0.3 V
–
–
–
CISB
Internal Substrate Bias
Voltage Filter Capacitor
–
100
–
nF
8, 9, 15
8
10
MICRONAS INTERMETALL
AMU 2481
4.5.3. Characteristics at TA = 0 to 65 °C, VSUP = 4.75 to 5.25 V, fΦM = 14.3 to 18.4 MHz
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
ISUP
Supply Current
14
–
140
170
mA
VIMOL
IM Bus Output Low Voltage
3
–
–
0.4
V
IIMO = 3 mA
IIMOH
IM Bus Output High Current
–
–
10
µA
VIMO = 5 V
–ISIL
S–Clock/Ident/Data Input
Low Current
–
1
2.7
mA
VSI = 0.3 V
VSIH
S–Clock/Ident/Data Input
High Voltage
–
–
1.2
V
ISI = 0
VSOL
S–Bus Output Low Voltage
8, 9, 15
–
–
0.3
V
ISO = 6 mA
ISOH
S–Data Output High Current
6
–
–
10
µA
VSO = 5 V
IOMAIN
DAC1 Output
Peak–to–Peak Current
22, 23
–
0.81
–
mA
IREF1 =0.15 mA,
VOL2 = 0 dB
–
25
–
µA
IREF1 =0.15 mA,
VOL2 = –30 dB
IREF2 =0.15 mA
8, 9, 15
Test Conditions
IOAUX
DAC2 Output
Peak–to–Peak Current
19, 20
–
0.81
–
mA
THD
Total Hamonic Distortion of
DAC Output
19, 20,
22, 23
–
–
0.1
%
VISB
Internal Substrate Bias Voltage
10
–
–3.4
–
V
CISB = 100 nF
VREF1
Reference Input Voltage Drop
21
–
2.5
–
V
RREF1 = 68 kOhm from
+12 V, VOL2 = 0 dB
–
0.45
–
V
RREF1 = 68 kOhm from
+12 V, VOL2 = –30 dB
–
2.5
–
V
RREF2 = 68 kOhm from
+12 V
VREF2
Reference Input Voltage Drop
MICRONAS INTERMETALL
1
21
AMU 2481
5. Appendix 1: Application Circuit (pin numbers for 24–pin Dil package)
A
68k
0.1µ 10 µ
+
PDM2
from ADC
PDM1
LV
S–Data
In
S–Clock
In/Out
S–Ident
In/Out
S–Data
Out
S Bus
from DMA
or MSP
24
15 µ
5.6 µH
4.7 n
L1
+
+
10
+12 V
D
1
21
12
100
100
+5 V
+
A
22 µ
14
16
19
17
20
Ch 3
4.7 k
1µ
AF Out
22 µ
18
+
1n *)
A
9
AMU 2481
22
Ch 1
4.7 k
8
1µ
23
15
Ch 4
A
AF Out
Ch 2
1n *)
A
6
2
11
3
4
13
LV
D
Reset
7
5
LV
ID CL
IM Bus
ΦM Main Clock
*optionally 10 nF for 50 µs analog deemphasis
Fig. 5–1: Application circuit
22
MICRONAS INTERMETALL
6. Appendix 2: Program Structure
MICRONAS INTERMETALL
AMU 2481
23
AMU 2481
MICRONAS INTERMETALL GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: http://www.intermetall.de
Printed in Germany
by Simon Druck GmbH & Co., Freiburg (8/92)
Order No. 6251-324-3E
24
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for
conclusion of a contract nor shall they be construed as to
create any liability. Any new issue of this data sheet invalidates
previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the
same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH
does not assume responsibility for patent infringements or
other rights of third parties which may result from its use.
Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases.
MICRONAS INTERMETALL
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