19-1003; Rev 2; 6/05 KIT ATION EVALU E L B A AVAIL 1.8V, 12-Bit, 170Msps ADC for Broadband Applications The MAX1213 is a monolithic, 12-bit, 170Msps analogto-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies up to 300MHz. The product operates with conversion rates up to 170Msps while consuming only 788mW. At 170Msps and an input frequency up to 250MHz, the MAX1213 achieves a spurious-free dynamic range (SFDR) of 72.9dBc. Its excellent signal-to-noise ratio (SNR) of 65.8dB at 10MHz remains flat (within 2dB) for input tones up to 250MHz. This ADC yields an excellent low-noise floor of -68dBFS, which makes it ideal for wideband applications such as cable head-end receivers and power-amplifier predistortion in cellular base-station transceivers. The MAX1213 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible and the data format can be selected to be either two’s complement or offset binary. The MAX1213 is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range. See the Pin-Compatible Versions table for a complete selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in this family. Features ♦ 170Msps Conversion Rate ♦ Low Noise Floor of -68dBFS ♦ Excellent Low-Noise Characteristics SNR = 65.8dB at fIN = 65MHz SNR = 64.5dB at fIN = 250MHz ♦ Excellent Dynamic Range SFDR = 76.5dBc at fIN = 65MHz SFDR = 72.9dBc at fIN = 250MHz ♦ 59.5dB NPR for fNOTCH = 28.8MHz and a Noise Bandwidth of 50MHz ♦ Single 1.8V Supply ♦ 788mW Power Dissipation at fSAMPLE = 170MHz and fIN = 65MHz ♦ On-Chip Track-and-Hold Amplifier ♦ Internal 1.23V-Bandgap Reference ♦ On-Chip Selectable Divide-by-2 Clock Input ♦ LVDS Digital Outputs with Data Clock Output ♦ MAX1213 EV Kit Available Ordering Information PART MAX1213EGK Cable Head-End Receivers PIN-PACKAGE -40°C to +85°C 68 QFN-EP* *EP = Exposed paddle. Applications Base-Station Power-Amplifier Linearization TEMP RANGE Pin-Compatible Versions PART RESOLUTION (BITS) SPEED GRADE (Msps) Wireless and Wired Broadband Communication MAX1121 8 250 Communications Test Equipment MAX1122 10 170 MAX1123 10 210 MAX1124 10 250 MAX1213 12 170 MAX1214 12 210 MAX1215 12 250 Radar and Satellite Subsystems Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1213 General Description MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications ABSOLUTE MAXIMUM RATINGS AVCC to AGND ..................................................... -0.3V to +2.1V OVCC to OGND .................................................... -0.3V to +2.1V AVCC to OVCC ...................................................... -0.3V to +2.1V AGND to OGND ................................................... -0.3V to +0.3V INP, INN to AGND ....................................-0.3V to (AVCC + 0.3V) REFIO, REFADJ to AGND ........................-0.3V to (AVCC + 0.3V) All Digital Inputs to AGND........................-0.3V to (AVCC + 0.3V) All Digital Outputs to OGND ....................-0.3V to (OVCC + 0.3V) ESD on All Pins (Human Body Model) .............................±2000V Thermal Resistance (multilayer board) θjc ................................................................................0.8°C/W θja .................................................................................24°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature .....................................................+150°C Storage Temperature Range ............................-60°C to +150°C Maximum Current into Any Pin............................................50mA Lead Temperature (soldering,10s) ..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 12 Integral Nonlinearity (Note 2) INL Differential Nonlinearity (Note 2) DNL Transfer Curve Offset VOS Bits -2 ±0.75 +2 LSB TA = +25°C, No missing codes -0.8 ±0.3 +0.8 LSB TA = +25°C (Note 2) -3.3 fIN = 10MHz, TA = +25°C +3.3 Offset Temperature Drift 40 mV µV/°C ANALOG INPUTS (INP, INN) Full-Scale Input Voltage Range VFS TA = +25°C (Note 2) 1320 1454 Full-Scale Range Temperature Drift 130 Common-Mode Input Range VCM Input Capacitance CIN Differential Input Resistance Full-Power Analog Bandwidth 1590 Internally self-biased RIN mVP-P ppm/°C 1.365 ±0.15 V 2.5 pF 3.00 4.2 FPBW 6.25 700 kΩ MHz REFERENCE (REFIO, REFADJ) Reference Output Voltage VREFIO TA = +25°C, REFADJ = AGND 1.18 1.23 Reference Temperature Drift REFADJ Input High Voltage 90 VREFADJ Used to disable the internal reference AVCC - 0.1 1.30 V ppm/°C V SAMPLING CHARACTERISTICS Maximum Sampling Rate fSAMPLE Minimum Sampling Rate fSAMPLE Clock Duty Cycle 170 MHz 20 40 to 60 % Aperture Delay tAD Figures 4, 11 620 ps Aperture Jitter tAJ Figure 11 0.2 psRMS 2 Set by clock-management circuit MHz _______________________________________________________________________________________ 1.8V, 12-Bit, 170Msps ADC for Broadband Applications (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 200 500 mVP-P 1.15 ±0.25 V CLOCK INPUTS (CLKP, CLKN) Differential Clock Input Amplitude (Note 3) Clock Input Common-Mode Voltage Range Internally self-biased Clock Differential Input Resistance RCLK 11 ±25% kΩ Clock Differential Input Capacitance CCLK 5 pF DYNAMIC CHARACTERISTICS (at -1dBFS) Signal-to-Noise Ratio SNR fIN = 10MHz, TA ≥ +25°C 64.5 66.2 fIN = 65MHz, TA ≥ +25°C 64.5 65.8 fIN = 200MHz fIN = 250MHz Signal-to-Noise and Distortion SINAD 64.5 fIN = 10MHz, TA ≥ +25°C 64 65.9 fIN = 65MHz, TA ≥ +25°C 63.5 65.2 fIN = 200MHz SFDR Worst Harmonics (HD2 or HD3) Two-Tone Intermodulation Distortion Noise Power Ratio TTIMD NPR dB 63.9 fIN = 250MHz Spurious-Free Dynamic Range dB 65 63.5 fIN = 10MHz, TA ≥ +25°C 73 83 fIN = 65MHz, TA ≥ +25°C 69 76.5 fIN = 200MHz 70.7 fIN = 250MHz 72.9 dBc fIN = 10MHz, TA ≥ +25°C -85 -73 fIN = 65MHz, TA ≥ +25°C -76.5 -69 fIN = 200MHz -70.7 fIN = 250MHz -72.9 dBc fIN1 = 99MHz at -7dBFS, fIN2 = 101MHz at -7dBFS -78 dBc fNOTCH = 28.8MHz ±1MHz, noise BW = 50MHz, AIN = -9.1dBFS 59.5 dB LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N) Differential Output Voltage |VOD| RL = 100Ω ±1% 250 400 mV Output Offset Voltage OVOS RL = 100Ω ±1% 1.125 1.310 V _______________________________________________________________________________________ 3 MAX1213 ELECTRICAL CHARACTERISTICS (continued) MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications ELECTRICAL CHARACTERISTICS (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS DIGITAL INPUTS (CLKDIV, T/B) Digital Input Voltage Low VIL Digital Input Voltage High VIH 0.2 x AVCC 0.8 x AVCC V V TIMING CHARACTERISTICS CLK-to-Data Propagation Delay tPDL Figure 4 1.75 ns CLK-to-DCLK Propagation Delay tCPDL Figure 4 4.95 ns DCLK-to-Data Propagation Delay tPDL - tCPDL Figure 4 (Note 3) 2.8 3.2 3.6 ns LVDS Output Rise Time tRISE 20% to 80%, CL = 5pF 460 LVDS Output Fall Time tFALL 20% to 80%, CL = 5pF 460 ps 11 Clock cycles Output Data Pipeline Delay tLATENCY Figure 4 ps POWER REQUIREMENTS Analog Supply Voltage Range AVCC 1.70 1.80 1.90 V Digital Supply Voltage Range OVCC 1.70 1.80 1.90 V mA Analog Supply Current IAVCC fIN = 65MHz 375 425 Digital Supply Current IOVCC fIN = 65MHz 63 75 mA Analog Power Dissipation PDISS fIN = 65MHz 788 900 mW Power-Supply Rejection Ratio (Note 4) PSRR Offset 1.8 mV/V Gain 1.5 %FS/V Note 1: ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Note 2: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The fullscale range (FSR) is defined as 4095 x slope of the line. Note 3: Parameter guaranteed by design and characterization: TA = TMIN to TMAX. Note 4: PSRR is measured with both analog and digital supplies connected to the same potential. 4 _______________________________________________________________________________________ 1.8V, 12-Bit, 170Msps ADC for Broadband Applications -60 -70 HD2 HD3 -40 -50 -60 -40 -50 -60 MAX1213 toc02 -80 -90 -90 -100 -100 -100 30 -110 0 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) FFT PLOT (8192-POINT DATA RECORD) -20 -30 -40 -50 -60 HD3 HD2 -70 30 0 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) fSAMPLE = 170MHz fIN1 = 99.25659MHz fIN2 = 101.08276MHz AIN1 = AIN2 = -6.974dBFS IMD = -78dBc -20 -80 -30 -40 fIN1 -60 fIN1 - fIN2 fIN1 + fIN2 3fIN2 - 2fIN1 -80 -90 -90 -100 -100 -110 SNR 65 2fIN1 - fIN2 20 30 SFDR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170MHz, AIN = -1dBFS 90 85 10 20 30 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) 0 -50 -55 -60 80 70 65 60 -75 -80 50 -90 45 -95 40 HD2 50 100 150 fIN (MHz) 200 250 300 200 250 300 SNR 60 50 SINAD 40 30 20 -100 0 150 70 HD3 -70 -85 55 100 SNR/SINAD vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170MHz, fIN = 65.098877MHz) SNR/SINAD (dB) HD2/HD3 (dBc) -65 75 50 fIN (MHz) HD2/HD3 vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170MHz, AIN = -1dBFS) MAX1213 toc07 95 55 45 0 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) MAX1213 toc08 10 SINAD 60 50 -110 0 20 30 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) 70 fIN2 -50 -70 10 SNR/SINAD vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170MHz, AIN = -1dBFS) 0 -10 AMPLITUDE (dBFS) fSAMPLE = 170MHz fIN = 250.04038MHz AIN = -1.040dBFS SNR = 64.5dB SINAD = 63.5dB SFDR = 72.9dBc HD2 = -77.4dBc HD3 = -72.9dBc 20 TWO-TONE IMD PLOT (8192-POINT DATA RECORD) MAX1213 toc04 0 -10 10 SNR/SINAD (dB) 20 HD3 -80 -110 10 HD2 -70 -90 0 AMPLITUDE (dBFS) -30 -80 -110 SFDR (dBc) HD2 -70 -20 MAX1213 toc06 -50 -30 fSAMPLE = 170MHz fIN = 200.11108MHz AIN = -1.025dBFS SNR = 65dB SINAD = 63.9dB SFDR = 70.7dBc HD2 = -74.8dBc HD3 = -70.7dBc MAX1213 toc09 -40 -20 0 -10 AMPLITUDE (dBFS) -30 fSAMPLE = 170MHz fIN = 65.09888MHz AIN = -1.099dBFS SNR = 66.5dB SINAD = 65.7dB SFDR = 76dBc HD2 = -77.7dBc HD3 = -76dBc HD3 MAX1213 toc05 AMPLITUDE (dBFS) -20 0 -10 AMPLITUDE (dBFS) fSAMPLE = 170MHz fIN = 12.47192MHz AIN = -1.001dBFS SNR = 66.7dB SINAD = 66.4dB SFDR = 83.8dBc HD2 = -83.8dBc HD3 = -84dBc MAX1213 toc01 0 -10 FFT PLOT (8192-POINT DATA RECORD) FFT PLOT (8192-POINT DATA RECORD) MAX1213 toc03 FFT PLOT (8192-POINT DATA RECORD) 0 50 100 150 fIN (MHz) 200 250 300 10 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS) _______________________________________________________________________________________ 5 MAX1213 Typical Operating Characteristics (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) Typical Operating Characteristics (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) -40 50 40 65 -60 SNR/SINAD (dB) HD2/HD3 (dBc) 60 HD2 -70 HD3 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 55 50 -90 45 0 SINAD 60 -80 -100 30 SNR 70 -50 70 40 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 20 40 60 80 100 120 140 160 180 ANALOG INPUT AMPLITUDE (dBFS) ANALOG INPUT AMPLITUDE (dBFS) fSAMPLE (MHz) SFDR vs. SAMPLE FREQUENCY (fIN = 65MHz, AIN = -1dBFS) HD2/HD3 vs. SAMPLE FREQUENCY (fIN = 65MHz,AIN = -1dBFS) TOTAL POWER DISSIPATION vs. SAMPLE FREQUENCY (fIN = 65MHz, AIN = -1dBFS) -65 -70 HD3 810 -75 70 65 790 -80 PDISS (mW) HD2/HD3 (dBc) 75 HD2 -85 -90 770 750 -95 -100 60 MAX1213 toc15 80 830 MAX1213 toc14 -60 MAX1213 toc13 85 SFDR (dBc) 75 MAX1213 toc11 80 SFDR (dBc) -30 MAX1213 toc10 90 SNR/SINAD vs. SAMPLE FREQUENCY (fIN = 65MHz, AIN = -1dBFS) HD2/HD3 vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170MHz, fIN = 65.098877MHz) MAX1213 toc12 SFDR vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170MHz, fIN = 65.098877MHz) 730 -105 -110 55 40 60 40 60 80 100 120 140 160 180 20 60 80 100 120 140 160 180 fSAMPLE (MHz) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE GAIN BANDWIDTH PLOT (fSAMPLE = 170MHz, AIN = -1dBFS) 0.6 0.4 0.4 0.2 DNL (LSB) 0.8 0 -0.4 fIN = 12.5MHz 0.8 1 0 -1 0 -0.2 -2 -3 -4 -0.8 -0.4 -1.2 -0.6 -1.6 -0.8 -6 -2.0 -1.0 -7 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE MAX1213 toc18 1.0 GAIN (dB) fIN = 12.5MHz 0 40 fSAMPLE (MHz) 1.2 6 20 fSAMPLE (MHz) 2.0 1.6 710 0 80 100 120 140 160 180 MAX1213 toc17 20 MAX1213 toc16 0 INL (LSB) MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications -5 DIFFERENTIAL TRANSFORMER COUPLING 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE 10 100 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 1000 1.8V, 12-Bit, 170Msps ADC for Broadband Applications SNR/SINAD vs. TEMPERATURE (fIN = 65MHz, AIN = -1dBFS) 68 -60 78 -64 -68 76 67 -72 65 SINAD 64 HD2/HD3 (dBc) SFDR (dBc) SNR 66 74 72 70 63 -80 HD2 -84 -92 61 66 -96 60 64 -100 -40 -15 10 35 60 85 -40 -15 10 35 60 -40 85 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) SNR/SINAD, SFDR vs. SUPPLY VOLTAGE (fIN = 65.098877MHz, AIN = -1dBFS) INTERNAL REFERENCE vs. SUPPLY VOLTAGE PROPAGATION DELAY TIMES vs. TEMPERATURE SNR 68 64 5 1.2510 1.2490 1.2470 1.2450 1.75 1.80 1.85 1.90 1.75 VOLTAGE SUPPLY (V) 1.80 1.85 1.90 70 65 60 -40 NPR (dB) -60 35 -70 30 -80 25 -90 20 -100 -20 -15 -10 -5 0 35 60 85 -50 40 -25 fNOTCH = 28.8MHz NPR = 59.5dB -20 -40 ANALOG INPUT POWER (dBFS) 10 0 -10 -30 45 -15 NOISE-POWER RATIO PLOT (WIDE NOISE BANDWIDTH: 50MHz) 50 -30 tPDL TEMPERATURE (°C) 55 -35 2 VOLTAGE SUPPLY (V) NOISE-POWER RATIO vs. ANALOG INPUT POWER (fNOTCH = 28.2MHz ±1MHz) -40 3 0 1.70 MAX1213 toc25 1.70 tCPDL 4 1 SINAD 60 MAX1213 toc24 1.2530 VREFIO (V) 72 6 85 MAX1213 toc26 76 MEASURED AT THE REFIO PIN REFADJ = AVCC = OVCC PROPAGATION DELAY (ns) SFDR MAX1213 toc23 1.2550 MAX1213 toc22 AVCC = OVCC NPR (dB) SNR/SINAD, SFDR (dB, dBc) HD3 -76 -88 68 62 80 MAX1213 toc21 69 MAX1213 toc20 80 MAX1213 toc19 70 SNR/SINAD (dB) HD2/HD3 vs. TEMPERATURE (fIN = 65MHz, AIN = -1dBFS) SFDR vs. TEMPERATURE (fIN = 65MHz, AIN = -1dBFS) 0 5 10 15 20 25 30 35 40 45 50 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX1213 Typical Operating Characteristics (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications Pin Description PIN NAME FUNCTION 1, 6, 11–14, 20, 25, 62, 63, 65 AVCC Analog Supply Voltage. Bypass each pin with a parallel combination of 0.1µF and 0.22µF capacitors for best decoupling results. 2, 5, 7, 10, 15, 16, 18, 19, 21, 24, 64, 66, 67 AGND Analog Converter Ground 3 REFIO Reference Input/Output. With REFADJ pulled high, this I/O port allows an external reference source to be connected to the MAX1213. With REFADJ pulled low, the internal 1.23V bandgap reference is active. 4 REFADJ Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases FSR). If REFADJ is connected to AVCC, the internal reference can be overdriven with an external source connected to REFIO. If REFADJ is connected to AGND, the internal reference is used to determine the FSR of the data converter. 8 INP Positive Analog Input Terminal. Internally self-biased to 1.365V. 9 INN Negative Analog Input Terminal. Internally self-biased to 1.365V. Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s digital outputs are updated with. CLKDIV has an internal pulldown resistor. CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate. CLKDIV = 1: ADC updates digital outputs at input clock rate. 17 CLKDIV 22 CLKP True Clock Input. This input ideally requires an LVPECL-compatible input level to maintain the converter’s excellent performance. Internally self-biased to 1.15V. 23 CLKN Complementary Clock Input. This input ideally requires an LVPECL-compatible input level to maintain the converter’s excellent performance. Internally self-biased to 1.15V. 26, 45, 61 OGND Digital Converter Ground. Ground connection for digital circuitry and output drivers. 27, 28, 41, 44, 60 OVCC Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results. 29 D0N 30 D0P True Output Bit 0 (LSB) 31 D1N Complementary Output Bit 1 8 Complementary Output Bit 0 (LSB) 32 D1P True Output Bit 1 33 D2N Complementary Output Bit 2 34 D2P True Output Bit 2 35 D3N Complementary Output Bit 3 36 D3P True Output Bit 3 _______________________________________________________________________________________ 1.8V, 12-Bit, 170Msps ADC for Broadband Applications PIN NAME FUNCTION 37 D4N 38 D4P True Output Bit 4 39 D5N Complementary Output Bit 5 40 D5P True Output Bit 5 42 DCLKN Complementary Clock Output. This output provides an LVDS-compatible output level and can be used to synchronize external devices to the converter clock. 43 DCLKP True Clock Output. This output provides an LVDS-compatible output level and can be used to synchronize external devices to the converter clock. 46 D6N 47 D6P True Output Bit 6 48 D7N Complementary Output Bit 7 Complementary Output Bit 4 Complementary Output Bit 6 49 D7P True Output Bit 7 50 D8N Complementary Output Bit 8 51 D8P True Output Bit 8 52 D9N Complementary Output Bit 9 53 D9P True Output Bit 9 54 D10N Complementary Output Bit 10 55 D10P True Output Bit 10 56 D11N Complementary Output Bit 11 (MSB) 57 D11P True Output Bit 11 (MSB) 58 ORN Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORN flags this condition by transitioning low. 59 ORP True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP flags this condition by transitioning high. 68 T/B Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input controls the digital output format of the MAX1213. T/B has an internal pulldown resistor. T/B = 0: Two’s complement output format. T/B = 1: Binary output format. — EP Exposed Paddle. The exposed paddle is located on the backside of the chip and must be connected to analog group for optimum performance. _______________________________________________________________________________________ 9 MAX1213 Pin Description (continued) MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications CLKDIV CLKP CLOCKDIVIDER CONTROL CLKN INPUT BUFFER INP T/H INN 2.2kΩ 2.2kΩ DCLKP DCLKN CLOCK MANAGEMENT COMMON-MODE BUFFER 12-BIT PIPELINE QUANTIZER CORE LVDS DATA PORT D0P/N–D11P/N 12 ORP ORN REFERENCE MAX1213 REFIO REFADJ Figure 1. Simplified MAX1213 Block Diagram Detailed Description— Theory of Operation Analog Inputs (INP, INN) INP and INN are the fully differential inputs of the MAX1213. Differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced AC performance as the signals are progressing through the analog stages. The MAX1213 analog inputs are self-biased at a common-mode voltage of 1.365V and allow a differential input voltage swing of 1.454V P-P (Figure 2). Both inputs are self-biased 10 2.2kΩ TO COMMON MODE TO COMMON MODE AGND INN +VFS / 4 COMMON-MODE VOLTAGE (1.365V) VFS / 2 VFS / 2 COMMON-MODE VOLTAGE (1.365V) -VFS / 4 INP +VFS / 4 Each pipeline converter stage converts its input voltage to a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. The result is a 12-bit parallel digital output word in user-selectable two’s complement or offset binary output formats with LVDS-compatible output levels. See Figure 1 for a more detailed view of the MAX1213 architecture. 2.2kΩ -VFS / 4 Both positive (INP) and negative/complementary analog input terminals (INN) are centered around a common-mode voltage of 1.365V, and accept a differential analog input voltage swing of ±VFS / 4 each, resulting in a typical differential full-scale signal swing of 1.454VP-P. Inputs INP and INN are buffered prior to entering each T/H stage and are sampled when the differential sampling clock signal transitions high. INN INP 1.454VP-P DIFFERENTIAL FSR The MAX1213 uses a fully differential pipelined architecture that allows for high-speed conversion, optimized accuracy, and linearity while minimizing power consumption and die size. AVCC Figure 2. Simplified Analog Input Architecture and Allowable Input Voltage Range through 2kΩ resistors, resulting in a typical differential input resistance of 4kΩ. It is recommended to drive the analog inputs of the MAX1213 in AC-coupled configuration to achieve best dynamic performance. See the Transformer-Coupled, Differential Analog Input Drive section for a detailed discussion of this configuration. ______________________________________________________________________________________ 1.8V, 12-Bit, 170Msps ADC for Broadband Applications The MAX1213 also features an internal clock-management circuit (duty-cycle equalizer) that ensures that the clock signal applied to inputs CLKP and CLKN is processed to provide a 50% duty-cycle clock signal that desensitizes the performance of the converter to variations in the duty cycle of the input clock source. Note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum clock frequency of >20MHz to work appropriately and according to data sheet specifications. Data Clock Outputs (DCLKP, DCLKN) The MAX1213 features a differential clock output, which can be used to latch the digital output data with an external latch or receiver. Additionally, the clock output can be used to synchronize external devices (e.g., FPGAs) to the ADC. DCLKP and DCLKN are differential outputs with LVDS-compatible voltage levels. There is a 4.95ns delay time between the rising (falling) edge of CLKP (CLKN) and the rising edge of DCLKP (DCLKN). See Figure 4 for timing details. Clock Inputs (CLKP, CLKN) Designed for a differential LVDS clock input drive, it is recommended to drive the clock inputs of the MAX1213 with an LVDS- or LVPECL-compatible clock to achieve the best dynamic performance. The clock signal source must be a high-quality, low-phase noise with fast edge rates to avoid any degradation in the noise performance of the ADC. The clock inputs (CLKP, CLKN) are internally biased to 1.15V, accept a typical differential signal swing of 0.5VP-P, and are usually driven in AC-coupled configuration. See the Differential, AC-Coupled PECLCompatible Clock Input section for more circuit details on how to drive CLKP and CLKN appropriately. Although not recommended, the clock inputs also accept a singleended input signal. Divide-by-2 Clock Control (CLKDIV) The MAX1213 offers a clock control line (CLKDIV), which supports the reduction of clock jitter in a system. Connect CLKDIV to OGND to enable the ADC’s internal divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate. CLKDIV has an internal pulldown resistor and can be left open for applications that require this divide-by-2 mode. Connecting CLKDIV to OVCC disables the divide-by-2 mode. REFT ADC FULL SCALE = REFT-REFB 1V G REFERENCE SCALING AMPLIFIER REFB REFERENCE BUFFER REFIO 0.1µF REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER 100Ω* MAX1213 AVCC *REFADJ MAY BE SHORTED TO AGND DIRECTLY AVCC/2 REFT: TOP OF REFERENCE LADDER. REFB: BOTTOM OF REFERENCE LADDER. Figure 3. Simplified Reference Architecture ______________________________________________________________________________________ 11 MAX1213 On-Chip Reference Circuit The MAX1213 features an internal 1.23V bandgap reference circuit (Figure 3), which in combination with an internal reference-scaling amplifier determines the FSR of the MAX1213. Bypass REFIO with a 0.1µF capacitor to AGND. To compensate for gain errors or increase the ADC’s FSR, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100kΩ trim potentiometer) between REFADJ and AGND or REFADJ and REFIO. See the Applications Information section for a detailed description of this process. To disable the internal reference, connect REFADJ to AVCC. In this configuration, an external, stable reference must be applied to REFIO to set the converter’s full scale. To enable the internal reference, connect REFADJ to AGND. MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications System Timing Requirements Figure 4 depicts the relationship between the clock input and output, analog input, sampling event, and data output. The MAX1213 samples on the rising (falling) edge of CLKP (CLKN). Output data is valid on the next rising (falling) edge of the DCLKP (DCLKN) clock, but has an internal latency of 11 clock cycles. Digital Outputs (D0P/N–D11P/N, DCLKP/N, ORP/N) and Control Input T/B Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N are LVDS compatible, and data on D0P/N–D11P/N is presented in either binary or two’s-complement format (Table 1). The T/B control line is an LVCMOS-compatible input, which allows the user to select the desired output format. Pulling T/B low outputs data in two’s complement and pulling it high presents data in offset binary format on the 12-bit parallel bus. T/B has an internal pulldown resistor and may be left unconnected in applications using only two’s complement output for- SAMPLING EVENT SAMPLING EVENT mat. All LVDS outputs provide a typical voltage swing of 0.325V around a common-mode voltage of roughly 1.15V, and must be differentially terminated at the far end of each transmission line pair (true and complementary) with 100Ω. The LVDS outputs are powered from a separate power supply, which can be operated between 1.7V and 1.9V. The MAX1213 offers an additional differential output pair (ORP, ORN) to flag out-of-range conditions, where out-of-range is above positive or below negative full scale. An out-of-range condition is identified with ORP (ORN) transitioning high (low). Note: Although a differential LVDS output architecture reduces single-ended transients to the supply and ground planes, capacitive loading on the digital outputs should still be kept as low as possible. Using LVDS buffers on the digital outputs of the ADC when driving larger loads may improve overall performance and reduce system-timing constraints. SAMPLING EVENT SAMPLING EVENT INN INP tCH tAD tCL CLKN N N+9 N+8 N+1 CLKP tCPDL tLATENCY DCLKP N-8 N+1 N N-7 DCLKN tCPDL - tPDL tPDL D0P/N– D11P/N ORP/N N-8 N-7 N-1 N tPDL - tPDL~ 0.4 x tSAMPLE WITH tSAMPLE = 1/fSAMPLE NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA. Figure 4. System and Output Timing Diagram 12 ______________________________________________________________________________________ N+1 1.8V, 12-Bit, 170Msps ADC for Broadband Applications INP ANALOG INPUT VOLTAGE LEVEL INN ANALOG INPUT VOLTAGE LEVEL OUT-OF-RANGE ORP (ORN) > VCM + VFS / 4 < VCM - VFS / 4 1 (0) 1111 1111 1111 (exceeds +FS, OR set) VCM + VFS / 4 VCM - VFS / 4 0 (1) 1111 1111 1111 (+FS) 0111 1111 1111 (+FS) 0000 0000 0000 or 1111 1111 1111 (FS/2) BINARY DIGITAL OUTPUT CODE (D11P/N–D0P/N) TWO’S COMPLEMENT DIGITAL OUTPUT CODE (D11P/N–D0P/N) 0111 1111 1111 (exceeds +FS, OR set) VCM VCM 0 (1) 1000 0000 0000 or 0111 1111 1111 (FS/2) VCM - VFS / 4 VCM + VFS / 4 0 (1) 0000 0000 0000 (-FS) 1000 0000 0000 (-FS) 1 (0) 00 0000 0000 (exceeds -FS, OR set) 10 0000 0000 (exceeds -FS, OR set) < VCM + VFS / 4 > VCM - VFS / 4 OVCC REFT ADC FULL SCALE = REFT-REFB REFERENCE BUFFER G REFERENCE SCALING AMPLIFIER REFB 1V VOP VON REFIO 0.1µF 2.2kΩ 13kΩ TO 1MΩ REFADJ 2.2kΩ CONTROL LINE TO DISABLE REFERENCE BUFFER Applications Information FSR Adjustments Using the Internal Bandgap Reference The MAX1213 supports a full-scale adjustment range of 10% (±5%). To decrease the full-scale signal range, an external resistor value ranging from 13kΩ to 1MΩ may be added between REFADJ and AGND. A similar approach can be taken to increase the ADC’s full-scale range (FSR). Adding a variable resistor, potentiometer, or predetermined resistor value between REFADJ and REFIO increases the FSR of the data converter. Figure 6a shows the two possible configurations and their impact on the overall full-scale range adjustment of the MAX1213. Do not use resistor values of less than 13kΩ to avoid instability of the internal gain regulation loop for the bandgap reference. See Figure 6b for the results of the adjustment range for a selection of resistors used to trim the full-scale range of the MAX1213. AVCC AVCC/2 REFT: TOP OF REFERENCE LADDER. REFB: BOTTOM OF REFERENCE LADDER. Figure 6a: Circuit Suggestions to Adjust the ADC’s Full-Scale Range FS VOLTAGE vs. FS ADJUST RESISTOR 1.57 MAX1213 fig06b Figure 5. Simplified LVDS Output Architecture MAX1213 1.55 1.53 RESISTOR VALUE APPLIED BETWEEN REFADJ AND REFIO INCREASES VFS 1.51 VFS (V) OGND 13kΩ TO 1MΩ 1.49 1.47 1.45 1.43 RESISTOR VALUE APPLIED BETWEEN REFADJ AND AGND DECREASES VFS 1.41 1.39 1.37 0 125 250 375 500 625 750 875 1000 FS ADJUST RESISTOR (kΩ) Figure 6b: FS Adjustment Range vs. FS Adjustment Resistor ______________________________________________________________________________________ 13 MAX1213 Table 1. MAX1213 Digital Output Coding MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications Differential, AC-Coupled, LVPECL-Compatible Clock Input The MAX1213 dynamic performance depends on the use of a very clean clock source. The phase noise floor of the clock source has a negative impact on the SNR performance. Spurious signals on the clock signal source also affect the ADC’s dynamic range. The preferred method of clocking the MAX1213 is differentially with LVDS- or LVPECL-compatible input levels. The fast data transition rates of these logic families minimize the clock-input circuitry’s transition uncertainty, thereby improving the SNR performance. To accomplish this, a 50Ω reverse-terminated clock signal source with low phase noise is AC-coupled into a fast differential receiver such as the MC100LVEL16D (Figure 7). The receiver produces the necessary LVPECL output levels to drive the clock inputs of the data converter. Transformer-Coupled, Differential Analog Input Drive In general, the MAX1213 provides the best SFDR and THD with fully differential input signals and it is not re- commended to drive the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics are usually lower since INP and INN are balanced, and each of the ADC inputs only requires half the signal swing compared to a single-ended configuration. Wideband RF transformers provide an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1213 to reach its optimum dynamic performance. A secondary-side termination of a 1:1 transformer (e.g., Mini-Circuit’s ADT1-1WT) into two separate 24.9Ω ±1% resistors (use tight resistor tolerances to minimize effects of imbalance; 0.5% would be an ideal choice) placed between top/bottom and center tap of the transformer is recommended to maximize the ADC’s dynamic range. This configuration optimizes THD and SFDR performance of the ADC by reducing the effects of transformer parasitics. However, the source impedance combined with the shunt capacitance provided by a PC board and the ADC’s parasitic capacitance limit the ADC’s full-power input bandwidth to approximately 600MHz. VCLK 0.1µF SINGLE-ENDED INPUT TERMINAL 8 0.1µF 0.1µF 2 7 150Ω 50Ω MC100LVEL16D 0.1µF 6 3 510Ω 150Ω 510Ω AVCC OVCC 4 5 0.01µF INP CLKN CLKP D0P/N–D11P/N VGND MAX1213 INN 12 AGND OGND Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration 14 ______________________________________________________________________________________ 1.8V, 12-Bit, 170Msps ADC for Broadband Applications Single-Ended, AC-Coupled Analog Inputs Although not recommended, the MAX1213 can be used in single-ended mode (Figure 9). Analog signals can be AC-coupled to the positive input INP through a 0.1µF capacitor and terminated with a 49.9Ω resistor to AGND. The negative input should be reverse terminated with 24.9Ω resistors and AC-grounded with a 0.1µF capacitor. Grounding, Bypassing, and Board Layout Considerations The MAX1213 requires board layout design techniques suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The analog and digital supply voltage pins accept input voltage ranges of 1.7V to 1.9V. Although both supply types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by digital switching currents, which can couple into the analog supply network. Isolate analog and digital supplies (AVCC and OVCC) where they enter the PC board with separate networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND). AVCC SINGLE-ENDED INPUT TERMINAL 10Ω 0.1µF ADT1-1WT OVCC INP ADT1-1WT D0P/N–D11P/N 25Ω MAX1213 25Ω 12 INN 10Ω 0.1µF AGND OGND Figure 8. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination AVCC SINGLE-ENDED INPUT TERMINAL 0.1µF OVCC INP D0P/N–D11P/N 50Ω 0.1µF MAX1213 INN 12 25Ω AGND OGND Figure 9. Single-Ended AC-Coupled Analog Input Configuration ______________________________________________________________________________________ 15 MAX1213 To further enhance THD and SFDR performance at high-input frequencies (>100MHz), a second transformer (Figure 8) should be placed in series with the single-ended-to-differential conversion transformer. This transformer reduces the increase of even-order harmonics at high frequencies. MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications To achieve optimum performance, provide each supply with a separate network of a 47µF tantalum capacitor and parallel combinations of 10µF and 1µF ceramic capacitors. Additionally, the ADC requires each supply pin to be bypassed with separate 0.1µF ceramic capacitors (Figure 10). Locate these capacitors directly at the ADC supply pins or as close as possible to the MAX1213. Choose surface-mount capacitors, whose preferred location should be on the same side as the converter to save space and minimize the inductance. If close placement on the same side is not possible, these bypassing capacitors may be routed through vias to the bottom side of the PC board. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the ADC’s package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The dynamic currents that may need to travel long distances before they are recombined at a common-source ground, resulting in large and undesirable ground loops, are a major concern with this approach. Ground loops can degrade the input noise by coupling back to the analog front end of the converter, resulting in increased spurious activity, leading to decreased noise performance. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. To minimize the coupling of the digital output signals from the analog input, segregate the digital output bus carefully from the analog input circuitry. To further minimize the effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sections of the ADC. This approach does not require split ground planes, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. The MAX1213 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater design flexibility, increased thermal dissipation, and optimized AC performance of the ADC. The exposed paddle (EP) must be soldered down to AGND. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the board with standard infrared (IR) flow soldering techniques. Thermal efficiency is one of the factors for selecting a package with an exposed pad for the MAX1213. The exposed pad improves thermal and ensures a solid ground connection between the DAC and the PC board’s analog ground layer. Considerable care must be taken when routing the digital output traces for a high-speed, high-resolution data converter. It is recommended running the LVDS output traces as differential lines with 100Ω matched impedance from the ADC to the LVDS load device. BYPASSING-ADC LEVEL AVCC BYPASSING-BOARD LEVEL OVCC 0.1µF AVCC 0.1µF 1µF AGND 10µF 47µF ANALOG POWERSUPPLY SOURCE 10µF 47µF DIGITAL/OUTPUT DRIVER POWERSUPPLY SOURCE OGND D0P/N–D11P/N OVCC MAX1213 12 1µF AGND OGND NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL) SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE AS POSSIBLE TO THE ADC. Figure 10. Grounding, Bypassing, and Decoupling Recommendations for MAX1213 16 ______________________________________________________________________________________ 1.8V, 12-Bit, 170Msps ADC for Broadband Applications Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. However, the static linearity parameters for the MAX1213 are measured using the histogram method with an input frequency of 10MHz. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. The MAX1213’s DNL specification is measured with the histogram method based on a 10MHz input tone. Dynamic Parameter Definitions Aperture Jitter Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11). CLKN tion error only and results directly from the ADC’s resolution (N bits): SNR[max] = 6.02 x N + 1.76 In reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the SNR calculation and should be considered when determining the signal-to-noise ratio in ADC. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In the case of the MAX1213, SINAD is computed from a curve fit. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the ADC’s full-scale range. Intermodulation Distortion (IMD) IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: VIM12 + VIM22 + ...... + VIM32 + VIMn2 IMD = 20 × log V12 + V22 CLKP ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) T/H TRACK HOLD TRACK Figure11. Aperture Jitter/Delay Specifications Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantiza- The fundamental input tone amplitudes (V1 and V2) are at -7dBFS. The intermodulation products are the amplitudes of the output spectrum at the following frequencies: • Second-order intermodulation products: fIN1 + fIN2, fIN2 - fIN1 • Third-order intermodulation products: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 • Fourth-order intermodulation products: 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1 • Fifth-order intermodulation products: 3 x fIN1 - 2 x fIN2, 3 x fIN2-2 x fIN1, 3 x fIN1+2 x fIN2, 3 x fIN2 + 2 x fIN1 Full-Power Bandwidth A large -1dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. The -3dB-point is defined as full-power input bandwidth frequency of the ADC. ______________________________________________________________________________________ 17 MAX1213 Static Parameter Definitions Noise Power Ratio (NPR) AVCC 1 AGND 2 REFIO 63 62 61 60 59 58 D9P D9N D10N 57 56 55 54 53 52 51 D8P 50 D8N 3 49 D7P REFADJ 4 48 D7N AGND 5 47 D6P AVCC 6 46 D6N AGND 7 45 OGND INP 8 44 OVCC INN 9 43 DCLKP AGND 10 42 DCLKN AVCC 11 41 OVCC AVCC 12 40 D5P AVCC 13 39 D5N D4P EP MAX1213 AVCC 14 38 AGND 15 37 D4N AGND 16 36 D3P 35 D3N CLKDIV 17 QFN ______________________________________________________________________________________ D2P D2N D1P D1N D0P D0N OVCC OVCC AVCC OGND AGND CLKN CLKP AGND 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Applications that require lower resolution and/or higher speed can refer to other family members of the MAX1213. Adjusting an application to a lower resolution has been simplified by maintaining an identical pinout for all members of this high-speed family. See the Pin-Compatible Versions table for a selection of different resolution and speed grades. 18 D10P D11N D11P ORN ORP OVCC OGND AVCC 67 66 65 64 AVCC AGND 68 AVCC AGND AGND T/B TOP VIEW AVCC Pin-Compatible Lower Speed/Resolution Versions Pin Configuration AGND NPR is commonly used to characterize the return path of cable systems where the signals are typically individual quadrature amplitude-modulated (QAM) carriers with a frequency spectrum similar to noise. Numerous such carriers are operated in a continuous spectrum, generating a noise-like signal, which covers a relatively broad bandwidth. To test the MAX1213 for NPR, a “noise-like” signal is passed through a high-order bandpass filter to produce an approximately square spectral pedestal of noise with about the same bandwidth as the signals being simulated. Following the bandpass filter, the signal is passed through a narrow band-reject filter to produce a deep notch at the center of the noise pedestal. Finally, this signal is applied to the MAX1213 and its digitized results analyzed. The RMS noise power of the signal inside the notch is compared with the RMS noise level outside the notch using an FFT. Note that the NPR test requires sufficiently long data records to guarantee a suitable number of samples inside the notch. NPR for the MAX1213 was determined for 50MHz noise bandwidth signals, simulating a typical cable signal environment (see the Typical Operating Characteristics for test details and results) with a notch frequency of 28.8MHz. AGND MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications 1.8V, 12-Bit, 170Msps ADC for Broadband Applications 68L QFN.EPS For the MAX1213, the package code is G6800-4. PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 ______________________________________________________________________________________ 19 MAX1213 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX1213 1.8V, 12-Bit, 170Msps ADC for Broadband Applications Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 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