MAXIM MAX101

19-0296; Rev 0; 8/94
UAL
N
KIT MA
ATION
EVALU
BLE
A
IL
A
V
A
500Msps, 8-Bit ADC with Track/Hold
____________________________Features
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
500Msps Conversion Rate
7.0 Effective Bits Typical at 250MHz
1.2GHz Analog Input Bandwidth
Less than ±1/2LSB INL
50Ω Differential or Single-Ended Inputs
±270mV Input Signal Range
Ratiometric Reference Inputs
Dual Latched Output Data Paths
Low Error Rate, Less than 10-15 Metastable States
84-Pin Ceramic Flat Pack
________________________Applications
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Signal Processing
High-Energy Physics
Communications
______________Ordering Information
PART
MAX101CFR*
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
84 Ceramic Flat Pack
(with heatsink)
*Contact factory for 84-pin ceramic flat pack without heatsink.
_________________________________________________________Functional Diagram
VART
VARTS
VARBS
VARB
MAX101
8
AIN+
FLASH CONVERTER
(8 -BIT)
AINTRACK
AND
HOLD
STROBE
L
A
T
C
H
E
S
8
ADATA
B
U
F
F
E
R
STROBE
DCLK
DCLK
CLK
FLASH CONVERTER
(8 -BIT)
CLK
TRK1
TRK1
PHADJ VBRT
VBRTS
8
VBRBS
VBRB
L
A
T
C
H
E
S
8
BDATA
________________________________________________________________ Maxim Integrated Products
Call toll free 1-800-998-8800 for free literature.
1
MAX101
_______________General Description
The MAX101 ECL-compatible, 500Msps, 8-bit analogto-digital converter (ADC) allows accurate digitizing of
analog signals from DC to 250MHz (Nyquist frequency). Dual monolithic converters, driven by the track/hold
(T/H), operate on opposite clock edges (time interleaved). Designed with Maxim’s proprietary advanced
bipolar processes, the MAX101 contains a high-performance T/H amplifier and two quantizers in an 84-pin
ceramic flat pack.
The innovative design of the internal T/H assures an
exceptionally wide 1.2GHz input bandwidth and aperture delay uncertainty of less than 2ps, resulting in a
high 7.0 effective bits at the Nyquist frequency. Special
comparator output design and decoding circuitry
reduce out-of-sequence code errors. The probability of
erroneous codes due to metastable states is reduced to
less than 1 error per 1015 clock cycles. And, unlike
other ADCs that can have errors resulting in false fullscale or zero-scale outputs, the MAX101 keeps the error
magnitude to less than 1LSB.
The analog input is designed for either differential or
single-ended use with a ±270mV range. Sense pins for
the reference input allow full-scale calibration of the
input range or facilitate ratiometric use.
Phase adjustment is available to adjust the relative
sampling of the converter halves for optimizing converter performance. Input clock phasing is also available
for interleaving several MAX101s for higher effective
sampling rates.
MAX101
500Msps, 8-Bit ADC with Track/Hold
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
VCC ...........................................................................0V to +7V
VEE .............................................................................-7V to 0V
VCC - VEE .........................................................................+12V
Analog Input Voltage .............................................................±2V
Reference Voltage (VART, VBRT)...........................-0.3V to +1.5V
Reference Voltage (VARB, VBRB) ..........................-1.5V to +0.3V
Clock Input Voltage (VIH, VIL) .....................................-2.3V to 0V
DIV10 Input Voltage (VIH, VIL).......................................VEE to 0V
Output Current, (IOmax)
TJ <100°C .......................................................................14mA
100°C < TJ <125°C.........................................................12mA
Operating Temperature Range...............................0°C to +70°C
Operating Junction Temperature (Note 2)............0°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+250°C
Note 1: The digital control inputs are diode protected. However, limited protection is provided on other pins. Permanent damage
may occur on unconnected units under high-energy electrostatic fields. Keep unused units in supplied conductive carrier or
shunt the terminals together.
Note 2: Typical thermal resistance, junction-to-case RθJC = 5°C/W and thermal resistance, junction to ambient (MAX101CFR)
RθJA =12°C/W, if 200 lineal ft/min airflow is provided. See Package Information.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 1.02V, VARB, VBRB = -1.02V, TA = +25°C, unless otherwise noted.
TMIN to TMAX = 0°C to +70°C. Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
Integral Nonlinearity (Note 4)
INL
AData, BData
Differential Nonlinearity
DNL
AData, BData,
no missing codes
TA = +25°C
TA = TMIN to TMAX
TA = +25°C
TA = TMIN to TMAX
fCLK = 500MHz,
VIN = 95% full scale
(Note 5)
fAIN = 10MHz
fAIN = 125MHz
fAIN = 250MHz
Bits
±0.50
±0.75
±0.75
±0.85
LSB
LSB
DYNAMIC SPECIFICATIONS
Effective Bits
Signal-to-Noise Ratio
Maximum Conversion Rate
Analog Input Bandwidth
Aperture Width
Aperture Jitter
ANALOG INPUT
ENOB
SNR
fCLK
BW3dB
tAW
tAJ
Input Voltage Range
VIN
Input Offset Voltage
Least Significant Bit Size
Input Resistance
VIO
LSB
RI
Input Resistance
Temperature Coefficient
2
6.7
fAIN = 125MHz, fCLK = 500MHz,
VIN = 95% full scale (Note 6)
(Note 7)
Full scale
Zero scale
AIN+, AIN-, TA = TMIN to TMAX
TA = TMIN to TMAX
AIN+, AIN-, to GND
Bits
44.5
dB
1.2
270
2
Msps
GHz
ps
ps
500
Figure 4
Figure 4
AIN+ to AIN-, Table 2,
TA = TMIN to TMAX
7.6
7.1
7.0
230
-305
-17
1.8
49
315
-215
32
2.5
51
0.008
_______________________________________________________________________________________
mV
mV
mV
Ω
Ω/°C
500Msps, 8-Bit ADC with Track/Hold
MAX101
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 1.02V, VARB, VBRB = -1.02V, TA = +25°C, unless otherwise noted.
TMIN to TMAX = 0°C to +70°C. Note 3)
PARAMETER
REFERENCE INPUT
Reference String Resistance
SYMBOL
RREF
CONDITIONS
VART to VARB
MIN
TYP
100
Reference String Resistance
Temperature Coefficient
MAX
175
UNITS
Ω
Ω/°C
0.02
LOGIC INPUTS
Digital Input Low Voltage
VIL
CLK, CLK
TA = TMIN to TMAX
Digital Input High Voltage
VIH
CLK, CLK
TA = TMIN to TMAX
-1.1
Digital Input High Current
IIH
DIV10 = 0V
TA = TMIN to TMAX
1.1
Input Bias Current
IB
PHADJ = 0V
CLK, CLK = -0.8V
(no termination)
Clock Input Bias Current
ICLK
-1.50
V
V
3.1
mA
TA = TMIN to TMAX
40
µA
TA = TMIN to TMAX
50
µA
LOGIC OUTPUTS (Note 8)
AData, BData
Digital Output Low Voltage
VOL
Digital Output Low Voltage
DCLK, DCLK
Digital Output High Voltage
AData, BData,
DCLK, DCLK
Digital Output Voltage
VOH
VOH - VOL DCLK, DCLK
TA = +25°C
-1.95
TA = TMIN to TMAX
-1.95
-1.60
-1.50
TA = +25°C
-1.3
-1.00
TA = TMIN to TMAX
-1.4
-0.9
TA = +25°C
-1.02
-0.70
TA = TMIN to TMAX
-1.10
-0.60
TA = TMIN to TMAX
275
445
TA = +25°C
550
V
V
mV
POWER REQUIREMENTS
Positive Supply Current
IVCC
VCC = 5.0V
Negative Supply Current
IVEE
VEE = -5.2V
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
CMRR
PSRR
VINCM = ±0.5V
VCC(nom) = ±0.25V
VEE(nom) = ±0.25V
765
TA = TMIN to TMAX
TA = +25°C
-935
TA = TMIN to TMAX
-975
TA = TMIN to TMAX
35
TA = TMIN to TMAX
1065
1130
40
40
-750
-525
mA
mA
dB
dB
_______________________________________________________________________________________
3
TIMING CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 1.02V, VARB, VBRB = -1.02V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Clock Pulse Width Low
Clock Pulse Width High
tPWL
tPWH
CLK, CLK
CLK, CLK
0.9
0.9
CLK to DCLK
Propagation Delay
tPD1
DIV10 = 0, Figures 1, 2
1.2
DCLK to A/BData
Propagation Delay
tPD2
DIV10 = 0, Figures 1, 2
0.7
Rise Time
tR
20% to 80%
Fall Time
tF
20% to 80%
Pipeline Delay
(Latency)
See Figures 2, 3
and Table 1
tNPD
TYP
DCLK
DATA
DCLK
DATA
MAX
UNITS
2.5
2.5
ns
ns
2.3
3.4
ns
1.3
1.8
ns
400
850
400
700
Divide-by-1 mode
15
ps
ps
15
Clock
Cycles
All devices are 100% production tested at +25°C and are guaranteed by design for TA = TMIN to TMAX as specified.
Deviation from best-fit straight line. See Integral Nonlinearity section.
See the Signal-to-Noise Ratio and Effective Bits section in the Detailed Description of Specifications.
SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Clock pulse width minimum requirements tPWL and tPWH must be observed to achieve stated performance.
Outputs terminated through 100Ω to -2.0V.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
__________________________________________Typical Operating Characteristics
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 1.02V, VARB, VBRB = -1.02V, TA = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.50
0.50
0.25
DNL (LSBs)
0.25
0
-0.25
-0.50
0
-0.25
-0.50
-0.75
-0.75
0
64
128
OUTPUT CODE
4
MAX101 TOC2
0.75
MAX101 TOC1
0.75
INL (LSBs)
MAX101
500Msps, 8-Bit ADC with Track/Hold
192
256
0
64
128
OUTPUT CODE
_______________________________________________________________________________________
192
256
500Msps, 8-Bit ADC with Track/Hold
FFT PLOT
(fAIN = 251.4462MHz)
-30
-30
(dB)
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
0
50
25
75
100
125
0
25
12.5
(MHz)
37.5
50
62.5
(MHz)
EFFECTIVE BITS vs. ANALOG INPUT
FREQUENCY (fAIN)
(fCLK = 500MHz, VIN = 95% FS)
EFFECTIVE BITS vs. CLOCK
FREQUENCY (fCLK)
(fAIN = 500MHz, VIN = 95% FS)
EFFECTIVE BITS
7
6
MAX110 TOC6
8
MAX110 TOC5
8
EFFECTIVE BITS
(dB)
fCLK = 250MHz,
SER = -47.2dB,
NOISE FLOOR = -70.5dB,
SPURIOUS = -61.8dB
-10
-20
-40
MAX101 TOC4
fCLK = 500MHz,
SER = -44.5dB,
NOISE FLOOR = -67.3dB,
SPURIOUS = -58.2dB
-10
-20
0
MAX101 TOC3
0
FFT PLOT
(fAIN = 10.4462MHz)
7
6
0
50
100
150
200
fAIN (MHz)
250
300
0
100
200
300
400
fCLK (MHz)
500
600
_______________________________________________________________________________________
5
MAX101
____________________________Typical Operating Characteristics (continued)
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 1.02V, VARB, VBRB = -1.02V, TA = +25°C, unless otherwise noted.)
____________________________Typical Operating Characteristics (continued)
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 1.02V, VARB, VBRB = -1.02V, TA = +25°C, unless otherwise noted.)
DATA CLOCK (DCLK)
RISE TIME (526ps), DIV10 = OPEN
100mV/div
-550mV
100mV/div
5.2ns
-1.55V
-4.18ns
BDATA FALL TIME (714ps),
DIV10 = OPEN
BDATA RISE TIME (855ps),
DIV10 = OPEN
6
-825mV
100mV/div
100mV/div
-1.825V
-4.98ns
5.2ns
MAX101 TOC10
-1.55V
-4.18ns
-825mV
MAX101 TOC8
MAX101 TOC7
-550mV
DATA CLOCK (DCLK) FALL TIME
(352ps), DIV10 = OPEN
MAX101 TOC9
MAX101
500Msps, 8-Bit ADC with Track/Hold
5.02ns
-1.825V
-4.98ns
_______________________________________________________________________________________
5.02ns
500Msps, 8-Bit ADC with Track/Hold
PIN
NAME
1
PAD
Internal connection, leave open.
FUNCTION
2, 62
CLK
3, 61
CLK
Complementary Differential Clock Inputs. Can be driven from standard 10KH ECL with the following
considerations: Internally, pins 2, 62 and 3, 61 are the ends of a 50Ω transmission line. Either end
can be driven with the other end terminated with 50Ω to -2V. See Typical Operating Circuit.
4, 7, 15, 18,
24, 27, 30,
34, 37, 40,
46, 49, 57,
60, 64, 67,
68, 70, 71,
74, 77, 78,
79, 82, 84
GND
Power-Supply Ground
5, 59
TRK1
6, 58
TRK1
8, 21, 43,
56, 81
VCC
Positive Power Supply, +5V ±5% nominal
Phasing inputs (normally left open). See Applications Information section.
9
VBRB
“B” side negative reference voltage input (Note 9)
10
VBRBS
“B” side negative reference voltage sense (Note 9)
11
TP4
Internal connection, leave pin open.
12
TP3
Internal connection, leave pin open.
13
VBRTS
“B” side positive reference voltage sense (Note 9)
14
VBRT
“B” side positive reference voltage input (Note 9)
16, 48, 63
N.C.
No Connect—no internal connection to these pins.
29
SUB
Circuit Substrate contact. This pin must be connected to VEE.
31
DCLK
33
DCLK
32, 69, 80
VEE
35
DIV10
36, 38, 39,
41, 42, 44,
45, 47
A7–A0
28, 26, 25,
23, 22, 20,
19, 17
B7–B0
Complementary Differential Clock Outputs. Used to synchronize following circuitry: Outputs A0–A7
are valid after DCLK’s rising edge. B0–B7 output data are valid after DCLK’s falling edge (see Figure 1
for output timing information).
Negative Power Supply, -5.2V ±5% nominal
Divide by 10 mode. Leave open for normal operation. Selects test mode when grounded.
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to ECL logic swings and drive 100Ω transmission lines. Terminate with 100Ω to -2V
(120Ω for Tj > +100°C). See Figures 1–3.
_______________________________________________________________________________________
7
MAX101
______________________________________________________________Pin Description
MAX101
500Msps, 8-Bit ADC with Track/Hold
_________________________________________________Pin Description (continued)
PIN
NAME
FUNCTION
50
VART
“A” side positive reference voltage input (Note 9)
51
VARTS
“A” side positive reference voltage sense (Note 9)
52
TP1
Internal connection, leave pin open.
53
TP2
Internal connection, leave pin open.
54
VARBS
“A” side negative reference voltage sense (Note 9)
55
VARB
“A” side negative reference voltage input (Note 9)
65
TP5
Internal connection, leave pin open.
66
TP6
Internal connection, leave pin open.
72, 73
AIN+
75, 76
AIN-
83
PHADJ
Analog Inputs, internally terminated with 50Ω to ground. Full-scale linear input range is approximately
±270mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
Phase adjustment for T/H. Normally connected to ground. A phase adjustment of approximately ±18ps
can be made by varying this pin’s bias point to optimize interleaving between sides A and B (Note 10).
VART, VARB, VBRT, and VBRB should be adjusted separately from a well bypassed reference circuit to ensure proper
amplitude and offset matching. The sense connections to each of these terminals allows precision setting of the reference
voltage. The reference ladder is similar for both converter halves (check electrical section for values). Any noise on these
terminals will severely reduce overall performance.
Note 10: Good results are obtained by connecting the PHADJ input to ground. Improve performance by applying a voltage between
±1.25V to this input. The time that the “A” T/H bridge samples relative to the time that the “B” T/H bridge samples can be
varied through a ±18ps range.
Note 9:
CLK
CLK
tPWH
tPWL
DCLK
DCLK
tPD1
ADATA
BDATA
tPD2
tPD2
Figure 1. Output Timing, Normal Mode, DIV10 = OPEN
8
_______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
N–1
N
N+1
N+2
+14
0
+15
1
+16
MAX101
CLK
+17
7
8
DCLK
ADATA
N-1
BDATA
N-2
N+1
N
N+3
N+2
tPD2
tPD2
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING.
Figure 2. Output Timing, Clock to Data, Normal Mode DIV10 = OPEN
CLK
N
N+1
N+2
N+3
+15
+16
+17
DCLK
ADATA
N
BDATA
N+5
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING.
Figure 3. Output Timing, Test Mode (DIV10 = GND)
_______________________________________________________________________________________
9
MAX101
500Msps, 8-Bit ADC with Track/Hold
______Definitions of Specifications
Signal-to Noise Ratio and Effective Bits
Signal-to-noise ratio (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency to the
RMS amplitude of all other analog-to-digital (A/D) output signals. The theoretical minimum A/D noise is
caused by quantization error and is a direct result of
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N
is the number of effective bits of resolution. Therefore, a
perfect 8-bit ADC can do no better than 50dB. The FFT
plots in the Typical Operating Characteristics show the
output level in various spectral bands.
Effective bits is calculated from a digital record taken
from the ADC under test. The quantization error of the
ideal converter equals the total error of the device. In
addition to ideal quantization error, other sources of
error include all DC and AC nonlinearities, clock and
aperture jitter, missing output codes, and noise. Noise
on references and supplies also degrades effective bits
performance.
The ADC’s input is a sine wave filtered with an antialiasing filter to remove any harmonic content. The digital record taken from this signal is compared against a
mathematically generated sine wave. DC offsets,
phase, and amplitudes of the mathematical model are
adjusted until a best-fit sine wave is found. After subtracting this sine wave from the digital record, the residual error remains. The rms value of the error is applied
in the following equation to yield the ADC’s effective
bits.
Effective bits = N - log2
measured rms error
—————————ideal rms error
CLK
CLK
tAW
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
TRACK
HOLD
TRACK
T/H
APERTURE DELAY (tAD)
APERTURE WIDTH (tAW)
APERTURE JITTER (tAJ)
Figure 4. T/H Aperture Timing
typical converters can be incorrect, including false fullor zero-scale output. The MAX101’s unique design
reduces the magnitude of this type of error to 1LSB,
and reduces the probability of the error occurring to
less than one in every 1015 clock cycles. If the MAX101
were operated at 500MHz, 24 hours a day, this would
translate to less than one metastable state error every
46 days.
Integral Nonlinearity
where N is the resolution of the converter. In this case,
N = 8.
The worst-case error for any device will be at the converter’s maximum clock rate with the analog input near
the Nyquist rate (one-half the input clock rate).
Integral nonlinearity is the deviation of the transfer function from a reference line measured in fractions of 1LSB
using a “best straight line” determined by a least
square curve fit.
Aperture Width and Jitter
Differential nonlinearity (DNL) is the difference between
the measured LSB step and an ideal LSB step size
between adjacent code transitions. DNL is expressed
in LSBs and is calculated using the following equation:
[VMEAS - (VMEAS - 1)] - LSB
DNL(LSB) = ——————————————LSB
where VMEAS - 1 is the measured value of the previous
code.
A DNL specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Aperture width is the time the T/H circuit takes to disconnect the hold capacitor from the input circuit (i.e., to
turn off the sampling bridge and put the T/H in hold
mode). Aperture jitter is the sample-to-sample variation
in aperture delay (Figure 4).
Error Rates
Errors resulting from metastable states may occur when
the analog input voltage, at the time the sample is
taken, falls close to the decision point for any one of the
input comparators. The resulting output code for many
10
Differential Nonlinearity
______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
Converter Operation
The parallel or “flash” architecture used by the MAX101
provides the fastest multibit conversion of all common
integrated ADC designs. The basic element of a flash, as
with all other ADC architectures, is the comparator, which
has a positive input, a negative input, and an output. If
the voltage at the positive input is higher than the negative input (connected to a reference), the output will be
high. If the positive input voltage is lower than the reference, the output will be low. A typical n-bit flash consists
of 2n - 1 comparators with negative inputs evenly spaced
at 1LSB increments from the bottom to the top of the reference ladder. For n = 8, there are 255 comparators.
For any input voltage, all the comparators with negative
inputs connected to the reference ladder below the
input voltage will have outputs of 1 and all comparators
with negative inputs above the input voltage will have
outputs of 0. Decode logic is provided to convert this
information into a parallel n-bit digital word (the output)
corresponding to the number of LSBs (minus 1) that the
input voltage is above the bottom of the ladder.
The comparators contain latch circuitry and are
clocked. This allows the comparators to function as
described previously when, for example, clock is low.
When clock goes high (samples) the comparator will
latch and hold its state until the clock goes low again.
The MAX101 uses a monolithic dual interleaved parallel
quantizer chip with two separate 8-bit converters.
These converters deliver results to the A and B output
latches on alternate negative edges of the input clock.
Track/Hold
As with all ADCs, if the input waveform is changing
rapidly during the conversion the effective bits and
SNR will decrease. The MAX101 has an internal
track/hold (T/H) that increases attainable effective bits
performance and allows more accurate capture of analog data at high conversion rates.
The internal T/H circuit provides two important circuit
functions for the MAX101:
1) Its nominal voltage gain of 4 reduces the input driving signal to ±270mV differential (assuming a
±1.02V reference).
2) It provides a differential 50Ω input that allows easy
interface to the MAX101.
Table 1. Output Mode Control
DIV10
DCLK*
(MHz)
MODE
DESCRIPTION
OPEN
250
Normal
Divide
by 2
AData and BData valid on opposite DCLK edges (AData on rise,
BData on fall).
50
Test
Divide
by 10
AData and BData valid on opposite DCLK edges (AData on rise,
BData on fall). Data sampled at
input CLK rate but 4 out of every
5 samples discarded.
GND
* Input clocks (CLK, CLK) = 500MHz for all above combinations. In
all modes, the output clock DCLK will be a 50% duty cycle signal.
Data Flow
The MAX101’s internal T/H amplifier samples the analog
input voltage for the ADC to convert. The T/H is split into
two sections that operate on alternate negative clock
edges. The input clock, CLK, is conditioned by the T/H
and fed to the A/D section. The output clock, DCLK,
used for output data timing, will be divided by 2 or 10
from the input clock, CLK (Table 1). This would result in
an output data rate of 250Mbps on each output port in
normal mode and 50Mbps in test mode. The differential
inputs, AIN+ and AIN-, are tracked continuously
between data samples. When a negative strobe edge is
sensed, one-half of the T/H goes into the hold mode
(Figure 4). When the strobe is low, the just-acquired
sample is presented to the ADC’s input comparators.
Internal processing of the sampled data takes an additional 15 clock cycles before it is available at the outputs, AData and BData. See Figures 1–3 for timing.
__________Applications Information
Analog Input Ranges
Although the normal operating range is ±270mV, the
MAX101 can be operated with up to ±500mV on each
input with respect to ground. This extended input level
includes the analog signal and any DC common-mode
voltage.
To obtain full-scale digital output with differential
input drive, a nominal +270mV must be applied
between AIN+ and AIN-. That is, AIN+ = +135mV and
AIN- = -135mV (with no DC offset). Mid-scale digital
output code occurs when there is no voltage difference
across the analog inputs. Zero-scale digital output
code, with differential -270mV drive, occurs when AIN+
= -135mV and AIN- = +135mV. Table 2 shows how the
output of the converter stays at all ones (full scale)
when over-ranged or all zeros (zero scale) when underranged.
______________________________________________________________________________________
11
MAX101
_______________Detailed Description
MAX101
500Msps, 8-Bit ADC with Track/Hold
Table 2. Input Voltage Range
INPUT
Differential
Single
Ended
AIN+
(mV)
AIN(mV)
OUTPUT
CODE
MSB to
LSB
+135
-135
11111111
full scale
0
0
10000000
mid scale
-135
+135
+270
0
11111111
full scale
0
0
10000000
mid scale
-270
0
0 0 0 0 0 0 0 0 zero scale
0 0 0 0 0 0 0 0 zero scale
POSITIVE
REFERENCE
VART
PARASITIC
RESISTANCE
VARTS
* An offset VIO, as specified in the DC electrical paramters, will be
present at the input. Compensate for this offset by adjusting the
reference voltage. Offsets may be different between side A and
side B.
R
TO
COMPARATORS
For single-ended operation:
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are terminated internally with 50Ω to analog ground.)
2) Drive the other input with a ±270mV + offset to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
R
R
Reference
The ADC’s reference resistor is a Kelvin-sensed, resistor string that sets the ADC’s LSB size and dynamic
operating range. Normally, the top and bottom of this
string are driven with an external buffer amplifier. It will
need to supply approximately 21mA due to the 100Ω
minimum resistor string impedance. A ±1.02V reference voltage is normally applied to inputs VART, VBRT,
VARB, and VBRB. This reference voltage can be adjusted up to ±1.2V to accommodate extended input
requirements (accuracy specifications are guaranteed
with ±1.02V references). The reference inputs VARTS,
VARBS, VBRTS, and VBRBS allow Kelvin sensing of the
applied voltages to increase precision.
An RC network at the ADC’s reference terminals is
needed for best performance. This network consists of
a 33Ω resistor connected in series with the buffer output that drives the reference. A 0.47µF capacitor must
be connected near the resistor at the buffer’s output
(see Typical Operating Circuit ). This resistor and
capacitor combination should be located within 0.5
inches of the MAX101 package. Any noise on these
pins will directly affect the code uncertainty and
degrade the ADC’s effective bits performance.
R
R
VARBS
PARASITIC
RESISTANCE
VARB
NEGATIVE
REFERENCE
Figure 5. Reference Ladder
12
______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
Layout, Grounding, and Power Supplies
A +5V ±5% supply as well as a -5.2V ±5% supply is
needed for proper operation. Bypass the VEE and VCC
supply pins to GND with high-quality 0.1µF and 0.001µF
ceramic capacitors located as close to the package as
possible. Connect all ground pins to a ground plane to
optimize noise immunity and highest device accuracy.
Output Mode Control (DIV10)
When DIV10 is grounded, it enables the test mode,
where the input incoming clock is divided by ten. This
reduces the output data and clock rates by a factor of
5, allowing the output clock duty cycle to remain at
50%. The clock to output phasing remains the same
and four out of every five sampled input values are discarded.
When left open, this input (DIV10) is pulled low by internal circuitry and the converter functions in its normal
mode.
Phase Adjust
This control pin affects the point in time that one-half of
the converter samples the input signal relative to the
other half. PHADJ is normally connected to ground (0V),
but can be adjusted over a ±1.25V range that typically
provides a ±18ps adjustment between the “A” side T/H
bridge strobe and the “B” side T/H bridge strobe.
Input Clock Phasing (TRK1, TRK1)
At power-up, the clock edge from which AData and
BData are synchronized is undetermined. The converter can work from a specific input clock edge, as
described in the following paragraph.
TRK1 and TRK1 are differential inputs that are used in
addition to the normal input clock (CLK) to set data
phasing. A signal at one-half the input clock rate with
the proper setup and hold times (setup and hold typically 300ps) is applied to these inputs. Choose AData
by applying a logic “1” to TRK1 (“0” to TRK1) before
CLK’s negative transition. Choose BData by applying a
logic “0” at CLK’s negative edge (“1” to TRK1). In this
manner, several MAX101s can be interleaved to obtain
faster effective sampling rates. Voltages at the TRK1
input between ±50mV are interpreted as logic “1” and
voltages between -350mV and -500mV are interpreted
as logic “0”.
______________________________________________________________________________________
13
MAX101
CLK and DCLK
All input and output clock signals are differential. The
input clocks, CLK and CLK, are the primary timing signals for the MAX101. CLK (pins 2, 62) and CLK (pins 3,
61) are fed to the internal circuitry through an internal
50Ω transmission line. One set of CLK, CLK inputs
should be driven and the other pair terminated by 50Ω
to -2V. Either set of inputs can be used as the driven
inputs (input lines are balanced) for easy circuit connection. A minimum pulse width (tPWL) is required for
CLK and CLK (Figures 1–3).
For best performance and consistent results, use a lowphase-jitter clock source for CLK and CLK. Phase jitter
larger than 2ps from the input clock source reduces the
converter’s effective bits performance and causes
inconsistent results. The clock supplied to the MAX101
is internally divided by two, reshaped, and buffered.
This divided clock becomes the internal signal used as
strobes for the converters.
DCLK and DCLK are output clock signals derived from
the input clocks and are used for external timing of the
AData and BData outputs. (AData is valid after the rising edge of DCLK and BData is valid after the falling
edge.) They are fixed at one-half the rate of the input
clocks in normal mode (Table 1). The MAX101 is characterized to work with 500MHz maximum input clock
frequencies. See Typical Operating Circuit.
MAX101
500Msps, 8-Bit ADC with Track/Hold
___________________________________________________Typical Operating Circuit
0.01µF
+5V
0.1µF
1
+VS
VOUT
GND
MX580LH
3
2
2.5V
0.01µF
0.001µF
1.5k
MC100E151
1/2 MAX412
20Ω
500Ω
1.2k
0.47µF
0.01µF
8, 21, 43, 56, 81
33Ω
50
51
50Ω
54
0.01µF
1.5k
20k
1/2 MAX412
20Ω
33Ω
500Ω
0.47µF
1.2k
WATKINS-JOHNSON
SMRA 89-1 (2x)
VCC
D
Q
>
Q
D
Q
>
Q
CMPSH-3
50Ω
20k
VART
55
VARTS
8
ADATA
VARBS
VARB
CMPSH-3
10k
MAX101
72, 73
DCLK
AIN+
DCLK
75, 76
33
31
AIN-
1.5k
1/2 MAX412
20Ω
500Ω
1.2k
0.47µF
0.01µF
33Ω
13
50Ω
10
0.01µF
1.5k
20k
1/2 MAX412
20Ω
33Ω
500Ω
0.47µF
1.2k
VBRT
CMPSH-3
50Ω
20k
MC100E151
14
9
VBRBS
8
BDATA
VBRB
CMPSH-3
+1.25V
62
-2V
2
PHADJ
83
50Ω
-2V
3
PHASE
CLK
-1.25V
61
MC100E116
CLK
GND
4, 7, 15, 18, 24, 27, 30, 34,
37, 40, 46, 49, 57, 60, 64, 67, 68,
70, 71, 74, 77, 78, 79, 82, 84
SUB
29
VEE
32, 69, 80
0.001µF
0.1µF
-5.2V
14
Q
Q
D
Q
>
Q
VBRTS
10k
50Ω
D
>
______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
VEE
GND
GND
TP6
TP5
GND
68
67
66
65
64
GND
GND
AIN+
AIN+
69
70
71
72
73
AIN-
AIN-
GND
GND
GND
VEE
VCC
GND
GND
GND
74
75
76
77
78
79
80
81
82
83
84
PHADJ
TOP VIEW
PAD
1
63 N.C.
CLK
2
62 CLK
CLK
3
61 CLK
GND
4
60 GND
TRK1
5
59
TRK1
TRK1
6
58
TRK1
GND
7
57
GND
VCC
8
56
VCC
VBRB
9
55
VARB
VBRBS
10
54
VARBS
TP4
11
53 TP2
TP3
12
52 TP1
VBRTS
13
51 VARTS
VBRT
14
50 VART
GND
15
49
GND
N.C.
16
48
N.C.
B0
17
47
A0
GND
18
46
GND
B1
19
45
A1
B2
20
44
A2
VCC
21
43
VCC
38
39
40
41
42
A6
A5
GND
A4
A3
37
36
A7
GND
35
DIV10
33
34
32
VEE
GND
31
DCLK
DCLK
30
GND
29
SUB
28
B6
B7
26
B5
27
25
GND
GND
24
B4
22
B3
23
MAX101
Ceramic Flat Pack
______________________________________________________________________________________
15
MAX101
____________________________________________________________Pin Configuration
________________________________________________________Package Information
PIN FIN HEATSINK
FORCED CONVECTION PARAMETERS
MAX100-insertB
23
21
19
θJA (°C/W)
MAX101
500Msps, 8-Bit ADC with Track/Hold
17
15
0° Angle*
13
11
45° Angle*
9
7
0
100
200
300
400
500
VELOCITY (ft /min)
*DIRECTION OF AIRFLOW ACROSS HEATSINK
E1
E
E2
e
S
0.060±.005(7x)
D1
D
D2
D3
0.075±.020(6x)
EQUAL SPACES
PIN #1
C
MILLIMETERS
MIN
MAX
A
17.272 18.288
A1 1.041 1.270
A2 3.048 3.302
b
0.406 0.508
C
0.228 0.279
D
29.184 29.794
D1 44.196 44.704
D2 25.298 25.502
D3 28.448 28.829
1.270 BSC
e
E
29.184 29.794
E1 44.196 44.704
E2 25.298 25.502
E3 28.194 28.702
S
1.930 2.184
DIM
b
A2 A1
A
5°–6°
INCHES
MIN MAX
0.680 0.720
0.041 0.050
0.120 0.130
0.016 0.020
0.009 0.011
1.149 1.173
1.740 1.760
0.996 1.004
1.120 1.135
0.050 BSC
1.149 1.173
1.740 1.760
0.996 1.004
1.110 1.130
0.076 0.086
84-PIN CERAMIC FLAT
PACK WITH HEAT SINK
0.060±.005
E3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1994 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.