PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features ■ PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ■ Programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and accesses of 32-, 16-, or 8-bit local bus devices ■I 2O compatible messaging unit ■ 3.3 or 5 volt PCI signaling, 5 volt core, low-power CMOS in 208-pin PQFP ■ Two independent programmable DMA channels for local bus memory to/from PCI host bus data transfers ■ Eight programmable FIFOs for zero wait state burst operation ■ PCI to/from local data transfers up to 133MB/sec ■ Local bus runs asynchronously to the PCI bus ■ Eight 32-bit mailbox and two 32-bit doorbell registers ■ Performs Big Endian/Little Endian conversion ■ Upward compatibility with PCI 9060, 9060ES, 9060SD T E C H N O L O G Y ® Flexible Connection to the PCI Bus For add-in card and embedded system designers and integrators alike, the mission is clear: reduce the time to integrate new technology and time to market. Achieving this task requires the latest in I/O technology. PLX Technology, Inc. is committed to providing complete and proven PCI solutions with our PCI 9080 Bus Master I/O Accelerator interface chip. The PLX® PCI 9080 provides a compact, high performance PCI bus master interface with a programmable local bus. Integrating the latest in I/O technology, the PCI 9080 contains an Intelligent I/O (I2O) messaging unit in hardware that allows high performance and compatible software implementations of the I2O bus protocol specification. The highly flexible local bus solution can be configured to directly connect a wide variety of processors, controllers and memory subsystems. Combined with the PCI 9080RDK reference design kits, PCI SDK and I2O software development kits available from PLX, the design-in process is simple and painless with little or no glue logic. Customers are using the PCI 9080 with IBM PowerPC 40x, Motorola MPC850/860, Intel i960C/J/H, Hitachi Super H, MIPS R 3000/4000/5000, NEC V830/831, ARM, Motorola 68XXX, and others. Thoroughly tested and proven, PLX products have become the gold standard of the industry. Leading the way in PCI design, the PCI 9080 provides two intelligent DMA channels with scatter/gather, programmable burst modes, and asynchronous bus clocks to provide the best PCI throughput available. The versatility of the PCI 9080 also allows for a local processor to configure other PCI devices in the system. While the PCI 9080 is capable of keeping up with the most demanding of applications and the latest in technology, upward compatibility with existing PLX PCI I/O accelerators is maintained. The 9080 continues the PLX tradition of providing the highest performance and fully compatible PCI interface solutions. T e c h n i c a l S p e c i fi c a t i o n s Package 208-pin PQFP PCI compliance PCI local bus specification, v. 2. 1 I2O messaging unit PCI extension of the 2OIspecification v.1.5 Interface protocol Direct bus master PCI signaling 3. 3v or 5v Local bus speed 0-40MHz Big/Little Endian conversion Dynamic switching for direct slave, direct master, DMA, and the internal register accesses on the local side PCI Bus Speed 33MHz max PCI host capability Type 0 or Type 1 PCI configuration cycles in direct master mode Mailbox registers Eight 32-bit, accessed from PCI or local bus Doorbell registers Two 32-bit, one from PCI to local bus, one from local bus to PCI bus Unaligned DMA transfer support From any byte boundary Programmable local bus modes Selected through mode pins Mode C 32-bit address/32-bit data, non multiplexed Mode J 32-bit address/32-bit data, multiplexed Mode S 32-bit address/16-bit data, non multiplexed Supported PCI 9080 Internal Block Diagram Internal Registers PCI Config Local Config Run-Time DMA I2O Messaging PCI Bus PCI Bus State Machines PCI Bus Interface & Arbiter Control Logic T E C H N O L O G Y ® PLX Technology, Inc. 390 Potrero Ave. Sunnyvale, CA 94086 USA Tel: 1-800-759-3735 Fax: 1-408-774-2169 Email: [email protected] Web Site: www.plxtech.com FIFOs PCI Initiator (For Direct Master Xfers) Dir. Master Write PCI Target (for Direct Slave Xfers) Dir. Slave Write PCI Initiator (For Ch 1 DMA Xfers) DMA1 PCI/Loc PCI Initiator (For Ch 0 DMA Xfers) DMA0 PCI/Loc I20 Messaging Dir. Master Read Dir. Slave Read DMA1 Loc/PCI DMA0 Loc/PCI DMA EEPROM Initialization Local Bus State Machines Local Slave (for Direct Master Xfers) Local Master (for Direct Master Xfers) Local Master (for Ch 1 DMA Xfers) Local Master (for Ch 0 DMA Xfers) DMA Chaining Local Bus Interface – Select Bus Width 8,16 or 32 bit – Endian Conversion – Select Muxe or non-Muxe Addr/Data Local Bus Serial EEPROM interface Unaligned Xfer Product Ordering Information PCI 9080 PCI to Local Bus Master Chip I2O SDK I2O Software Development Kit for Motorola MPC860 CPU, Intel i960 CPU, IBM PPC 401 CPU PCI SDK PCI Software Development Kit for Motorola MPC860 CPU, Intel i960 CPU, IBM PPC 401 CPU *See PLX web site for latest version and product support information © 1998 by PLX Technology, Inc. All rights reserved. PLX and PLXMon 98 are trademarks of PLX Technology, Inc. which may be regis tered in some jurisdictions. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or regist ered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or specification. 9080-PB-010 9/98 5K