TI TLS2205

SLFS040 – DECEMBER 1993
Single-Chip Voice-Coil Motor Driver and
Spindle-Motor Driver
Precision Dual-Voltage Monitor
Operates From Single 5-V Supply
LinBiCMOS
DL PACKAGE
(TOP VIEW)
SCLK
SDATA
SPSZ
PORN
UV
CPOR
NC
NC
AVCC
VDD
VCMGND
VCMA
SPNGND
SPNGND
SPNGND
SPNGND
VCMB
VCMVCC
AGND
RETOUT
RETSET
NC
RSENP
RSENN
CMPI
CMPO
VIVCM
VCMREF
Technology
Low Power Dissipation
Internal Overtemperature Shutdown
Circuitry
Low-Profile 56-Terminal DL Package and
64-Terminal PM Package Available
4-V Reference Buffer
System Power-On Reset
Monotonic 8-Bit DAC
description
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
44
13
14
15
SUBSTRATE
GROUND
AND
HEAT SINK
43
42
MTRCLK
DVCC
AUXIN
AUXOUT
NC
HU
HV
HW
DGND
U
SPNVCC
SPNSNSR2
SPNGND
SPNGND
SPNGND
SPNGND
SPNSNSR1
V
W
CRET
REFBUF
SPNCOMP
CTS
VPHASE
COMDLY2
COMDLY1
SPNSW
CTDRV
41
16
The TLS2205 is a combination voice-coil and
spindle-motor driver with voltage monitor
40
17
integrated circuit. This circuit is designed for
39
18
small-form-factor, high-performance hard disk
19
38
drives. The TLS2205 integrates a three-phase
37
20
brushless dc motor driver with a linear full-bridge
36
21
voice-coil driver. Additional circuitry is added for
35
22
power-up and power-down sequencing of the
23
34
driver amplifiers used for motor speed control. A
33
24
brake function can be invoked on the spindle
32
25
motor after the head is in a safe landing zone.
31
26
External sense resistors are used for precision
30
27
spindle motor and VCM current monitoring.
28
29
Automatic head retract is provided for voltage or
thermal fault conditions. The TLS2205 operates
NC – No internal connection
with only 5 V of supply voltage and has a
sleep-mode option for low-power applications. All
device functions are controlled from a three-wire serial port. Device packaging is a 56-terminal DL or 64-terminal
PM package. Center pins are tied to the die mount tab for improved heat dissipation on both packages.
Voice-Coil Motor Driver
Spindle-Motor Driver
– 0.4-A MOS H-Bridge Power Amplifier
– No Crossover Distortion
– Precision VCM Control Loop With External Sense
Resistor
– Internal 8-Bit Control DAC With Four Gain Ranges
– Controlled-Velocity Head Retract
– Compensation Adjust Terminals for Bandwidth
Control
– Capability for External Velocity Feedback
– Low rDS(on), 2 Total
– No External Retract Power Supply Isolation
Components Required
–
–
–
–
–
–
–
–
–
–
–
Hall- or Back-EMF Commutation Circuitry
3-Phase Driver With 1.3-A MOS Output
Bipolar or Unipolar Drive Modes
Programmable Frequency-Locked Speed
Control Loop
Programmable Start-Up Current
Linear Spindle Current Control
Low rDS(on), 1.3 Total
Sector Data Tachometer Signal Input
(Optional)
Speed Sense Tachometer Output
Internal Schottky Diodes for Retract Power
Source
Controlled Brake Function
LinBiCMOS is a trademark of Texas Instruments Incorporated.
Copyright
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1993, Texas Instruments Incorporated
1
SLFS040 – DECEMBER 1993
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC
RSENP
RSENN
CMPI
CMPO
VIVCM
VCMREF
CTDRV
SPNSW
COMDLY1
COMDLY2
VPHASE
CTS
SPNCOMP
NC
NC
AVCC
NC
NC
VDD
NC
NC
VCMGND
VCMGND
VCMGND
VCMGND
VCMA
VCMB
VCMVCC
AGND
RETOUT
RETSET
NC
NC
NC
NC
CPOR
UV
PORN
SPSZ
SDATA
SCLK
MTRCLK
DVCC
AUXIN
AUXOUT
HU
HV
PM PACKAGE
(TOP VIEW)
NC – No internal connection
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
HW
DGND
U
U
SPNVCC
SPNSNSR1
SPNGND
SPNGND
SPNGND
SPNGND
SPNSNSR2
V
W
W
CRET
REFBUF
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
6
5
10
54
3
2
Voltage
Monitor
Ref
AUXIN
12
12
2
8-Bit
DAC
G2-4
2
Vdac
Fspn
Speed
Feedback
MUX
Pclk
Fref
Charge
Pump
GS1
GS2
20 k
20 k
10 k
20 k
SCK
Phase
Spnmode
Spnmode
Gain Control
2V
Comm
Vdac
20 k
Down
Up
AWAKE – Bias Enable
GS3
AUX1 – MSB Options Control
AUX0 – LSB Options Control
BEMF GAIN – Gain Switch for Back-EMF Mode
BRAKE – Brake Enable
VCMENA – Enable VCM/B Outputs
SPNMODE – Select Control for SPNCOMP Output
COMM – Commutate Spindle Inverter (Start Mode)
UPOLAR – Select Spindle Unipolar Run Mode
NHALLS – Select Back-EMF Spindle-Commutation Mode
START – Spindle Start Mode
SPNENA – Enable Spindle Power Amps
Port A:
VCM
Driver
8
VCM
Reference
NHphase
Fspn
Fref
Port C:
System Control
Word
Fault
ChargePump
Voltage
Tripler
11
Port B:
Mtr Poles
Spin Speed
#Poles
1/8
12
15 V
53 Auxiliary
Output
MUX
Serial
Port
ID = 0
1/2
Speed Discriminator
8 x 2048 Counts
NOTE: Terminal numbers are for the DL package.
PORN
CPOR
UV
VDD
AUXOUT
AUXIN
SPSZ
SDATA
SCLK
1
MTRCLK
56
functional block diagram
SPNMODE
Upolar
+
_
NHphase
2
Retract
Control
Unipolar-Mode
Center-Tap
Driver
Fault
VCM CurrentSensor Amp
(x 8)
Fault
VCM Power
Amps
(x 5)
4V
Back-EMF
or
Hall
Hphase
Commutation
SpindleControl
Logic
Padv
SpindleControl
Amps
49
50
51
32
31
34
33
45
40
38
39
47
35
30
29
37
21
20
27
24
23
25
26
17
12
28
36
SPNSW
CTDRV
CRET
RETSET
RETOUT
VIVCM
RSENN
CMPI
RSENP
CMPO
VCMB
VCMA
VCMREF
REFBUF
HW
HV
HU
COMDLY2
COMDLY1
CTS
VPHASE
SPNSNSR2
SPNSNSR1
W
V
U
SPNCOMP
SLFS040 – DECEMBER 1993
3
SLFS040 – DECEMBER 1993
Terminal Functions
NAME
TERMINAL
NO.†
I/O
NO.‡
DESCRIPTION
SUBSYSTEM§
AGND
19
14
AUXIN
54
54
AUXOUT
53
53
AV CC
9
1
I
Analog 5-V supply voltage
CMPI
25
20
I
VCM frequency-compensation input
VCM
CMPO
26
21
O
VCM frequency-compensation output
VCM
COMDLY1
31
26
I
Spindle back-EMF commutation delay control input
SPN
COMDLY2
32
27
O
Spindle back-EMF commutation delay control output
SPN
CPOR
6
62
O
Power-on-reset delay capacitor output
VM
CRET
37
34
O
Retract power full-wave-rectifier output
VM
CTDRV
29
24
O
Center-tap pnp drive output
SPN
CTS
34
29
I
Spindle center-tap sense input
SPN
DGND
48
47
DV CC
55
55
I
Logic power supply voltage
HU
51
52
I
Hall-phase U input
SPN
HV
50
51
I
Hall-phase V input
SPN
HW
49
48
I
Hall-phase W input
SPN
MTRCLK
56
56
I
Spindle-motor reference clock input
SPN
PORN
4
60
I/O
Power-on-reset node, open-drain output/reset input
REFBUF
36
33
O
4-V reference
RETOUT
20
15
O
Retract voltage set output
VM
RETSET
21
16
I
Retract voltage set input
VM
RSENN
24
19
I
VCM current-sense negative input
VCM
RSENP
23
18
I
VCM current-sense positive input
VCM
SCLK
1
57
I
Serial input clock
SDATA
2
58
I/O
Serial input/output port
SPNCOMP
35
30
O
Spindle charge-pump filter
SPN
13, 14, 15, 16,
41, 42, 43, 44
39, 40, 41, 42
Spindle ground
SPN
SPNSNSR1
40
43
I
Spindle-sense-resistor kelvin input
SPN
SPNSNSR2
45
38
O
Spindle-sense-resistor output
SPN
SPNSW
30
25
O
Spindle compensation capacitor switch
SPN
SPNVCC
SPSZ
46
44
I
Spindle-driver supply voltage
SPN
3
59
I
Serial I/O port select. When low, data goes into port.
When high, data goes out of port.
U
47
45, 46
O
Spindle-phase U connection
SPNGND
Analog GND
VM
I
Spindle-phase commutate input
SPN
O
Spindle-system status output
SPN
Logic GND
UV
5
61
I
Undervoltage, power-on-reset voltage sense input
† 56-terminal DL package
‡ 64-terminal PM package
§ SPN = spindle, VCM = voice-coil motor, VM = voltage monitor, SP = serial port
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
VM
SP
SP
VM
VCM
SP
SP
SP
SPN
VM
SLFS040 – DECEMBER 1993
Terminal Functions (Continued)
NAME
TERMINAL
NO.†
SUBSYSTEM§
NO.‡
I/O
DESCRIPTION
37
O
Spindle-phase V connection
SPN
V
39
VCMA
12
11
O
VCM driver output A
VCM
VCMB
17
12
O
VCM driver output B
VCM
VCMGND
11
7, 8, 9, 10
VCM driver supply ground
VCM
VCMREF
28
23
VCM voltage reference
VCM
VCMVCC
V DD
18
13
VCM driver supply voltage
VCM
10
4
O
Charge-pump voltage-tripler output
SPN
VIVCM
27
22
O
VCM current-sense output (VCM = 2 V)
VCM
VPHASE
33
28
O
Spindle-back-EMF-phase voltage
SPN
W
38
35, 36
O
Spindle-phase W connection
SPN
O
† 56-terminal DL package
‡ 64-terminal PM package
§ SPN = spindle, VCM = voice-coil motor, VM = voltage monitor, SP = serial port
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)¶
Motor supply voltage, SPNVCC, VCMVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Power supply voltage, AVCC, DVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Maximum voltage at U, V, W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Spindle current at U, V, W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A
VCM current, VCMA, VCMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.41 A
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Thermal resistance (DL package): Junction-to-ambient, R JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . 89 C/W
Junction-to-case, R JC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 14 C/W
Thermal resistance (PM package): Junction-to-ambient, R JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . 71 C/W
Junction-to-case, R JC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 14 C/W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 C to 125 C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 C
¶ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to ground.
2. The device is mounted on a printed-circuit board with 0.22 square inches of copper connected to the package tabs.
PACKAGE
DISSIPATION RATING TABLE
TA 25 C
DERATING FACTOR
POWER RATING
ABOVE TA = 25 C
TA = 70 C
POWER RATING
DL
1125 mW
9.0 mW/ C
720 mW
PM
1125 mW
9.0 mW/ C
720 mW
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
SLFS040 – DECEMBER 1993
recommended operating conditions
Supply voltage, DVCC, AV CC, SPNVCC , VCMVCC
High-level input voltage, VIH
Low-level input voltage, V IL
SCLK,, SDATA,, AUXIN,, MTRCLK,, PORN,,
HU, HV, HW, SPSZ
Setup time, tsu
Level change on SDATA or SPSZ before
SCLK
MIN
NOM
MAX
4.5
5
5.5
V
DV CC+0.3
V
1.5
V
25
ns
MHz
3.5
Speed reference clock frequency
MTRCLK
Speed reference clock duty cycle
Speed reference clock duration
1
12
25%
50%
75%
20.8
41.6
62.5
1
10
25%
50%
75%
25
50
Clock frequency
Clock duty cycle
SCLK
Pulse duration, tw
UNIT
ns
MHz
75
ns
Operating free-air temperature, TA
0
70
C
Operating virtual junction temperature, TJ
0
150
C
MAX
UNIT
electrical characteristics over recommended supply voltage range, TA = 25 C
PARAMETER
TEST CONDITIONS
High-level output voltage, V OH
MIN
IO = 5 A
IO = 5 A
Low-level output voltage, VOL
Operating supply current, ICC
TYP
3.5
V
1.5
DVCC, AV CC
Sleep supply current, ICC
V
20
mA
3
mA
High-level input current, IIH
Low-level input current, IIL
1
A
–1
A
voltage and temperature monitor electrical characteristics over recommended supply voltage
range, TA = 25 C
PARAMETER
TEST CONDITIONS
MIN
Power-on-reset voltage
TYP
Power-on-reset sense bias current
UV
Hysteresis
Internal power-on-reset threshold voltage, AV CC
Power-on-reset timing voltage
CPOR
Power-on-reset timing current
Output voltage
PORN
Output leakage current
Charge-pump voltage-tripler output voltage
See Note 4
UNIT
100
nA
See Note 5
25
mV
4
V
1.21
V
0.4
12
Thermal shutdown hysteresis
13
0.25
20
Voltage monitor accuracy
V
5
IPORN= 1 mA
VDD
Charge-pump voltage-tripler output voltage load regulation
A
0.8
V
10
A
15
V
V/ A
mV
10 %
Thermal shutdown temperature
160
NOTES: 3. PORN reset timing is time reset = CCPOR (VCPOR/ICPOR).
4. V DD can be used to drive external NMOS switches; however, the effective dc loading should be less than 1 A.
6
MAX
1.21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
C
SLFS040 – DECEMBER 1993
voice-coil motor driver electrical characteristics over recommended range of supply voltage,
TA = 25 C
PARAMETER
Total output drain-to-source on-state
resistance, 2 rDS(on)
TEST CONDITIONS
MIN
VCMA, VCMB
Total VCM driver voltage drop
IO = 200 mA
IO = 400 mA
VCM driver voltage drop on retract
ICRET = 50 mA,
TYP
MAX
2
3
RETSET grounded
VCM gain accuracy
UNIT
0.6
V
1.2
V
1.3
V
4%
VCM differential linearity
1.6%
Slew rate
.05
V/ s
V
Control voltage
RETSET
0.7
Pullup resistance
CRET,
RETOUT
20
Output voltage
3.88
Output impedance
REFBUF
f = 10 kHz
4
4.12
Source current
7
Output voltage
VCMREF
Clamp voltage
CRET
V
6.1
1.94
See Note 6
2
2.06
9
mA
V
V
NOTE 5: Optional Zener diode may be required on CRET for filtering narrow voltage spikes
spindle-motor driver electrical characteristics over recommended supply voltage range, TA = 25 C
PARAMETER
Total output drain-to-source on-state resistance,
2 r DS(on)
TEST CONDITIONS
MIN
U, V, W
Source-driver output voltage slew rate
Sink-driver output voltage slew rate
See Note 7
Retract clamp diode forward voltage
U, V, W, CRET
Center tap driver-output saturation resistance
CTDRV
IRETOUT = 50 mA
See Note 8
Speed discriminator count range
See Note 9
Maximum compensation voltage
VCM DAC word = FFhex
Maximum spin compensation voltage
RUN MODE
Minimum spin compensation voltage
1.3
1.6
UNIT
0.07
V/ s
0.07
V/ s
0.5
V
150
8
8333
16384
4
V
5
V
3
SPNCOMP
Charge-pump output current matching
Spindle-driver start current
MAX
0.8
Charge-pump leakage current
Charge-pump output current
TYP
V
5
nA
50
A
1.2
A
1%
U, V, W
NOTES: 6. This slew rate is determined by the percentage of programmed current.
7. CTDRV is an open-drain switch.
8. The typical count (1041) fspindle = 3600 (RPM) at f(MTRCLK) = 1 MHz
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
7
SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
voltage monitor
The TLS2205 voltage-monitor circuit is designed to monitor the voltage of the system’s 5-V power supply. The
device has an internal lockout threshold voltage of 4 V. If the power supply drops below 4 V, an internal fault is
generated and PORN goes low. In applications where a more accurate threshold is desired (greater than 4 V),
an external resistor divider may be connected to UV. If UV is not used, it must be tied to VCC (refer to
Figure 1). The following equations can be used to determine the voltage divider resistor values:
VCC(trip) = 1.21 / [R2 / (R1 + R2)]
where:
UV sense bias current = 10 nA
R1 is resistor connected from VCC to UV
R2 is resistor connected from UV to ground
VCC(trip) > 4 V
Hysteresis at UV 25 mV
Note:
A capacitor (Cuv1) may be considered for short-duration power loss.
The voltage monitor incorporates a deglitch timing delay circuit for applications where PORN is used to reset
the system’s microprocessor. A delay can be implemented on PORN by connecting a capacitor between CPOR
and ground. The reset time (see Figure 2) is calculated by using the following equation:
TR = CCPOR
(VCPOR
ICPOR)
where:
TR = reset time in seconds
CCPOR = capacitor value in farads
VCPOR = 1 V
ICPOR = 5 A
Figure 1 represents the voltage-monitor circuit, and Figure 2 represents the power-on reset (PORN) timing
diagram. The following is a functional overview of the voltage monitor system. (VCC(trip) = 4.2 V).
Time 1: During startup, Comp1 resets the R-S flip-flop and allows the CCPOR capacitor to start charging. As
the supply voltage increases, VCPOR becomes greater than 1.21 V (band-gap voltage), which allows
Comp2 to pull PORN high, disabling the retract control circuit.
Time 2: Time 2 represents the normal run mode. At this time, the R-S flip-flop is reset, CPOR is high, PORN
is high, and the retract control circuit is disabled.
Time 3: An external fault is generated by the microprocessor (or external device) by pulling PORN low. No other
parts of the voltage-monitor circuit are affected.
Time 4: If the system’s supply voltage drops below the preset value (VCC(trip) = 4.2 V, see Figure 2), the
R-S flip-flop is set and allows the capacitor across CPOR to discharge. When VCPOR drops below
1.21 V, PORN is pulled low and a fault is generated that triggers the retract control circuit. Once
VCC(trip) increases above the trip level, the R-S flip-flop is reset and CCPOR begins to charge towards
VCC. After TR seconds, the voltage across CCPOR is greater than 1.21 V and the retract control circuit
is disabled along with PORN being pulled high.
Time 5: Time 5 represents the power down/emergency retract mode. If the system’s supply voltage drops below
the preset value (VCC(trip) = 4.2 V, see Figure 2), the R-S flip-flop is set and allows the capacitor
across CPOR to discharge. When Vcpor drops below 1.21 V, PORN is pulled low and a fault is
generated.
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
VCC
Overtemperature
Fault
Voltage Reference
Vlt ICPORVref
VCC
1.21 V
VCC
Comp1
RDY
+
_
R1
PORN
Comp2
+
_
+
_ 0.25 V
5 A
UV
CPOR
VCPOR
Cuv1
R
R2
Q
VCC
Cpor
S
+
_
45.6 k
20 k
V CC (enable) = 4.1 V
NOTE: Vlt = Low voltage threshold = 0.25 V
VCPOR = Voltage across the power-on-reset capacitor
ICPOR = Current supplied to the CPOR terminal
5 A
Vref = Reference voltage = 1.21 V
Area within the dotted line is internal to the device
Figure 1. Voltage Monitor Circuit
Time 1
AVCC
Time 2
Time 3
Time 4
Time 5
5V
VCC(trip) = 4.2 V
0V
5V
CPOR
Band-Gap Voltage = 1.21 V
0V
5V
PORN
0V
TR = Reset Time
Time
Figure 2. Power-On Reset Timing Diagram
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
9
SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
voice-coil driver system
The voice-coil full-bridge power amplifier is capable of 0.4-A output current and has a total drain-to-source
on-state resistance (2 rDS(on)) of 2 . The voice-coil control system includes a precision current-sense
amplifier that detects load current with a single resistor in series with the voice-coil motor (VCM). The VCM
current is commanded via serial port A. Full-scale current is controlled by the value of the VCM current sense
resistor (Rsvcm). The retract control circuitry is fully integrated and does not require external isolation of the
device power supply terminals such as an external isolation transistor/diodes. Voice-coil driver auxiliary digital
control functions include an output-disable and low-power sleep mode following a retract of the VCM to the
landing zone. During a fault condition, the VCM drivers are disabled.
VCM current control
The voice-coil motor current is controlled by an internal 8-bit digital-to-analog converter (DAC), four adjustable
gain ranges, and the external current-sense resistor (Rsvcm). The four gain ranges (see functional block
diagram) are system dependent and provide the current needed to ensure that the head assembly swings
across the whole platter. Selecting one of the four gain ranges is accomplished via port A, bits 8 and 9 (see
Table 1 for gain settings and Table 4 for bit definitions). During the start mode, the 8-bit DAC is used to start the
spindle (see Figure 5). In the run mode, the 8-bit DAC is used to program the VCM current. Port A (bits 0 – 7)
controls the 8-bit DAC (see Table 4). The VCM current-control equation is given as follows:
IVCM = IX [ B7 + 1/2 B6 + 1/4 B5 + 1/8 B4 + 1/16 B3 + 1/32 B2 + 1/64 B1 + 1/128 B0 – 1] [A]
where:
IX = (Vref G) /(16 Rsvcm)
IX (+ full scale) at V = $FF
IX (– full scale) at V = $00
Vref (the internal system voltage reference) = 2 V
Rsvcm (the external VCM current sense resistor) typically 0.47
G (the VCM current gain scale)
B0 – B7 (port-A control bits)
1%
Maximum VCM current is load dependent. The following equation should be used as a guideline to determine
maximum VCM current:
IVCMmax = VCCmax / Rtotal
where:
VCCmax = 5.5 V
Rtotal = Rsvcm + 2
rDS(on) + Rvcm
Table 1. VCM Gain-Range Scale Truth Table
GAIN SWITCH SETTING
(see functional block diagram)
10
SERIAL PORT A GAIN SETTINGS
(see Table 4)
GS1
GS2
GS3
GR0
GR1
GAIN (G)
Open
Open
Open
0
0
0.250
Closed
Open
Open
0
1
0.333
Open
Closed
Open
1
0
0.500
Open
Open
Closed
1
1
1.000
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PRINCIPLES OF OPERATION
VCM current-loop stability is accomplished using the filter at CMPI and CMPO. This filter has the following
transfer function:
(Rcmp (Ccmp2 + Cmp1) s + 1)
Ccmp2 s (Rcmp Ccmp1 s + 1)
where:
s is a Laplace operator
VCM retract
The TLS2205 integrated retract circuit eliminates the need for external power supply isolation devices. The
retract mode is triggered by the voltage monitor fault logic signal. The retract power path is coupled from the
spindle-motor back-EMF to the RETOUT MOS high-side driver via CRET. After the retract control block has
been triggered by a loss of power, the following events occur:
1. The system control logic is reset to the power-up state. All bias is disabled (including VDD); all power
outputs are disabled.
2. The retract control circuit locks the VCMB low-side driver on and disables the VCMB high-side driver.
3. The retract control circuit disables the VCMA low- and high-side drivers.
4. RETOUT is enabled, and RETSET is used to control the voltage applied to RETOUT.
The spindle back-EMF-mode voltage supplies the energy necessary to retract the VCM (see Figure 3). The
energy stored in the capacitor (CVDD) connected to VDD is used to control the RETOUT and VCMB power
devices. The value of this capacitor can be calculated based on ~ 2 A of retract-mode discharge current and
the time to retract t the VCM. The RETOUT control equation is:
VVCMA = Vbe [1 + (Rrset1/Rrset2) ]
CVDD = 2 A ( t)
VVCMA
where:
Vbe is the base-to-emitter junction voltage
0.7 V.
Example:
Assume: Rrset1 = 62 k
Rrset2 = 100 k
t = 6 ms max
2 A (5 ms)
0.7 V (1 + 62 k /100 k )
= 0.009 F
0.01 F
t = 0.01 F [0.7 V (1 + 62 k /100 k )]
2 A
= 5.7 ms
Therefore: CVDD =
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SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
Figure 3 shows a block diagram of the TLS2205 retract equivalent circuit (retract mode only).
N
Spindle Motor
VDD
U
V
W
CRET
RETOUT
CVDD
RRETRACT
(or shorted)
Cret
VCMA
Clamp
Rsvcm
Rrset1
VCM
RETSET
VCMB
Vbe
Rrset2
Rlsd
1
NOTE: Area within the dotted line is internal to the device
Figure 3. Retract Equivalent Circuit
spindle-driver system
The spindle-driver system is capable of 1-A output current and has a total drain-to-source on-state resistance
(2 rDS(on)) of 1.3 Soft switching on the output drivers eliminates the need for external snubbers or flyback
diodes. An internal voltage clamp circuit helps protect against flyback voltages, while internal Schottky diodes
provide a low-loss power path for the VCM retract function. Internal logic and analog detection circuitry provide
complete sequencing of the power outputs in all run modes. Support for unipolar operation is provided by
disabling the spindle high-side drivers and pulling the motor center tap to 5 V using an external pnp or PMOS
transistor. CTDRV is used to control the base of the transistor during unipolar operation and is open otherwise.
During a fault condition, the spindle-motor drivers are disabled.
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PRINCIPLES OF OPERATION
spindle-driver system (continued)
For active braking, all the spindle low-side drivers are disabled and the high-side drivers are enabled, thereby
shorting out the spindle windings at or near the supply voltage, SPNVCC.
spindle commutation
Hall- or back-EMF-spindle commutation is selected from serial port C. See the port-C system control bit
definitions in Table 6 for additional information.
Hall mode
In the Hall mode, the spindle position information is input to the TLS2205 via the HU, HV, and HW logic input
terminals. Start current can be controlled with the internal 8-bit DAC, which is normally used to control the VCM
current or the internal charge pump. If the DAC option is selected, the VCM driver is normally disabled during
spindle start for power conservation. In either case, the spindle motor starts without microprocessor
intervention.
back-EMF mode
For the back-EMF mode, the system microprocessor is used in conjunction with the TLS2205 internal circuitry
to start the spindle motor.
Start current is controlled the same way as in the Hall mode by using the DAC. Two schemes can be used to
start commutation in the back-EMF mode. The first scheme is to use AUXIN; this method requires a pulse
generated from the microprocessor as an input signal to AUXIN. Various frequencies and start currents are used
to start the spindle motor. The second scheme is to use the COMM bit (bit 4) in port C. This method requires
the microprocessor to write to port C to change the state of bit 4. For every 1-to-0 state change of
bit 4, the spindle inverters advance one state. Different frequencies and start currents are used to start the
spindle motor. Once the motor has reached approximately 10% of its rated speed, the TLS2205 may be switched
into the run mode via port C.
Figure 4 shows the TLS2205 commutation delay circuit and the required external components.
2V
Vref
+
_
Rcom2
Rcom1 Ccom1
+
_
100 mV
NHphase
COMDLY 2
Ccom2
VPHASE
COMDLY 2
Figure 4. Commutation Delay Circuit
This circuit is composed of an operational amplifier (OPA) followed by a hysteresis comparator. The TLS2205
spindle inverter is advanced for every transition of the NHphase signal. The transition of NHphase occurs every
time the COMDLY2 signal crosses the common-mode reference, Vref. The required external components are
defined as:
Rcom1 – Integrator gain-set resistor
Ccom1 – DC-blocking capacitor
Rcom2 – Integrator dc-set resistor
Ccom2 – Integrator gain-set capacitor
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SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
back-EMF mode (continued)
The transfer function between COMDLY2 and VPHASE is :
Vcomdly2 =
[1 + s
s (Rcom2 Ccom1) VPHASE
(Rcom1 Ccom1)] [1 + s (Rcom2
Ccom2)]
where:
s is a Laplace operator
The component design procedures include the following:
Choose Rcom2 with a value as large as possible to permit small capacitor values. The typical value for
Rcom2 is 1 M
Calculate Ccom2 so that there is at least 45 of phase shift at the phase frequency where the TLS2205 is
switched into the internally commutated mode. The approximate value is 10% of the target frequency.
Calculate Rcom1 based on the desired COMDLY2 signal swing at the target frequency. The
recommended signal swing is 1.25 V peak. Near the target frequency the integrator function,
VCOMDLY2/VPHASE, becomes:
1
VCOMDLY2[Mag] =
(Rcom1
Ccom2)
(3
num
motor poles/2) Wmotor
VPHASE
VCOMDLY2[Phase] = – 90
VPHASE
0.433 Kb Wmotor sin(Wmotor t)
VCOMDLY2 =
(Rcom1 Ccom2) (3 num motor poles/2) Wmotor
0.433 Kb sin(Wmotor t)
VCOMDLY2 =
(Rcom1 Ccom2) (3 num motor poles/2)
The peak value of this function is independent of the frequency.
Rcom1 =
1.25
0.433
Ccom2 (3
Kb
Num Motor Poles/2)
Choose Ccom1 such that the dc-blocking pole, 1/(Rcom1 Ccom1), occurs at a frequency below the
integration pole, 1/(Rcom2 Ccom2). Typically the dc-blocking pole is placed at 1/2 the integration pole.
Where:
Wmotor = Mechanical frequency of the motor, r/s
Kb = Back-EMF constant, V/(r/s)
The internal speed-regulation feedback loop then takes control of spindle commutation, and further
microprocessor intervention is not required. Figure 5 shows the timing relationships for the
spindle-motor-control sequencing in both Hall and back-EMF modes. Internal logic and analog filtering provide
the commutation function in the commonly used back-EMF mode. In this mode, VPHASE (the difference
between the undriven phase and the center tap voltage) is filtered to generate a signal that determines
commutation timing (NHphase).
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PRINCIPLES OF OPERATION
High Phase
V
W
W
U
U
V
Off Phase
W
V
U
W
V
U
Low Phase
U
U
V
V
W
W
V
W
U
VPHASE
COMDLY2
NHphase
Phase
(speed clock)
Padv
(commutate)
(no Hall mode)
HV
HW
HU
HPhase
(commutate)
Figure 5. Spindle-Motor Control Sequencing
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SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
spindle-current control
Spindle-current control is accomplished by regulating the current through the external sense resistor, Rsspn,
via the spindle low-side drivers (LSD). Figure 6 illustrates the arrangement for the spindle-current control
(port C, bit 5) during the start mode (SPNMODE = 1) and the run mode (SPNMODE = 0). During startup
(SPNMODE = 1), the 8-bit DAC is used to command the spindle start current. Upon switching to the run mode
(SPNMODE = 0), the 8-bit DAC is used to control the VCM and the spindle motor is switched into closed-loop
operation (see Figure 6). The transconductance function is:
Ispindle = (0.079 SPNCOMP – 0.057) / Rsspn
Note:
Rsspn is typically 0.2
Vgs 1 V
Maximum spindle current is load dependent. The following equation should be used as a guideline to determine
maximum spindle current:
Ispindle = VCC(max) / Rtotal
where:
VCC(max) = 5.5 V
Rtotal = Rsspn + 2
rDS(on) + Rspindle
VCC
HSD
+
_
SPNCOMP
SPNVCC
EN
8
8-B
D/A
2
(0 – 2 V)
To VCM
(see Functional
Block Diagram)
Cspn1
Cspn2
SPNSW
R4
U, V, or W
+
_LSD
R3
SPNMODE
Rspn
Spindle
S
R1
R2
Vref
SPNSNSR1
NOTE: For startup mode (SPNMODE = 1), S = closed
For run mode (SPNMODE = 0), S = open
Area within the dotted line is internal to the device
Figure 6. Spindle-Current Control
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Rsspn
SPNSNSR2
SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
spindle-speed control
The TLS2205 provides a frequency-locked-loop speed-control system. Figure 7 is an illustration of the
spindle-speed control loop. This system operates by generating a once-around signal from either Hall or
back-EMF state changes. This signal is then divided by either 12 (for 8-pole motor) or 18 (for 12-pole motor)
(port B bit 11). This signal is called Fspn. Fspn is a once-around spindle-motor clock. Fspn is compared to a
signal that is generated from the MTRCLK (Fref). Fref is generated by dividing the MTRCLK by 16, then dividing
again by the value stored in the spindle-reference counter (port B bits 0 –10). The Fref and Fspn signals are
compared, and the time domain error is fed to the charge pump every other rotation. The charge-pump output
is a speed error signal that is filtered by a PI filter at SPNCOMP. The output of this filter commands the spindle
current. The spindle rotation TACH output (Fspn) or the back-EMF commutation clock (NHphase) can be directly
measured at AUXOUT. AUXIN can be used to provide an external index signal for motor commutation instead
of using the speed feedback circuit. See Table 7 for a description of the spindle-motor operating modes.
Spindle rotational speed is calculated from the equation below:
fspindle = fMTRCLK /[ (16
R) + 1] [Hz]
where:
R is the value stored in port B bits 0 –11 (0 < R < 2047)
Spindle-speed regulation 1 / [( 8 R) + 1] (%)
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SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
Motor
Padv
VSPNCOMP
Ispindle
Kt
Js
Speed
Detect
GA
1440 Hz @ Fspn = 3600 RPM
8-Pole Motor
Fspn
Up
/12 or /18
MTRCLK
/2
(/R) + 1
0<R<2047
/8
Time-Difference
Detector
Fref
Count_Enable
Down
Charge
Pump
SPNMODE
SPNCOMP
Count_Clear
Cspn1 Cspn2
SPNSW
Rspn
Speed Up
Slow Down
Fspn
Fref
Up
Down
Count_Enable
Count_Clear
NOTE: Area within dotted line is internal to the device
Figure 7. Spindle-Control Loop Block Diagram and Timing Waveforms
serial port
The TLS2205 serial port is designed to receive 16-bit data in three-wire serial format and distribute the data to
internal data and control ports. The serial-port interface is designed to be compatible with the Texas Instruments
TMS320C2x digital signal processor (DSP) family or standard 8- or 16-bit microprocessors. Data can be
transmitted in either 8- or 16-bit format. The data is sent MSB first for the 16-bit word. The first four MSBs
determine the port address. The other 12 bits are used for data or port control functions. The first two MSBs must
both be 0 to select the device. The received data is routed to one of three internal 12-bit register ports. Port A
controls the VCM DAC and gain range of eight data bits with four gain ranges. Port B is used to set the spindle
reference counter. Port C is used for system controls.
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PRINCIPLES OF OPERATION
serial-port timing
The TLS2205 is designed to receive data in four basic formats: TMS320C2x burst mode, TMS320C2x
continuous mode, 8-bit microprocessor format mode, and 16-bit microprocessor format mode.
The serial port uses three control lines: SCLK (serial-port clock), SDATA (serial-port data), and SPSZ (serial-port
select not). The SCLK line is a serial data clock with data rates up to 12 MHz; SCLK should have a 50% duty
cycle. The SDATA line is the actual serial data input and must be synchronous with the leading edge of SCLK.
SPSZ is the serial-port select input and is internally tied low to be synchronous with the leading edge of SCLK.
If the TMS320C2x DSP is used in burst or continuous modes, the following bits in the ST1 register should be
set (1) or reset (0) as indicated:
BIT NAME
BIT #
SET/RESET
RESULT
TXM (transmit mode)
2
1
FSX is configured as an output
FO (format)
3
0
16-bit mode selected
FSM (framing sync)
5
1
A framing sync is generated
Refer to the TMS320C2x User’s Guide for further details.
burst mode
In the serial-port burst-mode operation, transfers are separated in time by periods of no serial-port activity (the
serial port does not operate continuously). For burst-mode operation, the SPSZ line must be low on the
negative-going edge of SCLK before data is read in; then 16 data bits can be read in. All continuing data bits
are ignored until the SPSZ line is toggled from low to high to low. Then data is valid on the first negative-going
clock. See Figure 8 for details.
SCLK
Frame Sync
SPSZ
SR11
Device
Port
12 Data Bits
SDATA
ID1
ID0 PT1 PT0 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
ID1
ID0 PT1 PT0
NOTE: ID1 must be the first bit shifted into the register; after 15 shifts, the TLS2205 is selected and the desired port is loaded with valid data.
Figure 8. Serial-Port Burst-Mode Operation
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SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
continuous mode
In the continuous-mode serial-port operation, transfers are continuous in time. In the continuous mode, the
SPSZ line is toggled from high to low every falling edge (16 SCLK cycles). See Figure 9 for details.
SCLK
Frame Sync
SPSZ
Device
Port
12 Data Bits
SDATA
ID1
ID0 PT1 PT0 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 ID1
ID0 PT1 PT0 SR11
Figure 9. Serial-Port Continuous-Mode Operation
8-bit/16-bit microprocessor mode
In 8- or 16-bit serial-port operation, transfer of data must meet the following criteria:
1. SDATA must change on the leading edge of SCLK.
2. SPSZ must go high after the falling edge of SCLK at the end of byte 1 of the data transmission.
3. SPSZ must go low on the leading edge of SCLK during the first bit of the second byte of the data
transmission.
4. SPSZ must stay low until SCLK goes low on the last bit of the second byte of the data transmission.
After the second byte has been transmitted, the data is decoded and sent to the proper port. If the SPSZ line
goes high during an invalid bit time, the serial port resets and waits for a valid address. See Figure 10 for details.
SCLK
SPSZ
SPSZ Must Go High After Falling
Edge Of Eighth Clock
Byte 1
SPSZ Must Go High After Falling
Edge Of Sixteenth Clock
Byte 2
SDATA
ID1
ID0 PT1 PT0 SR11 SR10 SR9 SR8
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
Figure 10. Serial-Port Microprocessor-Mode Operation
NOTE: ID1 must be the first bit shifted into the register; after 15 shifts, the TLS2205 is selected and the desired port is loaded with valid data.
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port and data-bit definitions
The TLS2205 incorporates three programmable ports that must be programmed via the serial port (SCLK,
SDATA, and SPSZ). ID0 must be the first bit shifted into the register; after 15 shifts, the following occurs:
1. If ID0 = 0 and ID1 = 0, the TLS2205 is selected (see Table 2) and the rest of the data is processed.
2. PT0 and PT1 determine which port is selected (see Table 3).
3. The 16 bits of data are serially loaded into the serial port register.
4. The selected port is loaded with all 16 bits of data. Port A controls the VCM (see Table 4), port B controls
the spindle motor (see Table 5), and port C controls the device functions (see Table 6).
Table 2. Device Select
DEVICE SELECT
Chip selected
Chip not selected
ID1
ID0
0
0
0
1
1
0
1
1
DESCRIPTION
The TLC2205 serial port is selected.
Table 3. Port Selection
PT1
PT0
No port
PORT SELECT
0
0
Null
A
0
1
VCM port A
B
1
0
Spindle-speed port B
C
1
1
System control port C
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PRINCIPLES OF OPERATION
Table 4. Port-A Definition (VCM Control)
BIT #
NAME
DESCRIPTION
0
B0
VCM DAC control word LSB
1
B1
VCM DAC control word
2
B2
VCM DAC control word
3
B3
VCM DAC control word
4
B4
VCM DAC control word
5
B5
VCM DAC control word
6
B6
VCM DAC control word
7
B7
VCM DAC control word MSB
8
GR0
VCM gain-control LSB
9
GR1
VCM gain-control MSB
10
—
Future expansion
11
—
Future expansion
12
PT0
Port-select LSB
13
PT1
Port-select MSB
14
ID0
Device-select LSB
15
ID1
Device-select MSB
Table 5. Port-B Definition (Spindle-Speed Regulator Control Word)
BIT #
22
NAME
DESCRIPTION
COUNT
0
R0
Spindle reference-counter LSB
1
1
R1
Spindle reference counter
2
2
R2
Spindle reference counter
4
3
R3
Spindle reference counter
8
4
R4
Spindle reference counter
16
5
R5
Spindle reference counter
32
6
R6
Spindle reference counter
64
7
R7
Spindle reference counter
128
8
R8
Spindle reference counter
256
9
R9
Spindle reference counter
512
10
R10
Spindle reference-counter MSB
1024
11
MTR POLE
12
PT0
Port-select LSB
13
PT1
Port-select MSB
14
ID0
Device-select LSB
15
ID1
Device-select MSB
Spindle-motor pole switch (8 or 12)
0 = 8 pole, 1 = 12 pole
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PRINCIPLES OF OPERATION
Table 6. Port-C Definition (System Control Functions)
BIT #
NAME
SUBSYSTEM
0
SPNENA
SPN
Spindle power-inverter enable
DESCRIPTION
1
START
SPN
Spindle-operation mode
2
NHALLS
SPN
No Hall-commutation-mode select
3
UPOLAR
SPN
Spindle-inverter unipolar select
4
COMM
SPN
Spindle-inverter advance (no hall mode)
5
SPNMODE
SPN
Select DAC current-control mode
6
VCMENA
VCM
VCM power output enable
7
BRAKE
SPN
Spindle BRAKE enable
8
BEMF GAIN
SPN
Back-EMF amplifier sense gain
9
AUX0
SYS
AUXOUT function select MSB
10
AUX1
SYS
AUXOUT function select LSB
11
AWAKE
SYS
System power enable
12
PT0
SYS
Port-select LSB
13
PT1
SYS
Port-select MSB
14
ID0
SYS
Device-select LSB
15
ID1
SYS
Device-select MSB
Port-C system control bit definitions
AWAKE
This bit controls the dc bias conditions in the device. When this bit is low, the device is in the sleep mode and
all dc bias sources, with the exception of the voltage monitor, are disabled. All logic, with the exception of the
serial register, is disabled, and device power dissipation is minimized. When this bit is high, the device is awake
and power dissipation is maximum.
AUX1
AUX1 is the MSB of the auxiliary logic control functions (see Table 7).
AUX0
AUX0 is the LSB of the auxiliary logic control functions (see Table 7).
BEMF GAIN
This bit controls the gain of the back-EMF sense amplifier. When the bit is low, the forward back-EMF gain sense
(measured at Vphase) is one. When the bit is high, the forward sense gain is five. This function is intended to
start the spindle motor in back-EMF mode.
BRAKE
BRAKE enables the high-side power inverters and disables the low-side power drivers. The brake is normally
implemented after a retract has occurred and the head has reached the head stop.
VCMENA
VCMENA enables the VCM output drivers. In the disabled state, the VCM output power amplifier outputs go low.
However, the power amplifiers still have dc bias applied and can be enabled in a short period of time.
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PRINCIPLES OF OPERATION
Port-C system control bit definitions (continued)
SPNMODE
SPNMODE is used to determine whether the spindle charge pump or DAC is driving the spindle-control
amplifiers. When SPNMODE is asserted, the spindle current is controlled by the DAC.
COMM
The COMM bit is used to commutate the spindle driver in the start mode. For every low-to-high state change,
the spindle inverter advances one step.
UPOLAR
UPOLAR controls the spindle-motor drive mode. When this bit is low, the TLS2205 drives the motor in a standard
bipolar mode. When this bit is high, CTDRV is switched low and the internal high-side drivers are disabled. An
external pnp transistor can be switched on using CTDRV, and the device operates in the unipolar mode.
NHALLS
The NHALLS bit controls which commutation mode is used by the spindle-control logic. When this bit is 0, the
TLS2205 uses the Hall sense inputs (HU, HV, HW) to directly commutate the spindle motor. When this bit is 1,
the TLS2205 switches into the back-EMF commutation mode. The Hall inputs have no meaning in the back-EMF
commutation mode. However, the Hall logic inputs determine the motor inverter power-up initial state. The Hall
inputs are internally tied low.
START
This bit controls the spindle-motor driver logic inputs and auxiliary I/O signals (see Table 7).
SPNENA
The SPNENA bit enables the spindle-motor drivers. The charge-pump control path (SPNCOMP) is not affected
by this bit. When this bit is 0, the spindle-motor power drivers are disabled (motor phases U, V, W are Hi-Z) but
not powered down. When this bit is 1, the spindle drivers are enabled.
AUXIN/AUXOUT functional description
Port-C controls (for spindle-motor operation in back-EMF mode)
The spindle-motor operation modes are shown in the description section of Table 7. To fully understand this
figure, the functional block diagram must be used in conjunction with port C.
As an example:
1. To start the drive (START MODE), START (bit 1) = 0, AUX1 (bit 10) = 1, and AUX0 (bit 9) = 1. As a result,
Phase is the signal seen on the internal PCLK line, SCK is the signal seen on the internal PADV line, and
NHphase is the signal seen at AUXOUT.
2. Once the spindle is spinning at approximately 20% of rated speed, the drive is switched into RUN
MODE 0 (START = 0, AUX1 = 0, and AUX0 = 0). As a result, phase is the signal seen on the internal
PCLK line and NHphase is the signal seen on the internal PADV line and at AUXOUT.
3. After the spindle reaches operational speed, the drive is switched into RUN MODE 3 (START = 0,
AUX1 = 1, AUX0 = 1). As a result, AUXIN is the signal seen on the internal PCLK line, NHphase is the
signal seen on the internal PADV line, and Fspn is the signal seen at AUXOUT.
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SLFS040 – DECEMBER 1993
PRINCIPLES OF OPERATION
Table 7. Spindle-Motor Operating Modes
PORT C
AUXOUT
PCLK
PADV
START
BIT 1
AUX1
BIT 10
AUX0
BIT 9
MULTIPLEXER
OUTPUT
MULTIPLEXER
OUTPUT
MULTIPLEXER
OUTPUT
DESCRIPTION
0
0
0
NHphase
Phase
NHphase
RUN MODE0
0
0
1
NHphase
AUXIN
NHphase
RUN MODE1
0
1
0
Fspn
Phase
NHphase
RUN MODE2
0
1
1
Fspn
AUXIN
NHphase
RUN MODE3
1
0
0
Fref
AUXIN
SCK
1
0
1
Fref
AUXIN
SCK
TEST MODE0 †
TEST MODE1 †
1
1
0
Fspn
AUXIN
SCK
TEST MODE2 †
1
1
1
NHphase
Phase
SCK
START MODE
† These test modes were developed for internal chip testing.
descriptions
AUXOUT:
AUXIN:
PCLK:
PADV:
START:
AUX0:
AUX1:
COMM:
Fspn:
The auxiliary logic output multiplexer
The auxiliary logic input (can be used to commutate spindle)
The spindle-speed feedback clock (AUXIN or phase)
The spindle phase-advance clock (back-EMF mode)
Spindle start mode (from port C, bit 1, 1 = enable)
Option control (from port C, bit 9)
Option control (from port C, bit 10)
Commutation via serial port (from port C, bit 4)
The once-around signal and the frequency of PCLK divided by 12 for an 8 pole motor (bit 11
on port B set low), or divided by 18 for a 12 pole motor (bit 11 on port B set high).
Fref:
The divided output of the speed-discriminator reference frequency (MTRCLK)
Phase:
The spindle-control logic output of the spindle even states (see Figure 4, SC 0,2,4)
NHphase:
No Halls phase is the back-EMF zero-crossing clock
Hphase:
Halls-phase clock from external Hall sensors
SCK:
Start clock, AUXIN ORed with COMM (from port C, bit 4)
RUN MODE 0: Speed feedback information comes from motor commutation, AUXOUT = NHphase
RUN MODE 1: Speed feedback information comes from AUXIN, AUXOUT = NHphase
RUN MODE 2: Speed feedback information comes from motor commutation, AUXOUT = Fspn
RUN MODE 3: Speed feedback information comes from AUXIN, AUXOUT = Fspn
TEST MODE 0: AUXOUT = Fref: Fref = MTRCLK/N; N = value stored in port-B reference counter
TEST MODE 1: AUXOUT = Fref: Fref = MTRCLK/(16 N); N = same as above
TEST MODE 2: AUXOUT = Fspin: Fspin = AUXIN/12 or 18 depending on number of motor poles (port B, bit 11)
START MODE: Spindle commutation is controlled externally via AUXIN
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DALLAS, TEXAS 75265
25
SLFS040 – DECEMBER 1993
APPLICATION INFORMATION
5V
5V
9
18
C12
AVCC
DVCC
VCMVCC
SPNVCC
R1
5
C1
CRET
UV
CTDVR
R2
SPNSW
SPNCOMP
C4
25
C5
23
L m, Rm
12
VCM
17
24
20
CMP0
RSENP
SPNSNSR1
CTS
VCMA
W
VCMB
V
RSENN
U
RETOUT
PORN
R3
21 RETSET
28
VCMREF
27 VIVCM
R4
SDATA
SPSZ
SCLK
MTRCLK
49
50
51
36
C2
6
C3
10
11
13
14
15
16
19
C10
37
29
C13
30
35
HW
HV
HU
REFBUF
CPOR
AUXIN
AUXOUT
40
COMDLY1
VCMGND
COMDLY2
SPNGND
SPNGND
SPNGND
SPNGND
SPNGND
SPNGND
SPNGND
SPNGND
DGND
DALLAS, TEXAS 75265
C9
34
38
39
47
4
2
3
1
56
54
53
33
R8
31
32
41
42
43
44
48
Figure 11. Spindle Motor-Driver Application
POST OFFICE BOX 655303
R9
R10
C7
VPHASE
VDD
AGND
45
Pin numbers shown are for the DL package; see Table 8 for external component values.
26
C11
TLS2205
SPNSNSR2
R5
46
C8
CMPI
R6
26
55
C6
R7
SLFS040 – DECEMBER 1993
APPLICATION INFORMATION
Lm, Rm
VCM
R4
R5
R3
R6
C5
13
DVCC
SPNVCC
VCMVCC
PORN
R1
61
SDATA
UV
SPSZ
SCLK
R2
C1
5V
CMPI
CMP0
20
21
18
RSENP
VCMA
11
12
VCMB
19
RSENN
16
23
15
RETOUT
C12
AVCC
RETSET
1
VCMREF
5V
VIVCM
22
C4
MTRCLK
R10
58
59
57
56
54
53
R8
28
C7
26
CRET
SPNGND
DGND
R7
27
42
41
40
39
47
34
CTDRV
SPNGND
24
25
AGND
SPNCOMP
VCMGND
30
VCMGND
SPNSW
SPNGND
45,46
14
VCMGND
SPNSNSR2
10
SPNGND
SPNSNSR1
9
VCMGND
38
8
C11
60
C6
COMDLY2
43
7
C10
44
CPOR
VDD
W
4
CTS
62
C3
COMDLY1
REFBUF
29
C2
HU
V
33
VPHASE
37
52
AUXOUT
HV
35,36
51
AUXIN
TLS2205
5-V VCM SPINDLE-MOTOR DRIVER
HW
U
48
55
C8
C13
C9
R9
Pin numbers shown are for the PM package; see Table 8 for external component values.
Figure 12. Spindle Motor-Driver Application
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27
SLFS040 – DECEMBER 1993
APPLICATION INFORMATION
Table 8. External Components and Approximate Values
ALIAS
SUBSYSTEM†
R1
Ruv1
VM
External voltage-set resistor
100 k
R2
Ruv2
VM
External voltage-monitor set resistor
270 k
R3
Rrset1
SPN
Retract velocity-limit-set resistor
62 k
R4
Rrset2
SPN
Retract velocity-limit set resistor
100 k
R5
Rsvcm
VCM
VCM current-control resistor
R6
Rcmp
VCM
VCM frequency-compensation resistor
R7
Rcom2
SPN
Spindle commutation-control resistor
1M
R8
Rcom1
SPN
Spindle commutation-control resistor
56 k
R9
Rspn
SPN
Spindle speed-regulator compensation resistor
470 k
R10
Rsspn
SPN
Spindle transconductance-control resistor
0.33
C1
Cuv1
VM
External voltage-set capacitor
C2
Cpor
VM
Reset-time-delay capacitor
0.02 F
C3
CVDD
VM
Charge-pump storage capacitor
0.01 F
C4
Ccmp2
VCM
VCM frequency-compensation capacitor
120 pF
C5
Ccmp1
VCM
VCM frequency-compensation capacitor
1500 pF
C6
Ccom2
SPN
Spindle commutation-delay capacitor
2000 pF
C7
Ccom1
SPN
Spindle commutation-delay capacitor
C8
Cspn1
SPN
Spindle-speed-regulator frequency-compensation capacitor
0.68 F
C9
Cspn2
SPN
Spindle-speed-regulator frequency-compensation capacitor
0.048 F
C10
CV CC1
All
Power-supply bypass capacitor
0.1 F
C11
CV CC2
All
Power-supply bypass capacitor
47 F
C12
CV CC3
All
Power-supply bypass capacitor
0.1 F
C13
Cret
SPN
NAME
DESCRIPTION
Option filter of back-EMF-mode voltage capacitor
† SPN = spindle, VCM = voice-coil motor, VM = voltage monitor
28
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VALUE
0.33 k
82 k
1 F
0.2 F
1 F
SLFS040 – DECEMBER 1993
MECHANICAL DATA
DL/R-PDSO-G**
PLASTIC SHRINK SMALL-OUTLINE PACKAGE
48-PIN SHOWN
0.012 (0,305)
0.008 (0,203)
0.025 (0,635) TYP
(see Note C)
48
25
0.299 (7,59)
0.291 (7,39)
** PINS
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
0.420 (10,67)
0.395 (10,03)
0.009 (0,229)
0.005 (0,127)
1
24
A
0 –8
0.110 (2,79)
0.040 (1,02)
0.095 (2,41)
0.020 (0,51)
0.016 (0,406)
0.008 (0,203)
NOTES: A.
B.
C.
D.
E.
F.
G.
4040048/A–07/93
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Leads are within 0.0035 (0,089) radius of true postion at maximum material condition.
Body dimensions do not include mold flash, protrusion, or gate burr.
Mold flash, protrusion, or gate burr shall not exceed 0.015 (0,381).
Lead tips coplanar within 0.004 (0,102).
Lead length measured from lead top to point 0.010 (0,254) above seating plane.
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29
SLFS040 – DECEMBER 1993
MECHANICAL DATA
PM/S-PQFP-G64
PLASTIC QUAD FLAT PACKAGE
0,26
0,14
0,50 TYP
48
33
32
49
Pin # 1
Indicator
64
17
1
0,177
0,147
16
7,50 SQ TYP
10,10
SQ
9,90
12,20
11,80
SQ
0 –10
1,70 MAX
0,70
0,30
0,00 MIN
4040152/A–07/93
NOTES: A.
B.
C.
D.
30
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Maximum deviation from coplanarity is 0,08 mm.
Body dimensions do not include mold flash or protrusion.
POST OFFICE BOX 655303
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1999, Texas Instruments Incorporated