TH7110 315/433MHz FSK/FM/ASK Receiver Features ! ! ! ! ! ! ! ! Double superhet architecture for high degree of image rejection FSK for digital data and FM reception for analog signal transmission FM/FSK demodulation either with phase-coincidence or PLL demodulator Low current consumption in active mode and very low standby current Switchable LNA gain for improved dynamic range AFC feature allows wide carrier frequency acceptance range RSSI allows signal strength indication and ASK detection Surface mount package LQFP44 Ordering Information Part No. Temperature Range Package TH7110 -40 °C to 85 °C LQFP44 Application Examples ! ! ! ! ! General digital and analog 315 MHz or 433 MHz ISM band usage Low-power telemetry Alarm and security systems Keyless car and central locking Pagers Technical Data Overview ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Input frequency range: 300 MHz to 450 MHz Power supply range: 2.5 V to 5.5 V for double conversion and 2.7 V to 5.5 V for single conversion Temperature range: -40 °C to +85 °C Operating current: 6.5 mA at low gain and 8.2 mA at high gain mode Standby current: < 100 nA 1) with 40 kHz second IF filter BW (incl. SAW front-end filter loss) Sensitivity: -111 dBm 2) Sensitivity: -104 dBm with 150 kHz second IF filter BW (incl. SAW front-end filter loss) Range of first IF: 10 MHz to 80 MHz Range of second IF: 455 kHz to 21.4 MHz Maximum input level: –10 dBm at ASK and 0 dBm at FSK nd Image rejection: > 65 dB (e.g. with SAW front-end filter and at 10.7 MHz 2 IF) Spurious emission: < -70 dBm Input frequency acceptance: ±50 kHz (with AFC option) RSSI range: 70 dB Frequency deviation range: ±5 kHz to ±120 kHz Maximum data rate: 80 kbit/s NRZ Maximum analog modulation frequency: 15 kHz 1) 2) at ± 8 kHz FSK deviation, BER = 3⋅10 and phase-coincidence demodulation -3 at ± 50 kHz FSK deviation, BER = 3⋅10 and phase-coincidence demodulation TH7110 Data Sheet 3901007110 -3 Page 1 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver General Description The TH7110 receiver IC consists of the following building blocks: " " " " " " " " " PLL synthesizer (PLL SYNTH) for generation of the first and second local oscillator signals LO1 and LO2 Parts of the PLL SYNTH are the high-frequency VCO1, the feedback dividers DIV_8 and DIV_2, a phase-frequency detector (PFD) with charge pump (CP) and a crystal-based reference oscillator (RO) Low-noise amplifier (LNA) for high-sensitivity RF signal reception First mixer (MIX1) for down-conversion of the RF signal to the first IF (IF1) second mixer (MIX2) for down-conversion of the IF1 to the second IF (IF2) IF amplifier (IFA) to amplify and limit the IF2 signal and for RSSI generation Phase coincidence demodulator (DEMOD) with third mixer (MIX3) to demodulate the IF signal Operational amplifier (OA) for data slicing, filtering, ASK detection and automatic-frequency control (AFC) Bias circuitry for bandgap biasing and circuit shutdown With the TH7110 receiver chip, various circuit configurations can be arranged in order to meet a number of different customer requirements. For FM/FSK reception the IF tank used in the phase coincidence demodulator can be constituted either by a ceramic resonator or an LC tank (optionally with varactor to create an AFC circuit). In PLL demodulator configuration, the multiplier MIX3 forms a phase comparator. In ASK configuration, the RSSI signal is feed to an ASK detector, which is constituted by the operational amplifier. The second VCO (VCO2) can be used either as the VCO of a PLL demodulator or as the LO2 source of a second external PLL in a multi-channel system. The following table briefly summarizes the various configurations. Single-conversion configuration Double-conversion configuration FM/FSK narrow-band RX with ceramic demodulation tank narrow-band RX with ceramic demodulation tank FM/FSK wide-band RX with LC demod. tank and AFC wide-band RX with LC demod. tank and AFC FM/FSK extended sensitivity RX with PLL demodulator extended sensitivity RX with PLL demodulator multi-channel RX with ceramic demodulation tank and external channel synthesizer FM/FSK ASK RX with RSSI-based demodulation ASK RX with RSSI-based demodulation RX with RSSI-based demodulation and external channel synthesizer The preferred superheterodyne configuration is double conversion where MIX1 and MIX2 are driven by the internal local oscillator signals LO1 and LO2, respectively. This allows a high degree of image rejection, achieved in conjunction with an RF front-end filter. Efficient RF front-end filtering is realized by using a SAW, ceramic or helix filter in front of the LNA and by adding a LC filter at the LNA output. It is also possible to use the TH7110 in single-conversion configuration. This can be achieved by switching the LO2 input of MIX2 from the on-chip PLL synthesizer to the pin IN_MIX2 by means of an internal switch (done via pin SW_MIX2). Now MIX2 operates as an amplifier for the IF1 signal if an external pull-down resistor at pin IN_MIX2 is added. The same setting of MIX2 can be used for multi-channel applications. In this situation IN_MIX2 must be driven by an external LO2 signal. This signal can be generated by the VCO2, which is mainly a bipolar transistor that can be configured as a varactor-tuned VCO. Furthermore, a second external PLL for channel selection via LO2 tuning is required. This may be arranged by using a PLL synthesizer chip that can be controlled through a 3-wire bus serial interface. The reference signal for the external PLL synthesizer can be directly taken from the crystal-based reference oscillator RO. TH7110 Data Sheet 3901007110 Page 2 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver 23 24 VCO2_E 26 VCO2_B OUT_OA 27 28 OAN OAP VCO2 OA 32 31 OUTN OUTP Block Diagram 25 VCC_BIAS VEE_BIAS 30 MIX3 20 IN_DEM 1 VREF ENRO 44 BIAS ENRX 37 19 OUT_IFA 36 18 VCC_PLL VEE_RO 34 RSSI RO 35 17 RO 33 IFA 29 VEE_PLL LO2 IN_MIX2 11 21 6 LF2 IN_MIX1 VCO1 5 VEE_LNA MIX1 7 CAP_MIX1 LO1 8 VEE_MIX1 DIV_8 switch 9 IF1P 22 IF1 10 IF1N SW_MIX2 VCC_MIX1 MIX2 12 VCC_MIX2 DIV_2 13 OUT_MIX2 CP IF2 14 VEE_IF 38 15 PFD IN_IFA LF1 16 FBC1 40 VEE_VCO1 43 41 VCC_LNA VEE_LNA 42 2 VEE_LNAC IN_LNA 3 GAIN_LNA LNA 4 39 OUT_LNA Fig. 1: TH7110 block diagram TH7110 Data Sheet 3901007110 Page 3 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Frequency Planning Frequency planning is straightforward for single-conversion applications because there is only one IF that might be chosen, and then the only possible choice is low-side or high-side injection of the LO1 signal (which is now the one and only LO signal in the receiver). The receiver’s double-conversion architecture requires careful frequency planning. Besides the desired RF input signal, there are a number of spurious signals that may cause an undesired response at the output. Among them are the image of the RF signal (that must be suppressed by the RF front-end filter), spurious signals injected to the first IF (IF1) and their images which could be mixed down to the same second IF (IF2) as the desired RF signal (they must be suppressed by the LC filter at IF1 and/or by low-crosstalk design). By configuring the TH7110 for double conversion and using its internal PLL synthesizer with fixed feedback divider ratios of N1 = 8 (DIV_8) and N2 = 2 (DIV_2), four types of down-conversion are possible: low-side injection of LO1 and LO2 (low-low), LO1 low-side and LO2 high-side (low-high), LO1 high-side and LO2 low-side (high-low) or LO1 and LO2 high-side (high-high). The following table summarizes some equations that are useful to calculate the crystal reference frequency (REF), the first IF (IF1) and the VCO1 or first LO frequency (LO1), respectively, for a given RF and second IF (IF2). Injection type high-high low-low high-low low-high REF (RF – IF2)/14 (RF – IF2)/18 (RF + IF2)/14 (RF + IF2)/18 LO1 16•REF 16•REF 16•REF 16•REF IF1 LO1 – RF RF – LO1 LO1 – RF RF – LO1 LO2 2•REF 2•REF 2•REF 2•REF IF2 LO2 – IF1 IF1 – LO2 IF1 – LO2 LO2 – IF1 The following table depicts generated, desired, possible images and some undesired signals considering the examples of 315 MHz and 433.6 MHz RF reception at IF2 = 10.7 MHz. Signal type RF = 315 MHz RF = 315 MHz RF = 315 MHz RF = 315 MHz RF = RF = RF = RF = 433.6 MHz 433.6 MHz 433.6 MHz 433.6 MHz Injection type high-high low-low high-low low-high high-high low-low high-low low-high REF / MHz 21.73571 16.90556 23.26429 18.09444 30.20714 23.49444 31.73571 24.68333 LO1 / MHz 347.77143 270.48889 372.22857 289.51111 483.31429 375.91111 507.77143 394.93333 IF1 / MHz 32.77143 44.51111 57.22857 25.48889 49.71429 LO2 / MHz 43.47143 33.81111 46.52857 36.18889 60.41429 57.68889 74.17143 38.66667 46.98889 63.47143 49.36667 RF image/MHz 380.54286 225.97778 429.45714 264.02222 533.02857 318.22222 581.94286 356.26667 IF1 image/MHz 46.88889 54.17143 23.11111 35.82857 71.11429 36.28889 52.77143 60.06667 The selection of the reference crystal frequency is based on some assumptions. As for example: the first IF and the image frequencies should not be in a radio band where strong interfering signals might occur (because they could represent parasitic receiving signals), the LO1 signal should be in the range of 300 MHz to 430 MHz (because this is the optimum frequency range of the VCO1). Furthermore the first IF should be as high as possible to achieve highest RF image rejection. The columns in bold depict the selected frequency plans to receive at 315 MHz and 433.6 MHz, respectively. TH7110 Data Sheet 3901007110 Page 4 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Pin Definition and Description Pin No. 1 Name VREF I/O Type Functional Schematic Description analog output reference voltage output, approx. 1.23V VREF 1 4 OUT_LNA 60k analog output OUT_LNA 4 42 2 IN_LNA VEE_LNAC analog input IN_LNA ground 42 LNA input, approx. 26Ω single-ended 5k VEE_LNAC 2 3 GAIN_LNA LNA open-collector output, to be connected to external LC tank that resonates at RF analog input ground of LNA core (cascode) LNA gain control (CMOS input with hysteresis) GAIN_LNA 400Ω 3 5 VEE_LNA ground 6 IN_MIX1 analog input LNA biasing ground MIX1 input, approx. 33Ω single-ended 13Ω IN_MIX1 6 13Ω 500µA 7 CAP_MIX1 analog I/O 40µA CAP_MIX1 7 8 VEE_MIX1 ground 9 IF1P analog I/O 330Ω MIX1 ground VCC 20p IF1P IF1N 20p 10 9 10 IF1N analog I/O open-collector output, to be connected to external LC tank that resonates at first IF open-collector output, to be connected to external LC tank that resonates at first IF 2x500µA VEE VEE TH7110 Data Sheet 3901007110 connection for MIX1 blocking capacitor Page 5 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Pin No. Name I/O Type Functional Schematic Description 11 VCC_MIX1 supply MIX1 positive supply 12 VCC_MIX2 supply MIX2 positive supply 13 OUT_MIX2 analog output MIX2 output, approx. 330Ω output impedance 6.8k 130Ω OUT_MIX2 13 230µA 14 VEE_IF ground 15 IN_IFA analog input 16 FBC1 analog I/O ground of MIX2, IFA and DEMOD IN_IFA FBC1 15 16 VEE VCC 2.2k 2.2k 200µA FBC2 17 FBC2 IFA input, approx. 2.2kΩ input impedance VCC VCC VEE VEE analog I/O to be connected to external IFA feedback capacitor to be connected to external IFA feedback capacitor 17 VEE 18 VCC_IF supply positive supply for IFA, DEMOD and VCO2 19 OUT_IFA analog I/O IFA output and MIX3 input (of DEMOD) OUT_IFA 19 40µA 20 IN_DEM analog input DEMOD input, to MIX3 core 47k IN_DEM 20 21 SW_MIX2 digital input input selection for LO2 input port of MIX2 SW_MIX2 400Ω 21 TH7110 Data Sheet 3901007110 Page 6 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Pin No. 22 Name IN_MIX2 I/O Type Functional Schematic analog input Description external LO2 input port of MIX2, approx. 1kΩ singleended 840Ω IN_MIX2 22 840Ω 20µA 24 VCO2_B analog input VCC VCC VCO2 input, base of a bipolar transistor 47k VCO2_B 24 23 VCO2_E VEE VCC analog output VCO2 output, emitter of a bipolar transistor VCO2_E 23 VEE 25 VCC_BIAS supply positive supply of general bias system and OA 26 OUT_OA analog output OA output, 40uA current drive capability OUT_OA 50Ω 26 27 OAN analog input 20µA OAN 28 29 OAP RSSI analog input 50Ω 50Ω OAP 28 27 analog output RSSI 50Ω I (Pi) negative OA input, input voltage limited to approx. 0.7 Vpp between pins OAP and OAN positive OA input, input voltage limited to approx. 0.7 Vpp between pins OAP and OAN RSSI output, for RSSI and ASK detection, approx. 36kΩ output impedance 29 36k 30 VEE_BIAS TH7110 Data Sheet 3901007110 ground ground for general bias system and OA Page 7 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Pin No. 31 Name OUTP I/O Type analog output Functional Schematic OUTP OUTN Description FSK/FM positive output, output impedance of 100kΩ to 300kΩ 50Ω 32 OUTN analog output 33 VEE_PLL ground ground of dividers and PFD 34 VEE_RO ground RO ground 35 RO analog input RO input, Colpitts type oscillator with internal feedback capacitors 31 32 20µA 20µA 50k RO 35 FSK/FM negative output, output impedance of 100kΩ to 300kΩ 30p 30p 36 VCC_PLL supply 37 ENRX digital input 44 ENRO digital input 38 LF1 analog output positive supply of RO, DIV, PFD and charge pump mode control input (CMOS input) ENRX ENRO 1.5k mode control input (CMOS input) 37 44 charge pump output LF1 200Ω 38 39 LF2 analog input VCO1 control input LF2 400Ω 39 4p 40 VEE_VCO1 ground ground of VCO1 and charge pump 41 VEE_LNA ground ground of LNA biasing 43 VCC_LNA supply positive supply of LNA biasing TH7110 Data Sheet 3901007110 Page 8 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Technical Data Mode Configurations ENRX ENRO Mode 0 0 SBY 0 1 RO only 1 0 ON 1 1 ON Note: ENRX and ENRO are pulled down internally Description standby mode only reference oscillator active entire chip active entire chip active Second Mixer Input IN_MIX2 External LO2 Ext. pull-down res. (15 kΩ) N/C SW_MIX2 0 0 1 Mode double conversion with external LO2 single conversion double conversion with internal LO2 LNA Gain Control VGAIN_LNA Mode < 0.8 V > 1.4 V HIGH GAIN LOW GAIN Description LNA set to high gain by voltage at GAIN_LNA LNA set to low gain by voltage at GAIN_LNA Note: hysteresis between gain modes to ensure stability Absolute Maximum Ratings Parameter Supply voltage Input voltage Input RF level Storage temperature Electrostatic discharge Symbol Vcc VIN Pimax TSTG ESD Condition / Note Min Max Unit 0 - 0.3 -40 7.0 VCC+0.3 10 +125 V V dBm °C -500 -500 +500 +250 V V Min 2.5 2.7 -40 300 ±5 Max 5.5 5.5 +85 450 ±120 40 15 80 Unit V V ºC MHz kHz kbit/s kHz kbit/s no damage human body model, MIL STD 833D method 3015.7, all pins except OUT_IFA pin OUT_IFA Normal Operating Conditions Parameter Supply voltage for double conv. Supply voltage for single conv. Operating temperature Input frequency Frequency deviation FSK data rate FM bandwidth ASK data rate TH7110 Data Sheet 3901007110 Symbol Vcc, DC Vcc, SC Ta fi ∆f RFSK fm RASK Condition at FM or FSK NRZ NRZ Page 9 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver DC Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at Ta = 23 °C and Vcc = 3 V Parameter Symbol Standby current Total supply current at low gain ISBY Icc, low Total supply current at high gain Icc, high Opamp input offset voltage Opamp input offset current Opamp input bias current RSSI voltage at low input level Voffs Ioffs Ibias VRSSI, low RSSI voltage at high input level VRSSI, high Condition ENRX=0 ENRX=1, LNA at LOW GAIN ENRX=1, LNA at HIGH GAIN IOAP – IOAN 0.5 * (IOAP + IOAN) Pi = -65 dBm, LNA at LOW GAIN Pi = -35 dBm, LNA at LOW GAIN Min Typ Max Unit 5.0 6.5 100 8.0 nA mA 6.5 8.2 10.0 mA -20 -50 -100 0.5 1.0 20 50 100 1.5 mV nA nA V 1.25 1.9 2.45 V AC System Characteristics all parameters under normal operating conditions, unless otherwise stated; all parameters based on test circuits for FSK (Fig. 2), FM (Fig. 4) and ASK (Fig. 5), respectively; typical values at Ta = 23 °C and Vcc = 3 V, RF at 433.6 MHz, second IF at 10.7 MHz Parameter Start-up time – fast mode FSK/FM Symbol Tfast Start-up time – slow mode FSK/FM Tslow Start-up time – ASK TASK Input sensitivity – FSK (narrow band) Pmin, n Input sensitivity – FSK (wide band) Pmin, w Input sensitivity – ASK PminA, n (narrow band) Input sensitivity – ASK PminA, w (wide band) Maximum input signal – FSK/FM Pmax, FM Maximum input signal – ASK Pmax, ASK Spurious emission Image rejection Blocking immunity VCO gain Charge pump current Pspur ∆Pimag ∆Pblock KVCO ICP Condition ENRX from 0 to 1, ENRO = 1, valid data at output ENRX from 0 to 1, ENRO = 0, valid data at output depends on ASK detector time constant and start-up mode, valid data at output BIF2 = 40kHz ∆f = ±15kHz (FSK/FM) -3 BER ≤ 3⋅10 BIF2 = 150kHz ∆f = ±50kHz (FSK/FM) -3 BER ≤ 3⋅10 BIF2 = 40kHz -3 BER ≤ 3⋅10 BIF2 = 150kHz -3 BER ≤ 3⋅10 -3 BER ≤ 3⋅10 LNA at LOW GAIN -3 BER ≤ 3⋅10 LNA at LOW GAIN Min Typ Max 0.4 Unit ms 0.9 ms R3•C13 + Tfast (or Tslow) ms -111 dBm -104 dBm -109 dBm -106 dBm 0 dBm -10 dBm -70 ∆fblock > ±2MHz, note 1 65 57 250 60 dBm dB dB MHz/V µA Notes: 1. desired signal with FSK/FM or ASK modulation, CW blocking signal TH7110 Data Sheet 3901007110 Page 10 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Test Circuits FSK Reception C15 C16 C17 VCO2_E VCC VCO2_B C1 OUT_OA OAN OAP RSSI VEE OUTP XTAL VEE OUTN VEE VCC IN_MIX2 SW_MIX2 RO CP VCC C14 VCC IN_DEM VCC OUT_IFA ENRX LF1 VCC LF2 FBC2 VEE FBC1 C13 CERRES VCC R1 C3 C12 C10 LQFP44 VEE VEE C4 L4 VCC VCC IF1N IF1P VEE CAP_MIX1 IN_MIX1 VEE C7 C6 VCC C9 C8 L3 CERFIL OUT_MIX2 LCFIL L1 VREF SAWFIL ENRO VEE VCC L2 OUT_LNA IN_LNA VCC GAIN_LNA C5 C11 IN_IFA L5 CB* VCC Fig. 2: Test circuit for FSK reception TH7110 Data Sheet 3901007110 Page 11 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver FSK test circuit component list to Fig. 2 Part Size Value / Type Tolerance C1 0805 15 pF ±10% C3 0805 1 nF ±10% C4 0603 3.3 pF ±5% C5 0603 3.3 pF ±5% C6 0603 4.7 pF ±5% C7 0603 2.2 pF ±5% C8 0603 330 pF ±10% C9 0603 27 pF ±5% C10 0805 33 nF ±10% C11 0603 1 nF ±10% C12 0603 1 nF ±10% C13 0603 1.5 pF ±5% C14 0603 680 pF ±10% CP 0805 10 –12 pF ±5% C15 0805 10 – 47 pF ±5% C16 0805 10 – 47 pF ±5% C17 0603 330 pF ±10% R1 0805 10 kΩ ±10% L1 0603 33 nH ±5% L2 0603 33 nH ±5% L3 0603 15 nH ±5% L4 0805 100 nH ±5% L5 0805 100 nH ±5% XTAL HC49SMD 23.49444 MHz @ RF = 433.6 MHz SAWFIL QCC8C B3555 @ RF = 433.6 MHz CERFIL leaded type SFE10.7MFP @ BIF2 = 40 kHz SMD type SFECV10.7MJS-A @ BIF2 = 150 kHz SMD type CDACV10.7MG18-A CERRES Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor MIX1 blocking capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor CERRES parallel capacitor demodulator output low-pass capacitor, depending on data rate demodulator output low-pass capacitor, depending on data rate RSSI output low-pass capacitor loop filter resistor inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 Ω ±25ppm calibration ±30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS ±100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata ±40 kHz ceramic demodulator tank from Murata NIP – not in place, may be used optionally TH7110 Data Sheet 3901007110 Page 12 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver FSK Circuit with AFC and Ceramic Resonator Tolerance Compensation C15 C16 C17 C18 C19 R4 R3 VCC VCO2_E VCC VCO2_B C1 OUT_OA OAN OAP RSSI VEE OUTP XTAL VEE OUTN VEE R5 RO IN_MIX2 SW_MIX2 VCC CP VD C14 VCC IN_DEM VCC OUT_IFA ENRX LF1 VCC LF2 FBC2 VEE FBC1 C13 CERRES VCC C12 R1 C3 C10 LQFP44 VEE VEE C4 L4 VCC VCC IF1N IF1P VEE CAP_MIX1 IN_MIX1 VEE C7 C6 VCC C9 C8 L3 CERFIL OUT_MIX2 LCFIL L1 VREF SAWFIL ENRO VEE VCC L2 OUT_LNA IN_LNA VCC GAIN_LNA C5 C11 IN_IFA L5 CB* VCC Fig. 3: Test circuit for FSK with AFC and resonator compensation Circuit Feature ! ! ! ! Improves input frequency acceptance range up to RFnom ±50 kHz Eliminates calibration tolerances of ceramic resonator Eliminates temperature tolerances of ceramic resonator Non-inverted and inverted CMOS-compatible outputs TH7110 Data Sheet 3901007110 Page 13 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver FSK test circuit with AFC component list to Fig. 3 Part Size Value / Type Tolerance C1 0805 15 pF ±10% C3 0805 1 nF ±10% C4 0603 3.3 pF ±5% C5 0603 3.3 pF ±5% C6 0603 4.7 pF ±5% C7 0603 2.2 pF ±5% C8 0603 330 pF ±10% C9 0603 27 pF ±5% C10 0805 33 nF ±10% C11 0603 1 nF ±10% C12 0603 1 nF ±10% C13 0603 1.5 pF ±5% C14 0603 680 pF ±10% CP 0805 27 pF ±5% C15 0805 10 – 47 pF ±5% C16 0805 10 – 47 pF ±5% C17 0603 330 pF ±10% C18 33 nF ±10% C19 0805 33 nF 10 nF 1 nF ±10% R1 0805 0805 10 kΩ ±10% ±10% R3 R4 R5 L1 0805 0805 100 kΩ 680 kΩ 680 kΩ 0603 33 nH ±5% L2 0603 33 nH ±5% L3 0603 15 nH ±5% L4 0805 100 nH ±5% ±5% ±10% ±10% L5 0805 100 nH VD SOD-323 BB535 XTAL HC49SMD 23.49444 MHz @ RF = 433.6 MHz SAWFIL QCC8C B3555 @ RF = 433.6 MHz CERFIL leaded type SFE10.7MFP @ BIF2 = 40 kHz TBD SMD type SFECV10.7MJS-A @ BIF2 = 150 kHz ±40 kHz SMD type CDACV10.7MG18-A CERRES ±25ppm calibration ±30ppm temp. Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor MIX1 blocking capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor ceramic resonator loading capacitor demodulator output low-pass capacitor, depending on data rate demodulator output low-pass capacitor, depending on data rate RSSI output low-pass capacitor integrator capacitor, fixed integrator capacitor, @ 0.5 to 2 kbit/s NRZ integrator capacitor, @ 2 to 20 kbit/s NRZ integrator capacitor, @ 20 to 40 kbit/s NRZ loop filter resistor varactor diode biasing resistor integrator resistor integrator resistor inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor varactor diode from Infineon fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 Ω B3dB = 860 kHz low-loss SAW filter from EPCOS ±100 kHz (f0 = 433.92 MHz) ceramic filter from Murata ceramic demodulator tank from Murata NIP – not in place, may be used optionally TH7110 Data Sheet 3901007110 Page 14 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver FM Reception C15 R6 R5 R4 C17 VCC VCO2_E VCC VCO2_B C1 OUT_OA OAN R3 OAP RSSI VEE VEE OUTP XTAL OUTN VEE C16 IN_MIX2 SW_MIX2 RO CP VCC C14 VCC IN_DEM VCC ENRX OUT_IFA LF1 VCC LF2 FBC2 VEE FBC1 C13 CERRES VCC R1 C3 C12 C10 LQFP44 VEE VEE C4 C7 C6 L4 VCC VCC IF1N IF1P VEE CAP_MIX1 VCC C9 C8 L3 CERFIL OUT_MIX2 LCFIL L1 VREF SAWFIL ENRO IN_MIX1 L2 VEE VCC VEE VCC OUT_LNA IN_LNA GAIN_LNA C5 C11 IN_IFA L5 CB* VCC Fig. 4: Test circuit for FM reception TH7110 Data Sheet 3901007110 Page 15 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver FM test circuit component list to Fig. 4 Part Size Value / Type Tolerance C1 0805 15 pF ±10% C3 0805 1 nF ±10% C4 0603 3.3 pF ±5% C5 0603 3.3 pF ±5% C6 0603 4.7 pF ±5% C7 0603 2.2 pF ±5% C8 0603 330 pF ±10% C9 0603 27 pF ±5% C10 33 nF ±10% C11 0805 0603 1 nF ±10% C12 0603 1 nF ±10% C13 0603 1.5 pF ±5% C14 0603 680 pF ±10% CP 0805 0805 10 – 12 pF ±5% C15 100 pF ±5% C16 0805 100 pF ±5% C17 0603 0805 330 pF ±10% R1 10 kΩ ±10% R3 0805 12 kΩ ±5% R4 0805 6.8 kΩ ±5% R5 0805 33 kΩ ±5% R6 33 kΩ ±5% L1 0805 0603 33 nH ±5% L2 0603 33 nH ±5% L3 0603 15 nH ±5% L4 0603 100 nH ±5% L5 0603 100 nH XTAL HC49SMD 23.49444 MHz @ RF = 433.6 MHz SAWFIL QCC8C B3555 @ RF = 433.6 MHz CERFIL leaded type SFE10.7MFP @ BIF2 = 40 kHz SMD type SFECV10.7MJS-A @ BIF2 = 150 kHz SMD type CDACV10.7MG18-A CERRES ±5% Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor MIX1 blocking capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor CERRES parallel capacitor sallen-Key low-pass filter capacitor, to set cut-off frequency sallen-Key low-pass filter capacitor, to set cut-off frequency RSSI output low-pass capacitor loop filter resistor sallen-key filter resistor, to set desired filter characteristic sallen-key filter resistor, to set desired filter characteristic sallen-key filter resistor, to set cut-off frequency sallen-key filter resistor, to set cut-off frequency inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 Ω ±25ppm calibration ±30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS ±100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata ±40 kHz ceramic demodulator tank from Murata NIP – not in place, may be used optionally TH7110 Data Sheet 3901007110 Page 16 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver ASK Reception R3 C14 RO VCC VCO2_E VCC VCO2_B C1 OUT_OA OAN OAP RSSI VEE OUTP VEE OUTN VEE XTAL VCC C13 IN_MIX2 SW_MIX2 VCC IN_DEM VCC OUT_IFA ENRX LF1 VCC LF2 FBC2 VEE FBC1 VCC C12 R1 C3 C10 LQFP44 VEE VEE C4 L3 L4 VCC VCC IF1N VCC C9 C8 C7 C6 IF1P VEE CAP_MIX1 IN_MIX1 VEE R4 CERFIL OUT_MIX2 LCFIL L1 VREF SAWFIL ENRO VEE VCC L2 OUT_LNA IN_LNA VCC GAIN_LNA C5 C11 IN_IFA L5 CB* VCC Fig. 5: Test circuit for ASK reception TH7110 Data Sheet 3901007110 Page 17 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver ASK test circuit component list to Fig. 5 Part Size Value / Type Tolerance C1 0805 15 pF ±10% C3 0805 1 nF ±10% C4 0603 3.3 pF ±5% C5 0603 3.3 pF ±5% C6 0603 4.7 pF ±5% C7 0603 2.2 pF ±5% C8 0603 330 pF ±10% C9 0805 27 pF ±5% C10 0805 33 nF ±10% C11 0603 1 nF ±10% C12 0603 1 nF ±10% C13 0805 1 nF to 10 nF ±10% C14 0603 330 pF ±10% R1 0805 10 kΩ ±10% R3 0603 100 kΩ ±5% L1 0603 33 nH ±5% L2 0603 33 nH ±5% L3 0603 15 nH ±5% L4 0603 100 nH ±5% L5 0603 100 nH XTAL HC49SMD 23.49444 MHz @ RF = 433.6 MHz SAWFIL QCC8C B3555 @ RF = 433.6 MHz CERFIL leaded type SFE10.7MFP @ BIF2 = 40 kHz SMD type SFECV10.7MJS-A @ BIF2 = 150 kHz ±5% Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor MIX1 blocking capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor ASK data slicer capacitor, depending on data rate RSSI output low-pass capacitor loop filter resistor ASK data slicer resistor, depending on data rate inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 Ω ±25ppm calibration ±30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS ±100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata ±40 kHz NIP – not in place, may be used optionally TH7110 Data Sheet 3901007110 Page 18 of 20 Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Package Dimensions D D1 33 23 34 E 22 E1 e 44 12 1 A A2 b 11 A1 L Fig. 6: LQFP44 (Low Quad Flat Package) All Dimension in mm, coplanaríty < 0.1mm E1, D1 A A1 A2 e b min 0.05 1.35 0.30 10.00 0.8 max 1.60 0.15 1.45 0.45 All Dimension in inch, coplanaríty < 0.004” min 0.002 0.053 0.012 0.394 0.031 max 0.630 0.006 0.057 0.018 TH7110 Data Sheet 3901007110 Page 19 of 20 L 0.45 E, D α 0° 12.00 0.75 7° 0.018 0° 0.472 0.030 7° Nov. 2001 Rev. 005 TH7110 315/433MHz FSK/FM/ASK Receiver Your Notes Important Notice Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services. © 2000 Melexis GmbH. All rights reserved. For the latest version of this document. Go to our website at www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: All other locations: Phone: +32 1361 1631 E-mail: [email protected] Phone: +1 603 223 2362 E-mail: [email protected] QS9000, VDA6.1 and ISO14001 Certified TH7110 Data Sheet 3901007110 Page 20 of 20 Nov. 2001 Rev. 005