19-2269; Rev 3; 11/04 KIT ATION EVALU E L B A AVAIL +3.3V, 2.5Gbps Low-Power Limiting Amplifiers Features The MAX3272/MAX3272A 2.5Gbps limiting amplifiers accept a wide range of input voltages and provide a constant-level output voltage with controlled edge speeds. Additional features include power detectors with programmable loss-of-signal (LOS) indication, an optional squelch function that mutes the data output signal when the input voltage falls below a programmable threshold, and an output polarity selector. These parts exhibit excellent jitter performance and have low power dissipation. The MAX3272/MAX3272A feature current-mode logic (CML) data outputs that are tolerant of inductive connectors, and are available in a 4mm ✕ 4mm QFN package or in die form (MAX3272 only). Along with the MAX3271, the MAX3272/MAX3272A are ideal for lowpower, compact optical receivers. ♦ Single +3.3V Power Supply ♦ 33mA Supply Current ♦ 5ps Deterministic Jitter ♦ 90ps Edge Speed ♦ Output Squelch Function ♦ Programmable Loss-of-Signal Function ♦ CML Output Interface ♦ 20-Pin 4mm ✕ 4mm QFN or Thin QFN Package ♦ Selectable Output Polarity Ordering Information PART Applications TEMP RANGE PINPACKAGE PACKAGE CODE G2044-3 MAX3272EGP -40°C to +85°C 20 QFN Gigabit Ethernet Optical Receivers MAX3272E/D -40°C to +85°C Dice* Fibre Channel Optical Receivers MAX3272AETP+ -40°C to +85°C 20 Thin QFN T2044-3 System Interconnects MAX3272AEGP 20 QFN -40°C to +85°C — G2044-3 + Denotes Lead-Free Package. *Dice are designed and guaranteed to operate from -40°C to +85°C, but are tested only at TA = +25°C. 2.5Gbps Optical Receivers SONET/SDH Receivers Pin Configuration appears at end of data sheet. Typical Operating Circuit CAZ +3.3V +3.3V CAZ1 CAZ2 VCC MAX3272/ MAX3272A OUTPOL +3.3V VCC OUT+ IN+ SDI+ 0.1µF 100Ω 0.1µF MAX3873 IN- OUT- MAX3271 CLOS TH SQUELCH SDO+ SDO- GND LOS LOS SDI- CDR SCLKO+ SCLKOGND LEVEL CCLOS RTH LOSS OF SIGNAL Typical Operating Circuits continue at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3272/MAX3272A General Description MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers ABSOLUTE MAXIMUM RATINGS Continuous Current at CML Outputs (OUT+, OUT-) .........................-25mA to +25mA Continuous Power Dissipation at +85°C 20-Pin Thin QFN (derate 16.9mW/°C above +85°C) ......1.1W 20-Pin QFN (derate 20mW/°C above +85°C) .................1.3W Storage Ambient Temperature Range (TSTG) .................................................-55°C to +150°C Operating Junction Temperature Range (TJ) .....................................................-55°C to +150°C Die Attach Temperature...................................................+400°C Lead Temperature (soldering, 10s) .................................+300°C Power-Supply Voltage (VCC) .................................-0.5V to +6.0V Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) Voltage at SQUELCH, CAZ1, CAZ2, TH, CLOS ...............................................-0.5V to (VCC + 0.5V) Voltage at LOS, LOS (MAX3272)...........................-0.5V to +6.0V Voltage at LOS, LOS (MAX3272A) .............-0.5V to (VCC + 0.5V) Voltage at LEVEL...................................................-0.5V to +2.0V Voltage at OUTPOL ...............................................-0.5V to +6.0V Current into LOS, LOS ..........................................-1mA to +9mA Differential Input Voltage (IN+ - IN-).................................2.5VP-P Continuous Current at IN+, IN- ...........................................50mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Current SYMBOL CONDITIONS ICC (Note 2) VIN Differential MIN Input Data Rate Input Voltage Range (Notes 3, 4, 5) Random Jitter (Notes 4, 6) Data Output Edge Speed (20% to 80%) (Notes 3, 4) RIN Low Frequency Cutoff Output Resistance mA 1200 mVP-P 27 psP-P 5 3 90 130 30mVP-P ≤ VIN ≤ 1200mVP-P 90 115 100 105 IN+ to IN- 95 VOUT PSNR fOC ROUT LEVEL open, RLOAD = 50Ω 550 750 mVP-P mVP-P 30 dB CAZ = open 0.9 MHz CAZ = 0.1µF 1.5 Single ended to VCC 42.5 50 9 Differential Input Return Loss 4.0GHz 10 VIL kHz 57.5 dB 0.8 (Notes 3, 4, 8) 2 3.3 CCLOS = 0.01µF (Notes 3, 9, 10) 2.3 50 RTH = 20kΩ (Notes 3, 10) 4.5 6.5 7.8 12.9 CCLOS = open (Notes 3, 9, 10) RTH = 20kΩ (Notes 3, 10) Medium LOS Assert Level RTH = 1kΩ (Notes 3, 10) Medium LOS Deassert Level RTH = 1kΩ (Notes 3, 10) High LOS Assert Level RTH = 80Ω (Notes 3, 10) 17.4 24.3 48 _______________________________________________________________________________________ V dB 1 9.5 Ω dB 2.4 VIH Low LOS Deassert Level 2 1200 2.2 10 Low LOS Assert Level Ω µVRMS f ≤ 2MHz (Note 7) ≤ 2.5GHz LOS Assert/Deassert Time ps Outputs AC-coupled 2.5GHz to 4.0GHz LOS Hysteresis psRMS 15mVP-P < VIN ≤ 30mVP-P Single-Ended Output Return Loss OUTPOL Input Limits Gbps 220 Output Signal when Squelched Power-Supply Noise Rejection UNITS 44 15 Input-Referred Noise CML Output Voltage MAX 33 2.5 Output Deterministic Jitter Differential Input Resistance TYP 100 µs mVP-P 12.7 mVP-P mVP-P 22.4 mVP-P mVP-P +3.3V, 2.5Gbps Low-Power Limiting Amplifiers (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS High LOS Deassert Level RTH = 80Ω (Notes 3, 10) LOS Output High Voltage Sinking 30µA LOS Output Low Voltage Sourcing 1.2mA MIN TYP MAX UNITS 73 124.7 mVP-P 2.4 V Squelch Input Current 0.4 V 400 µA Dice are designed and guaranteed from -40°C to +85°C but are tested only at TA = +25°C. Supply current measurement excludes the current of the CML output stage (16mA typical). See Figure 1, Power-Supply Current Measurement. Note 3: Guaranteed by design and characterization. Note 4: Input edge speed is controlled using 4-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum data rate. Note 5: Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230, Annex A. Note 6: Random jitter is measured with the minimum input signal. For Fibre Channel and Gigabit Ethernet applications, the peakto-peak random jitter is 14.1 times the RMS random jitter. Note 7: Power-supply noise rejection (PSNR) is calculated by the equation PSNR = 20log (∆VCC/(∆VOUT)), where ∆VOUT is the change in differential output voltage due to the power-supply noise, ∆VCC. See Power-Supply Noise Rejection vs. Frequency in the Typical Operating Characteristics. Note 8: Hysteresis is defined as: 20 ✕ log(VLOS-DEASSERT/VLOS-ASSERT). Note 9: Response time to a 10dB change in input power. For the specification guaranteed, the power is assumed to switch back and forth between two levels (separated by 10dB and equidistant from assert and deassert levels) outside of the two hysteresis thresholds. Note 10: All power-detect AC parameters are guaranteed with a 223 - 1 PRBS, 2.5Gbps input, with the longest possible run of 80CID. Note 1: Note 2: Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. AMBIENT TEMPERATURE 60 850 800 LEVEL = OPEN 750 700 55 50 45 40 35 30 650 25 600 20 0 10 20 30 VIN (mVP-P) 40 50 20 MAX3272 toc03 65 SUPPLY CURRENT (mA) VOUT (mVP-P) 900 MAX3272 toc02 LEVEL = GND 950 70 MAX3272 toc01 1000 DETERMINISTIC JITTER vs. INPUT AMPLITUDE 18 DETERMINISTIC JITTER (psP-P) OUTPUT AMPLITUDE vs. INPUT AMPLITUDE 16 14 12 10 8 6 4 2 0 -40 -15 10 35 60 AMBIENT TEMPERATURE (°C) 85 1 10 100 1000 10,000 INPUT AMPLITUDE (mVP-P) _______________________________________________________________________________________ 3 MAX3272/MAX3272A ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) LOS HYSTERESIS vs. AMBIENT TEMPERATURE 7 4.5 HYSTERESIS (dB) 6 5 4 3 2 VIN 4.0 RTH = 80Ω VOUT 3.5 3.0 RTH = 20kΩ VLOS RTH = 1kΩ 2.5 1 CCLOS = 0.01µF 2.0 0 10 100 1000 10,000 10 35 60 AMBIENT TEMPERATURE (°C) LOSS OF SIGNAL TRESHOLD vs. RTH DATA OUTPUT EYE DIAGRAM (MINIMUM INPUT) XXXXXXXX 50 45 85 20µs/div DATA OUTPUT EYE DIAGRAM (MAXIMUM INPUT) 2.5Gbps 223 -1 PRBS 15mVP-P INPUT 40 LOS ASSERT (mV) -15 -40 INPUT AMPLITUDE (mVp-p) MAX3272 toc08 1 MAX3272 toc09 RANDOM JITTER (psRMS) 8 MAX3272 toc05 9 LOSS-OF-SIGNAL WITH SQUELCH 5.0 MAX3272 toc04 10 MAX3272 toc06 RANDOM JITTER vs. INPUT AMPLITUDE 2.5Gbps 223 -1 PRBS 1200mVP-P INPUT 35 30 150mV/ div 150mV/ div 25 20 15 10 5 0 10 100 1k 10k 100k 100ps/div 100ps/div 1M RTH (Ω) INPUT RETURN LOSS vs. FREQUENCY 30 20 35 30 25 20 15 10 10 5 10k 100k FREQUENCY (Hz) 1M 10M 40 35 30 25 20 15 10 5 0 1k 45 OUTPUT RETURN LOSS (dB) 40 OUTPUT RETURN LOSS vs. FREQUENCY MAX3272 toc11 40 INPUT RETURN LOSS (dB) 50 0 4 45 MAX3272 toc10 60 MAX3272 toc12 POWER-SUPPLY NOISE REJECTION vs. FREQUENCY POWER-SUPPLY NOISE REJECTION (dB) MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers 0 10M 100M 1G FREQUENCY (Hz) 10G 10M 100M 1G FREQUENCY (Hz) _______________________________________________________________________________________ 10G +3.3V, 2.5Gbps Low-Power Limiting Amplifiers COMMON-MODE REJECTION RATIO vs. FREQUENCY 18.5 MAX3272 toc14 12 MAX3272 toc13 10 18.0 DEASSERT 8 17.5 VIN (mVP-P) COMMON-MODE REJECTION RATIO (dB) 19.0 LOS ASSERT AND DEASSERT LEVELS vs. DATA RATE 17.0 16.5 6 ASSERT 4 16.0 223 - 1 PRBS PATTERN RTH = 20kΩ CIN = 0.1µF 2 15.5 15.0 0 100k 1M 10M FREQUENCY (Hz) 100M 0 500 1000 1500 2000 2500 DATA RATE (Mbps) Pin Description PIN NAME 1, 4, 17 GND Supply Ground FUNCTION 2 IN+ Noninverted Input Signal 3 IN- Inverted Input Signal 5 TH Loss-of-Signal Threshold Pin. Resistor to ground sets the LOS threshold. 6, 12, 15, 20 VCC Power Supply 7 CLOS LOS Time-Constant Capacitor Connection. For SONET applications, CCLOS = 0.01µF is recommended. 8 SQUELCH Squelch Input. The squelch function is disabled when SQUELCH is not connected or set to TTL low level. When SQUELCH is set to TTL high level and LOS is asserted, the data outputs (OUT+, OUT-) are forced to static levels. 9 LOS Noninverted Loss-of-Signal Output. LOS is asserted TTL high when the signal drops below the assert threshold set by the TH input. The MAX3272 does not have ESD protection on this pin. The MAX3272A has ESD protection on this pin. 10 LOS Inverted Loss-of-Signal Output. LOS is asserted TTL low when the signal drops below the assert threshold set by the TH input. The MAX3272 does not have ESD protection on this pin. The MAX3272A has ESD protection on this pin. 11 LEVEL Output Current Level. When this pin is not connected, the CML output current is approximately 16mA. When this pin is connected to ground, the output current increases to about 20mA. 13 OUT- Inverted Data Output 14 OUT+ Noninverted Data Output Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting amplifier and connect to VCC for normal operation. 16 OUTPOL 18 CAZ2 Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ1 extends the time constant of the offset correction loop. Typical value of CAZ is 0.1µF. 19 CAZ1 Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ2 extends the time constant of the offset correction loop. Typical value of CAZ is 0.1µF. EP EXPOSED PAD Connect the exposed paddle to board ground for optimal electrical and thermal performance. _______________________________________________________________________________________ 5 MAX3272/MAX3272A Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers Detailed Description VCC Figure 2 is a functional diagram of the MAX3272/ MAX3272A, comprising a CML input buffer, power detector and loss-of- signal indicators, gain stage, offsetcorrection loop, and CML output buffer. ICC IOUT 50Ω CML Input Buffer 50Ω The input buffer (Figure 3) provides 100Ω input impedance between IN+ and IN-. DC-coupling the inputs is not recommended; this prevents the DC offset-correction circuitry from functioning properly. Power Detect and Loss-of-Signal Indicator SQUELCH OPEN The MAX3272/MAX3272A are equipped with loss-of-signal (LOS) circuitry that indicates when the input signal is below a programmable threshold, set by resistor RTH at the TH pin (see the Typical Operating Characteristics for appropriate resistor selection). An averaging peakpower detector compares the input signal amplitude with this threshold and feeds the signal-detect information to the LOS outputs, which are internally terminated to 8kΩ (Figure 4). CONTROL MAX3272/ MAX3272A LEVEL OPEN RTH CML SUPPLY CURRENT (ICC) Figure 1. Power-Supply Current Measurement TH MAX3272/ MAX3272A CLOS TTL LOS TTL LOS POWER DETECTOR CONTROL POWER DETECTOR AND LOS INDICATOR SQUELCH IN+ 100Ω CML INPUT BUFFER CML OUTPUT BUFFER OUT+ OUT- IN- LOWPASS FILTER OUTPOL OFFSET CORRECTION 0.1µF CAZ1 CAZ2 Figure 2. Functional Diagram 6 LEVEL _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Limiting Amplifiers VCC VCC 540Ω 540Ω 0.25pF IN+ 8kΩ 110Ω LOS IN0.25pF ESD STRUCTURE ESD STRUCTURES GND Figure 4a. LOS Output Circuit for MAX3272 VCC GND Figure 3. Input Circuit Two control voltages VASSERT, and VDEASSERT, define the LOS assert and deassert levels. To prevent LOS chatter in the region of the programmed threshold, approximately 3.3dB of hysteresis is built into the LOS assert/deassert function. Once asserted, LOS is not deasserted until the input amplitude rises to the required level (VDEASSERT). To facilitate interfacing with +5V modules, the LOS and LOS pins on the MAX3272 do not have internal ESD protection. If ESD protection is desired, a low-capacitance Schottky diode or diode array structure, such as the MAX3202E, is recommended (see the Typical Operating Circuits). The LOS and LOS pins on the MAX3272A include ESD protection and, as a result, cannot be interfaced with +5V modules. Gain Stage The high-bandwidth gain stage provides approximately 42dB of gain. 8kΩ LOS ESD STRUCTURE GND Figure 4b. LOS Output Circuit for MAX3272A Offset-Correction Loop Due to the high gain of the amplifier, the MAX3272/ MAX3272A are susceptible to DC offsets in the signal path. In communications systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated by the transimpedance amplifier appears as input offset and is removed by the offsetcancellation loop. An external capacitor is required between CAZ1 and CAZ2 to decouple the offset-cancellation loop and determine the lower 3dB frequency of the signal path. _______________________________________________________________________________________ 7 MAX3272/MAX3272A Interface Schematics MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers Design Procedure VCC ESD STRUCTURES 50Ω 50Ω OUT+ Program the LOS Assert Threshold External resistor R TH programs the loss-of-signal threshold. See the LOS Threshold vs. RTH graph in the the Typical Operating Characteristics section to select the appropriate resistor. Select the Coupling Capacitors OUT- GND Select the Offset-Correction Capacitor LEVEL Figure 5. CML Output Circuit CML Output Buffer The MAX3272/MAX3272A CML output circuit (Figure 5) provides high tolerance to impedance mismatches and inductive connectors. The output current can be set to two levels using the LEVEL pin. When LEVEL is unconnected, the output current is approximately 16mA. Connecting LEVEL to ground sets the output current to approximately 20mA. The squelch function is enabled when the SQUELCH pin is set to a TTL high. This function holds OUT+ and OUT- to a static level whenever the input signal amplitude drops below the loss-of-signal threshold. This circuit is also equipped with a polarity selector, programmed by the OUTPOL pin. When this pin is connected to VCC, no inversion will occur. When connected to ground, the output signal will be inverted. 8 When AC-coupling, input and output coupling capacitors (CIN and COUT) should be selected to minimize the receiver’s deterministic jitter. Jitter is decreased as the input low-frequency cutoff (fIN) is decreased: fIN = 1 / [2π(50)(CIN)] For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) ≥ 0.1µF, which provides fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) ≥ 0.01µF, which provides fIN < 320kHz. Refer to application note HFAN-1.1: Choosing ACCoupling Capacitors. The capacitor between CAZ1 and CAZ2 determines the time constant of the signal path DC offset-cancellation loop. To maintain stability, it is important to keep a onedecade separation between fIN and the low-frequency cutoff (fOC) associated with the DC offset-cancellation circuit. For ATM/SONET or other applications using scrambled NRZ data, f IN < 32kHz, so f OCMAX < 3.2kHz. Therefore, CAZ = 0.1µF (fOC = 2kHz). For Fibre Channel or Gigabit Ethernet applications, leave pins CAZ1 and CAZ2 open. Program the LOS Time Constant External capacitor CCLOS programs the LOS assert and deassert times. When inputting data with many consecutive identical digits (CIDs), a longer time constant may be advantageous, so LOS does not flag incorrectly. In this case, connect the CLOS pin to a 0.01µF capacitor to set the assert time in the range of 2µs to 100µs. For scrambled data where the mark density is kept at 50%, a shorter time constant may be desirable. Leave the CLOS pin open for a shorter time constant of about 1µs. _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Limiting Amplifiers VCC CAZ1 CAZ2 GND OUTPOL TOP VIEW 20 19 18 17 16 GND 1 15 VCC IN+ 2 14 OUT+ TH 5 VCC 6 7 8 9 13 OUT- 12 VCC 11 LEVEL 10 LOS 4 LOS GND MAX3272/ MAX3272A SQUELCH 3 CLOS IN- QFN* VCC CAZ1 CAZ2 GND OUTPOL NOTE: EXPOSED PAD MUST BE CONNECTED TO SUPPLY GROUND. 20 19 18 17 16 PAD NAME COORDINATES (µm) 1 GND 47, 836 2 IN+ 47, 603 3 IN- 47, 425 4 GND 47, 237 5 TH 47, 47 6 VCC 255, -154 7 CLOS 436, -154 8 SQUELCH 645, -154 9 LOS 850, -154 10 LOS 1063, -154 11 LEVEL 1331, 37 12 VCC 1331, 212 13 OUT- 1331, 421 14 OUT+ 1331, 573 15 VCC 1331, 780 16 OUTPOL 1119, 1042 17 GND 957, 1042 18 CAZ2 773, 1042 19 CAZ1 583, 1042 20 N.C. 422, 1042 21 VCC 268, 1042 Coordinates are for the center of the pad. Coordinate 0, 0 is the lower left corner of the passivation opening for pad 5. 15 VCC 2 14 OUT+ IN- 3 13 OUT- GND 4 12 VCC TH 5 11 LEVEL VCC 6 7 8 9 10 LOS MAX3272A LOS IN+ + SQUELCH 1 CLOS GND THIN QFN* NOTE: EXPOSED PAD MUST BE CONNECTED TO SUPPLY GROUND. Applications Information Optical Hysteresis In an optical receiver, the electrical power change at the limiting amplifier is 2 times the optical power change. As an example, if a receiver’s optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage input to the limiting amplifier also increases by a factor of two. The optical power change is 10log(2x / x) = 10log(2) = +3dB. At the limiting amplifier, the electrical power change is: 10log (2VIN )2 / RIN VIN2 / RIN = 10log(22 ) = 20log(2) = + 6dB The MAX3272 typical voltage hysteresis is 3.3dB. This provides an optical hysteresis of 1.65dB. _______________________________________________________________________________________ 9 MAX3272/MAX3272A Pad Coordinates Pin Configuration +3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Typical Operating Circuit (continued) CAZ +3.3V +3.3V CAZ1 CAZ2 VCC MAX3272 OUTPOL +3.3V VCC OUT+ IN+ SDI+ SDO+ SDO- 0.1µF 100Ω 0.1µF MAX3873 IN- OUT- MAX3271 CLOS TH SQUELCH GND LOS LOS CDR SCLKO+ SCLKOGND SDI- LEVEL +3.3V CCLOS VCC RTH LOSS OF SIGNAL I/01 MAX3202E* *THE MAX3202E PROVIDES ESD PROTECTION ON THE LOS PIN Wire Bonding Die For high-current density and reliable operation, the MAX3272 uses gold metallization. Make connections to the dice with gold wire only, and use ball-bonding techniques (wedge bonding is not recommended). Die pad dimensions are 94.4 microns by 94.4 microns. Die thickness is 15 mils (0.375mm). 10 ______________________________________________________________________________________ GND +3.3V, 2.5Gbps Low-Power Limiting Amplifiers VCC (PAD 21) N.C. (PAD 20) CAZ1 (PAD 19) CAZ2 (PAD 18) GND (PAD 17) OUTPOL (PAD 16) GND (PAD 1) VCC (PAD 15) IN+ (PAD 2) OUT+ (PAD 14) IN(PAD 3) OUT(PAD 13) GND (PAD 4) 62 mils 1.57mm VCC (PAD 12) TH (PAD 5) LEVEL (PAD 11) VCC (PAD 6) CLOS (PAD 7) SQUELCH (PAD 8) LOS (PAD 9) LOS (PAD 10) 66 mils 1.68mm TRANSISTOR COUNT: 726 PROCESS: SiGe Bipolar SUBSTRATE: Insulator, Connect to GND DIE SIZE: 1.68mm ✕ 1.57mm DIE THICKNESS: 15 mils ______________________________________________________________________________________ 11 MAX3272/MAX3272A Chip Information Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12,16,20, 24L QFN.EPS MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM 21-0106 12 ______________________________________________________________________________________ E 1 2 +3.3V, 2.5Gbps Low-Power Limiting Amplifiers PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM 21-0106 E 2 2 ______________________________________________________________________________________ 13 MAX3272/MAX3272A Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 1 2 PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.