INTEGRATED CIRCUITS 74LV595 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) Product specification IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) FEATURES 74LV595 APPLICATIONS • Optimized for Low Voltage applications: 1.0V to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, • Serial-to-parallel data conversion • Remote control holding register DESCRIPTION Tamb = 25°C The 74LV595 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT595. • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, Tamb = 25°C The74LV595 is an 8-stage serial shift register with a storage register and 3-State outputs. The shift register and storage register have separate clocks. • 8-bit serial input • 8-bit serial or parallel output • Storage register with 3-State outputs • Shift register with direct clear • Output capability: Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. – parallel outputs; bus driver – serial output; standard The shift register has a serial input (DS) and a serial standard output (Q7’) all for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-State bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. • ICC category: MSI QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns SYMBOL PARAMETER CONDITIONS CL = 15pF VCC= 3.3V TYPICAL UNIT tPHL/tPLH Propagation delay SHCP to Q7’ STCP to Q7’ MR to Q7’ fmax Maximum clock frequency SHCP, STCP 77 MHz CI Input capacitance 3.5 pF CPD Power dissipation capacitance per gate 115 pF VCC = 3.3V Notes 1 and 2 15 16 14 ns NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING AND PACKAGE INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL PACKAGES –40°C to +125°C 74LV595 N 74LV595 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV595 D 74LV595 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV595 DB 74LV595 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV595 PW 74LV595PW DH SOT403-1 1998 Apr 20 2 853-1987 19255 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) PIN DESCRIPTION PIN NUMBER SYMBOL 15, 1, 2, 3, 4, 5, 6, 7 Q0 to Q7 8 GND 9 Q7’ 74LV595 PIN CONFIGURATION FUNCTION Parallel data output Q1 1 16 VCC Ground (0V) Q2 2 15 Q0 Serial data output Q3 3 14 DS Master reset (active LOW) Q4 4 13 OE Q5 5 12 STCP Q6 6 11 SHCP Q7 7 10 MR 10 MR 11 SHCP Shift register clock input 12 STCP Storage register clock input 13 OE Output enable input (active LOW) 14 DS Serial data input 16 VCC Positive supply voltage GND 8 9 Q7’ SV00720 FUNCTION TABLE INPUTS OUTPUTS FUNCTION SHCP STCP OE MR DS Q7’ Qn X X L L X L NC A LOW level on MR only affects the shift registers X L L X L L Empty shift register loaded into storage register X X H L X L Z Shift register clear. Parallel outputs in high-impedance OFF-states X L H H Q6’ NC Logic high level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’) X L H X NC Qn’ Contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages L H X Q6’ Qn’ Contents of shift register shifted through. Previous contents of the shift register are transferred to the storage register and the parallel output stages H = HIGH voltage level L = LOW voltage level X = Don’t care Z = High impedance OFF-state NC= No change = LOW-to-HIGH clock transition ↓ = HIGH-to-LOW transition 1998 Apr 20 3 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) LOGIC SYMBOL 74LV595 FUNCTIONAL DIAGRAM 11 12 SHCP STCP DS Q7’ 9 Q0 15 14 11 10 Q1 1 Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 SHCP 8–STAGE SHIFT REGISTER MR Q7’ STCP 14 DS MR OE 10 13 REGISTER 13 10 11 SV00723 14 SRG8 C1/ 1D 2D 3 15 1 2 3 4 5 6 7 9 SV00724 1998 Apr 20 Q1 1 Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 SV00725 C2 R 3–STATE OUTPUTS 15 EN3 12 OE Q0 LOGIC SYMBOL (IEEE/IEC) 13 8–BIT STORAGE 12 4 9 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 LOGIC DIAGRAM STAGE 0 DS D STAGE 7 STAGES 1 to 6 Q D Q FFO D Q Q7’ FF7 CP CP R R SHCP MR D Q D Q LATCH LATCH CP CP STCP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SV00721 TIMING DIAGRAM SHCP DS STCP MR OE Z–state Q0 Z–state Q1 Z–state Q6 Z–state Q7 Q7’ SV00726 1998 Apr 20 5 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. MAX UNIT See Note1 1.0 3.3 3.6 V 0 – VCC V 0 – VCC V +85 +125 °C 500 200 100 ns/V DC supply voltage VI Input voltage VO Output voltage Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC =3.6V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER VCC DC supply voltage CONDITIONS RATING UNIT –0.5 to +4.6 V ±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA ±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA ±IO DC output source or sink current – standard outputs – bus driver outputs –0.5V < VO < VCC + 0.5V 25 35 mA 50 70 mA –65 to +150 °C ±IGND, ±ICC Tstg PTOT DC VCC or GND current for types with –standard outputs –bus driver outputs Storage temperature range Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage HIGH level output voltage; all outputs VOH HIGH level output voltage; STANDARD outputs 1998 Apr 20 -40°C to +125°C MAX MIN VCC = 1.2V 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 2.8 3.0 2.8 VCC = 3.0V;VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 6 UNIT MAX VCC = 1.2V VCC = 1.2V; VI = VIH or VIL; –IO = 100µA VOH TYP1 V V Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 DC CHARACTERISTICS (Continued) Over recommended operating conditions voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER VOH HIGH level output voltage; BUS driver outputs LIMITS TEST CONDITIONS -40°C to +85°C VCC = 3.0V;VI = VIH or VIL; –IO = 8mA 2.40 -40°C to +125°C 2.82 2.20 UNIT V VCC = 1.2V; VI = VIH or VIL; IO = 100µA VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VOL LOW level output voltage; all outputs VOL LOW level output voltage; STANDARD outputs VCC = 3.0V;VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 V VOL LOW level output voltage; BUS driver outputs VCC = 3.0V;VI = VIH or VIL; IO = 8mA 0.20 0.40 0.50 V Input leakage current VCC = 3.6V; VI = VCC or GND 1.0 1.0 µA IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND 5 10 µA ICC Quiescent supply current; MSI VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA II V NOTE: 1. All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM tPHL/tPLH Propagation delay g y SHCP to Q7’ Figure 1 tPHL/tPLH Propagation delay g y STCP to Qn Figure 2 tPHL Propagation g delay y MR to Q7’ Figure 5 tPZH/tPZL 3-State 3 St t output t t enable time OE to Qn Figure 3 tPHZ/tPLZ 3-State 3 St t output t t disable time OE to Qn Figure 3 1998 Apr 20 LIMITS –40 to +85 °C CONDITION VCC(V) 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 7 MIN – – – – – – – – – – – – – – – – – – – – TYP1 95 32 24 182 100 34 25 192 85 29 21 162 85 29 21 162 65 24 18 142 LIMITS –40 to +125 °C MAX – 61 45 36 – 65 48 38 – 56 41 33 – 56 41 33 – 40 32 26 MIN – – – – – – – – – – – – – – – – – – – – MAX – 75 55 44 – 77 56 45 – 66 49 33 – 66 49 39 – 49 37 30 UNIT ns ns ns ns ns Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 AC CHARACTERISTICS (Continued) GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM tW Shift clock pulse width HIGH or LOW Figure 1 tW Storage clock pulse width HIGH or LOW Figure 2 tW Master reset pulse width LOW Figure 5 tsu Set-up time DS to SHCP Figure 4 tsu Set-up time SHCP to STCP Figure 2 th Hold time DS to SHCP Figure 4 trem Removal time MR to SHCP Figure 5 fmax Maximum clock pulse frequency SHCP or STCP Figure 1, 2 VCC(V) 2.0 2.7 3.0 to 3.6 2.0 2.7 3.0 to 3.6 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 2.0 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 1998 Apr 20 LIMITS –40 to +85 °C CONDITION 8 MIN 34 25 20 34 25 20 34 25 20 – 26 19 15 – 26 19 15 – 5 5 5 – 5 5 5 14 19 24 TYP1 10 8 62 7 5 42 10 8 62 40 14 10 82 40 14 10 82 –10 –4 –3 –22 –35 –12 –9 –72 40 58 702 LIMITS –40 to +125 °C MAX – – – – – – – – – – – – – – – – – – – – – – – – – – – – MIN 41 30 24 41 30 24 41 30 24 – 31 23 18 – 31 23 18 – 5 5 5 – 5 5 5 12 16 20 MAX – – – – – – – – – – – – – – – – – – – – – – – – – – – – UNIT ns ns ns ns ns ns ns MHz Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 AC WAVEFORMS VM = 1.5V at VCC 2.7V VM = 0.5 * VCC at VCC 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC ≥ 2.7V VX = VOL + 0.1VCC at VCC < 2.7V VY = VOH – 0.3V at VCC 2.7V VY = VOH – 0.1VCC at VCC < 2.7V VI OE INPUT VM GND tPLZ tPZL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL 1/fmax tPZH tPHZ VI CP INPUT VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VM GND tW VY VM GND outputs enabled tPLH tPHL outputs disabled outputs enabled VOH Qn OUTPUT SV00344 VM Figure 3. 3-State enable and disable times for input OE. VOL SV00718 Figure 1. Clock (SHCP) to output (Q7’), propagation delays, the shift clock pulse width and the maximum shift clock frequency. VI SHCP INPUT GND ÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏÏ VM DS INPUT tsu th VM GND 1/fmax VI GND t su VI GND STCP INPUT t su th VI SHCP INPUT VM vOH VM Q7’ OUTPUT VM tW VOL tPHL tPLH VOH Qn OUTPUT VM SV00722 VOL Figure 4. Data set-up and hold times for the data input (DS). SV00727 Figure 2. Storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. 1998 Apr 20 9 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) AC WAVEFORMS (Continued) 74LV595 TEST CIRCUIT VM = 1.5V at VCC 2.7V VM = 0.5 * VCC at VCC 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC ≥ 2.7V VX = VOL + 0.1VCC at VCC < 2.7V VY = VOH – 0.3V at VCC 2.7V VY = VOH – 0.1VCC at VCC < 2.7V S1 VCC RL = 1k VO VI PULSE GENERATOR 2 * VCC Open GND D.U.T. 50pF RT CL RL = 1k Test Circuit for switching times DEFINITIONS VI RL = Load resistor MR INPUT VM CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. GND tW SWITCH POSITION trem VI TEST SHCP INPUT GND tPLH/tPHL VM tPHL VOH Q7’ OUTPUT Open tPLZ/tPZL 2 VCC tPHZ/tPZH GND VCC VI < 2.7V VCC 2.7–3.6V 2.7V SV00895 VM Figure 6. Load circuitry for switching times. VOL SV00728 Figure 5. Master reset (MR) pulse width, the master reset to output (Q7’) propagation delay and the master reset to shift clock (SHCP) removal time. 1998 Apr 20 S1 10 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) DIP16: plastic dual in-line package; 16 leads (300 mil) 1998 Apr 20 11 74LV595 SOT38-4 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 Apr 20 12 74LV595 SOT109-1 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 Apr 20 13 74LV595 SOT338-1 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 Apr 20 14 74LV595 SOT403-1 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) NOTES 1998 Apr 20 15 74LV595 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Apr 20 16 Date of release: 05-96 9397-750-04455