19-1996; Rev 1; 12/01 KIT ATION EVALU E L B AVAILA +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery Features ♦ Single +3.3V Supply ♦ 530mW Operating Power ♦ Fully Integrated Clock Recovery and Data Retiming ♦ Exceeds ANSI, ITU, and Bellcore Specifications ♦ Additional High-Speed Input Facilitates System Loopback Diagnostic Testing ♦ 2.488Gbps Serial to 155Mbps Parallel Conversion ♦ Differential PECL Clock Output ♦ Single-Ended PECL Data Outputs ♦ Tolerates >2000 Consecutive Identical Digits ♦ Loss-of-Lock Indicator Ordering Information PART MAX3881ECB TEMP. RANGE -40°C to +85°C PIN-PACKAGE 64 TQFP-EP* *Exposed pad Applications Typical Application Circuit appears at end of data sheet. VCC VCC VCC GND PD11 PD12 PD13 VCC 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCC 64 VCC GND PD14 PD15 LOL Digital Cross-Connects GND TOP VIEW GND 2.488Gbps SDH/SONET Transmission Systems Add/Drop Multiplexers Pin Configuration GND 1 48 VCC FIL+ 2 47 PD10 FIL- 3 46 VCC VCC 4 45 PD9 PHADJ+ 5 44 VCC PHADJ- 6 43 PD8 VCC 7 42 VCC SDI+ 8 41 GND 40 VCC MAX3881 SDI- 9 VCC 10 39 PD7 SLBI+ 11 38 VCC SLBI- 12 37 PD6 VCC 13 36 VCC SIS 14 35 PD5 GND 15 34 VCC GND 16 33 GND VCC PD4 VCC PD3 VCC PD2 VCC GND VCC PD1 VCC PD0 VCC PCLK- GND PCLK+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TQFP-EP* *EXPOSED PAD IS CONNECTED TO GND. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3881 General Description The MAX3881 deserializer with clock recovery is ideal for converting 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data for SDH/SONET applications. Operating from a single +3.3V supply, this device accepts high-speed serial-data inputs and delivers single-ended PECL parallel data outputs and a differential PECL parallel clock output for interfacing with digital circuitry. The MAX3881 includes a low-power clock recovery and data retiming function for 2.488Gbps applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input; the signal is then retimed by the recovered clock. The MAX3881’s jitter performance exceeds all SDH/SONET specifications. An additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTL-compatible loss-of-lock (LOL) monitor. The MAX3881 is available in the extended temperature range (-40°C to +85°C) in a 64-pin TQFP-EP package. MAX3881 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (VCC)...............................-0.5V to +7.0V Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-) ...............................(VCC - 0.5V) to (VCC + 0.5V) Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA Voltage at LOL, SIS, PHADJ+, PHADJ-, FIL+, FIL- .................................................-0.5V to (VCC + 0.5V) PECL Output Current ..........................................................50mA Continuous Power Dissipation (TA = +85°C) 64-Pin TQFP (derate 33.3mW/°C above +85°C)............1.44W Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, PECL loads = 50Ω to (VCC - 2V), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER Supply Current SYMBOL ICC CONDITIONS MIN Excluding PECL outputs TYP MAX UNITS 160 240 mA 800 mVp-p SERIAL DATA INPUTS (SDI±, SLBI±) Differential Input Voltage VID Single-Ended Input Voltage VIS Input Termination to VCC RIN Figure 1 50 VCC - 0.4 Figure 2 VCC + 0.2 V Ω 50 PECL OUTPUTS (PD_, PCLK±) PECL Output High Voltage PECL Output Low Voltage TA = 0°C to +85°C VCC 1.025 VCC 0.88 TA = -40°C to 0°C VCC 1.085 VCC 0.88 TA = 0°C to +85°C VCC 1.81 VCC 1.62 TA = -40°C to 0°C VCC 1.83 VCC 1.555 VOH VOL V V TTL INPUTS AND OUTPUTS (SIS, LOL) Input High Voltage VIH Input Low Voltage VIL 2.0 Input Current Output High Voltage VOH IOH ≤ 40µA Output Low Voltage VOL IOL ≤ 1mA 2 V 0.8 V -10 +10 µA 2.4 VCC V 0.4 V _______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery (VCC = +3.0V to +3.6V, PECL loads = 50Ω to (VCC - 2V), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1) PARAMETER Serial Data Rate SYMBOL CONDITIONS MIN SDI Parallel Output Data Rate Parallel Clock-to-Data Output Delay tCLK-Q Jitter Tolerance MAX 155.52 Mbps 200 450 f = 70kHz (Note 2) 2.31 3.3 f = 100kHz 1.74 2.41 f = 1MHz 0.38 0.57 f = 10MHz 0.28 0.46 900 >2,000 Input Return Loss (SDI±, SLBI±) tR, tF UNITS Gbps Figure 2 Tolerated Consecutive Identical Digits Output Edge Speed TYP 2.488 100kHz to 2.5GHz -18 2.5GHz to 4.0GHz -11 20% to 80% 800 ps UIp-p Bits dB ps Note 1: AC characteristics are guaranteed by design and characterization. Note 2: At jitter frequencies <70kHz, the jitter tolerance of the MAX3881 outperforms the ITU/Bellcore specifications. SDI+ 25mV MIN 400mV MAX SDI- PCLK tCLK-Q (SDI+) - (SDI-) VID Figure 1. Input Amplitude 50mVp-p MIN 800mVp-p MAX PD0–PD15 Figure 2. Timing Parameters _______________________________________________________________________________________ 3 MAX3881 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 180 170 CF = 0.1µF INPUT JITTER (UIp-p) 190 SUPPLY CURRENT (mA) CLOCK 10.0 MAX3881-02 MAX3881-01 223 - 1 PATTERN DATA JITTER TOLERANCE SUPPLY CURRENT vs. TEMPERATURE 200 VCC = +3.6V 160 MAX3881 toc03 RECOVERED DATA AND CLOCK CF = 1.0µF 1.0 VCC = +3.0V 150 0.1 140 JITTER FREQUENCY = 5MHz 0.5 0.4 0.3 10-5 10-6 10-7 10-10 0 10 100 INPUT VOLTAGE (mVp-p) 1000 8.0 8.5 9.0 9.5 INPUT VOLTAGE (mVp-p) 10 100 10-9 0.1 4 75 10-8 SONET SPEC 0.2 50 10-4 BIT ERROR RATIO 0.7 0.6 PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE 25 MAX3881-05 JITTER FREQUENCY = 1MHz 0.8 BIT ERROR RATIO vs. INPUT VOLTAGE 0 10-3 MAX3881 toc04 1 1,000 100 JITTER FREQUENCY (kHz) -25 10 10,000 700 MAX3881-06 JITTER TOLERANCE vs. INPUT VOLTAGE 0.9 TEMPERATURE (°C) -50 PCLK TO DATA OUTPUT PROPAGATION DELAY (ps) 1.64ns/div JITTER TOLERNCE (UIp-p) MAX3881 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery 600 500 400 300 200 -50 -25 0 25 50 TEMPERATURE (°C) _______________________________________________________________________________________ 75 100 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery PIN NAME FUNCTION 1, 15, 16, 17, 25, 33, 41, 49, 57, 62, 64 GND Ground 2 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 3 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 4, 7, 10, 13, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60 VCC +3.3V Supply Voltage 5 PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 6 PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 8 SDI+ Positive Serial Data Input. 2.488Gbps data stream. 9 SDI- Negative Serial Data Input. 2.488Gbps data stream. 11 SLBI+ Positive System Loopback Input. 2.488Gbps data stream. 12 SLBI- Negative System Loopback Input. 2.488Gbps data stream. 14 SIS 18 PCLK+ Positive Parallel Clock PECL Output 19 PCLK- Negative Parallel Clock PECL Output 21, 23, 27, 29, 31, 35, 37, 39, 43, 45, 47, 51, 53, 55, 59, 61 PD0 to PD15 63 LOL EP Exposed Pad Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input (SLBI). Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK signal (Figure 2). Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pullup resistor). The LOL monitor is valid only when a data stream is present on the inputs to the MAX3881. Ground. This must be soldered to a circuit board for proper electrical and thermal performance (see Package Information). _______________________________________________________________________________________ 5 MAX3881 Pin Description MAX3881 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery PHADJ+ PHADJ- FIL+ FIL- VCC 50Ω Q D SDI+ CK PECL PD15 PECL PD1 PECL PD0 AMP SDI0 MUX SLBI+ I 0 PHASE & FREQUENCY DETECTOR LOOP FILTER VCO 16-BIT DEMULTIPLEXER AMP SLBI- I 50Ω VCC SIS MAX3881 PCLK+ CLOCK DIVIDER PECL PCLK- TTL LOL Figure 3. MAX3881 Functional Diagram Detailed Description The MAX3881 deserializer with clock recovery converts 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data. The device combines a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, 16-bit demultiplexer, clock divider, and PECL output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). The MAX3881 is designed to deliver the best combination of jitter performance and power 6 dissipation by using a differential signal architecture and low-noise design techniques. The PLL recovers the serial clock from the serial input data stream. The demultiplexer generates a 16-bit-wide 155Mbps parallel data output. Input Amplifier The input amplifiers on both the main data and system loopback accept a differential input amplitude from 50mVp-p to 800mVp-p. The bit error ratio (BER) is better than 1 x 10-10 for input signals as small as 9.5mVp-p, _______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery Phase Detector The phase detector in the MAX3881 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The external phase adjust pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment. Frequency Detector The digital frequency detector (FD) aids frequency acquisition during start-up conditions. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector. Loop Filter and VCO The phase detector and frequency detector outputs are summed into the loop filter. A 1.0µF capacitor, CF, is required to set the PLL damping ratio. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low phase noise and is trimmed to the correct frequency. Loss-of-Lock Monitor A loss-of-lock (LOL) monitor is included in the MAX3881 frequency detector. A loss-of-lock condition is signaled with a TTL low. When the PLL is frequencylocked, LOL switches to TTL high in approximately 800ns. Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3881. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal. Positive Emitter-Coupled Logic (PECL) Outputs The MAX3881 features PECL outputs for the parallel clock and data outputs. For proper operation, PECL outputs should be terminated with 50Ω to (VCC - 2V). In many cases, it is not feasible to use the 50Ω to (VCC 2V) termination, so it may be preferable to terminate to the Thèvenin equivalent. See application note HFAN-1, Interfacing Between CML, PECL, and LVDS for more details regarding the Thèvenin-equivalent PECL termination. Design Procedure Jitter Tolerance and Input Sensitivity Trade-Offs When the received data amplitude is higher than 50mVp-p, the MAX3881 provides a typical jitter tolerance of 0.46UIp-p at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UIp-p, leaving a jitter allowance of 0.31UIp-p for receiver preamplifier and postamplifier design. The BER is better than 1 x 10 -10 for input signals greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will be degraded, but will still be above the SDH/SONET requirement. Trade-offs can be made between jitter tolerance and input voltage according to the specific application. See the Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Voltage graphs. Applications Information Consecutive Identical Digits (CIDs) The MAX3881 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 x 10-10. The CID tolerance is tested using a 2 13 - 1 pseudorandom bit stream (PRBS), substituting a long run of zeros to simulate the worst case. A CID tolerance of greater than 2,000 bits is typical. Phase Adjust The internal clock is aligned to the center of the data eye. For specific applications, this sampling position can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input voltages up to ±1.5V. A simple resistor-divider with a bypass capacitor is sufficient to set these levels (Figure 4). When the PHADJ inputs are not used, they should be tied directly to VCC. System Loopback The MAX3881 is designed to allow system loopback testing. The user can connect a serializer output (MAX3891) in a transceiver directly to the SLBI+ and SLBI- inputs of the MAX3881 for system diagnostics. To select the SLBI± inputs, apply a TTL logic high to the SIS pin. Interfacing with PECL Input Levels When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining _______________________________________________________________________________________ 7 MAX3881 although the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information. MAX3881 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery 50Ω termination (Figure 5). AC-coupling is also required to maintain the input common-mode level. VCC Exposed-Pad Package The exposed-pad (EP), 64-pin TQFP incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3881 and must be soldered to the circuit board for proper thermal and electrical performance. Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3881 high-speed inputs and outputs. Power-supply decoupling should be placed as close to V CC pins as possible. To reduce feedthrough, take care to isolate the input signals from the output signals. 50Ω 0.1µF 25Ω PECL LEVELS 50Ω SDI+ 100Ω 0.1µF 25Ω SDI- MAX3881 Figure 5. Interfacing with PECL Input Levels Chip Information 3.3V MAX3881 TRANSISTOR COUNT: 2231 PROCESS: BiPolar PHADJ+ (PIN 5) PHADJ- (PIN 6) Figure 4. Phase-Adjust Resistor-Divider 8 _______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery +3.3V 0.01µF PHADJ+ +3.3V VCC PHADJ- VCC 124Ω PD15 84.5Ω +3.3V 124Ω PD0 +3.3V OUT+ FIL IN+ 84.5Ω MAX3881 VCC SDI+ +3.3V MAX3866 124Ω PRE/POSTAMPLIFIER OUTLOP SDI- OVERHEAD TERMINATION PCLK+ 84.5Ω SLBI+3.3V SLBI+ TTL 124Ω SIS FIL+ FIL- GND LOL PCLK- SYSTEM LOOPBACK 84.5Ω CF 1.0µF TTL TTL EXTERNAL TERMINATION REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. _______________________________________________________________________________________ 9 MAX3881 Typical Application Circuit +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery 64L, TQFP.EPS MAX3881 Package Information 10 ______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3881 Package Information (continued)