TB62217AFG TOSHIBA BiCD Process Integrated Circuit Silicon Monolithic TB62217AFG PWM drive Stepping Motor Driver / Brush DC Motor Driver Selectable, DC-DC Converter and Reset function IC The TB62217FG is a dual stepping motor driver driven by PWM chopper micro step, with 3- channel step-down DC-DC converters and an external-IC reset function. To drive a two-phase bipolar-type stepping motor, a 16-bit latch and a 16-bit shift register are built into the IC. The IC is suitable for driving stepping motors with low-torque ripple in a highly efficient manner. In addition, a signal axis can be switched to serve as a PWM driver for two DC motors. By equipping the stepping motor driver with Selectable Mixed Decay Mode for switching the attenuation ratio during chopping, and also equipping it with a DC-DC converter, it is possible for the IC to supply external voltage. With a built-in timer that starts running when the IC is supplied with power, the IC can be used in resetting (initializing) external devices. Weight: 0.45 g (typ.) Features • The following motor combinations can be used. Stepper DC Large DC (L) DC Small DC (S) (1) Dual motors ⎯ ⎯ (2) Single motor Single motor ⎯ (3) Single motor ⎯ Dual motors (4) ⎯ Single motor Dual motors (5) ⎯ Dual motors ⎯ (6) ⎯ ⎯ Quadruple motors Note Hereafter, DC Large will be referred to as DC (L) and DC Small will be referred to as DC (S). Stepping Motor DC Motor Mode Pulse spike Peak Recommended maximum current Stationary current 1.0A(MAX) DC Large 8.0A(500ns) 3.0A(100ms) (Single Motor) DC Small 8.0A（500ns) 2.5A (100ms) 0.8A 0.8A The large current standard is achieved by shorting a small current H-Bridge across two ICs. In addition, if the thermal setting is designed to be within the prescribed thermal range, the initial torque current can be used as the normal operating current. 1 2004-11-12 TB62217AFG • It is possible to supply external voltage by incorporating three step-down 1.5 V to 5.0 V variable DC-DC converters. • A Reset function has been added making it possible to deliver an external reset signal. • The DMOS motor driver output of this monolithic BiCD IC is capable of achieving a low ON resistance of Ron = 0.6 Ω (＠Tj = 25°C, 0.6A: typ.) • With two sets of internal 16-bit shift register and latch, the IC can drive stepping motors using a 4-bit micro step. • Equipped protection circuits: DC-DC converter over current/increased voltage protection, motor over current protection and total IC over temperature protection. In addition, equipped with Power On Reset circuit for initializing the IC when the power is turned on and off. • Package: 64-pin Pb-free QFP package with a heat sink (THQFP64-P-1010-0.50) • Motor maximum output pressure: 50 V • On-chip Mixed Decay Mode enables specification of four-stage attenuation ratio. • Chopping frequency can be set by external oscillator. High-speed chopping is possible at 100 kHz or higher. Note: When using the IC, exercise great care in regard to thermal conditions. This device is easy damaged by high static voltage (ESD). For this reason, please handle with care. Please Insert an SBD (Schottky Barrier Diode : Recommended "TSB CRS04” ) between "ODB" pin and "D-GND" pin , if using C channel. 2 2004-11-12 TB62217AFG MGND OUT SD- RS D1 RS D2 OUT SD+ MGND NC NC MGND OUT SC+ RS C2 RS C1 OUT SC- MGND DGND1 Layout (4-channel DC Motor Mode , example) C＿SELECT * Pin 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ENABLE SD 49 32 TEST ENABLE SC 50 31 ODA Th OUT 51 30 FBA Logic OUT 52 29 VREF CD ENABLE SB 53 28 VREF AB ENABLE SA 54 27 VM NC 55 26 VDIN２ LGND 56 25 VDIN１ LGND 57 24 NC NC 58 23 NC ORT 59 22 OSC＿Ｄ OSC＿M 60 21 CC PHASE SA 61 20 FBB PHASE SC 62 19 ODＢ PHASE SD 63 18 FBC PHASE SB 64 17 ODC Dch Driver Cch Driver 10 11 12 13 14 15 16 OUT SB- MGND DGND2 RS A2 9 RS B1 RS A1 8 RS B2 OUT SA- 7 OUT SB+ MGND 6 MGND 5 NC 4 NC 3 MGND 2 Bch Driver OUT SA+ 1 SLEEP Ach Driver T-HQFP64-1010-P-0.50 Combinations enclosed in the blue dashed lines are used when in DC (L) mode (A- and B-axis drivers in a pair, and C- and D-axis drivers in a pair). 3 2004-11-12 TB62217AFG Cautions on connection to the IC pins Note1 Connect all NC pins (pins left unused) to the lowest potential level (usually to GND). Note2 Connect any unused Vref pins (28pin,29pin) to GND. Note3 Unused DATA, CLOCK, and STROBE input pins are pulled down internally, so connect them to GND. Please ensure that noise is not introduced into the external circuit Note4 Connect any unused RS pins to VM. Note5 Connect the feedback pins (FBA, FBB, and FBC) to GND if the corresponding DC-DC converter is not used. Note6 Always connect the TEST pin to the lowest potential level (usually to GND). Note7: TEST pin The TB62217FG has a test mode function for inspection at the factory. The test mode reduces the “initial and normal protection mask time” and “ORT output time” to 1/1024 of the respective ratings so as to make the inspection easier. To maintain normal operation, therefore, be sure to connect pin 32 to a ground so that it will not be used. Conditions to use the test mode Input level Note 8 32 pin: TEST 32 High standard operation Low TEST Mode 100kΩ If the IC is inserted in an incorrect orientation, it will be damaged because a high voltage is applied to low-voltage blocks. To avoid such damage, always confirm the position of pin 1 and the position and dimensions of each lead when installing the IC. Note 9 The IC has no on-chip over voltage protection circuit. Avoid applying a voltage higher than any rated voltage (such as maximum ratings) to the IC. Note 10 Solder the heat sink provided on the bottom surface of the IC to a ground-level pattern arranged for heat release so as to ensure stable operation and efficient heat release. Note11 Once set up, since the IC is not affected by a logical input from a “Don’t care” pin even if a voltage is applied to the pin, as long as the applied voltage is not higher than its rating, no problem (such as a malfunction) will occur. 4 2004-11-12 TB62217AFG Pin Descriptions (initial setup mode) SLEEP = Low supports a write mode for the initial setup or extended setup mode data. (1) Pin description (SETUP mode, that is, initial setup or extended setup mode) (2) Pin description (dual axis stepping motor mode) (3) Pin description (single axis stepping motor and single axis DC (L) mode) (4) Pin description (single axis stepping motor and dual axis DC (S) mode) (5) Pin description (dual axis DC (S) and single axis DC (L) mode) (6) Pin description (dual axis DC (L) mode) (7) Pin description (quadruple axis DC (S) mode) Pin Name Assignment Table (1) (2) (3) (4) (5) (6) (7) SETUP STEP STEP STEP+ DC (L)+ MODE (Dual) + DC (L) Dual DC (S) Dual ( DC (S) Dual DC (L) 4ch DC (S) 1 SLEEP (L) SLEEP (H) SLEEP (H) SLEEP ( H SLEEP ( H SLEEP ( H SLEEP ( H 2 MGND MGND MGND MGND MGND MGND MGND 3 (OUT A- OUT A- OUT A- OUT A- OUT LAB- OUT LAB- OUT SA- 4 (RS A1) RS A1 RS A1 RS A1 RS A1 RS A1 RS A1 5 (RS A2) RS A2 RS A2 RS A2 RS A2 RS A2 RS A2 6 (OUT A(+) OUT A+ OUT A+ OUT A+ OUT LAB+ OUT LAB+ OUT SA+ 7 MGND MGND MGND MGND MGND MGND MGND 8 NC NC NC NC NC NC NC 9 NC NC NC NC NC NC NC 10 MGND MGND MGND MGND MGND MGND MGND 11 (OUT B+) OUT B+ OUT B+ OUT B+ OUT LAB+ OUT LAB+ OUT SB+ 12 (RS B2) RS B2 RS B2 RS B2 RS B2 RS B2 RS B2 13 (RS B1) RS B1 RS B1 RS B1 RS B1 RS B1 RS B1 14 (OUT B−) OUT B− OUT B− OUT B− OUT LAB− OUT LAB− OUT SB− 15 MGND MGND MGND MGND MGND MGND MGND 16 DGND2 DGND2 DGND2 DGND2 DGND2 DGND2 DGND2 17 (ODC) ODC ODC ODC ODC ODC ODC 18 (FBC) FBC FBC FBC FBC FBC FBC 19 (ODB) ODB ODB ODB ODB ODB ODB 20 (FBB) FBB FBB FBB FBB FBB FBB 21 CC CC CC CC CC CC CC 22 OSC_D OSC_D OSC_D OSC_D OSC_D OSC_D OSC_D 23 NC NC NC NC NC NC NC 30 NC NC NC NC NC NC NC 25 VDIN1 VDIN1 VDIN1 VDIN1 VDIN1 VDIN1 VDIN1 26 VDIN2 VDIN2 VDIN2 VDIN2 VDIN2 VDIN2 VDIN2 27 VM VM VM VM VM VM VM 28 (VREF AB) VREF AB VREF AB VREF AB VREF LAB VREF LAB VREF SAB 29 (VREF CD) VREF CD VREF LCD VREF SCD VREF SCD VREF LCD VREF SCD 30 (FBA) FBA FBA FBA FBA FBA FBA 31 (ODA) ODA ODA ODA ODA ODA ODA 5 Remark 2004-11-12 TB62217AFG (1) (2) (3) (4) (5) (6) (7) SETUP STEP STEP STEP+ DC (L)+ MODE (Dual) + DC (L) Dual DC (S) Dual ( DC (S) Dual DC (L) 4ch DC (S) Remark 32 TEST TEST TEST TEST TEST TEST TEST Connect to GND 33 DGND1 DGND1 DGND1 DGND1 DGND1 DGND1 DGND1 34 MGND MGND MGND MGND MGND MGND MGND 35 (OUT C−) OUT C− OUT LCD− OUT SC− OUT SC− OUT LCD− OUT SC− 36 (RS C1) RS C1 RS C1 RS C1 RS C1 RS C1 RS C1 37 (RS C2) RS C2 RS C2 RS C2 RS C2 RS C2 RS C2 38 (OUT C+) OUT C+ DOUT LC( OUT SC( OUT SC( OUT LCD( OUT SC( 39 MGND MGND MGND MGND MGND MGND MGND 40 NC NC NC NC NC NC NC 41 NC NC NC NC NC NC NC 42 MGND MGND MGND MGND MGND MGND MGND 43 (OUT D() OUT D( OUT LCD( OUT SD( OUT SD+ OUT LCD+ OUT SD+ 44 (RSD1) RSD1 RSD1 RSD1 RSD1 RSD1 RSD1 45 (RSD2) RSD2 RSD2 RSD2 RSD2 RSD2 RSD2 46 OUT D- OUT D- OUT LCD- OUT SD- OUT SD- OUT LCD- OUT SD- 47 MGND MGND MGND MGND MGND MGND MGND 48 C_SELECT C_SELECT C_SELECT C_SELECT C_SELECT C_SELECT C_SELECT 49 - - - ENABLE SD ENABLE SD - ENABLE SD 50 - STROBE CD ENABLE LCD ENABLE SC ENABLE SC ENABLE LCD ENABLE SC 51 TH_OUT TH_OUT TH_OUT TH_OUT TH_OUT TH_OUT TH_OUT 52 LOGIC OUT LOGIC OUT LOGIC OUT LOGIC OUT LOGIC OUT LOGIC OUT LOGIC OUT 53 - - - - - - ENABLE SB 54 STROBE AB STROBE AB STROBE AB STROBE AB 55 NC NC NC NC NC NC NC 56 LGND LGND LGND LGND LGND LGND LGND AGND (LGND) 57 LGND LGND LGND LGND LGND LGND LGND AGND (LGND) 58 NC NC NC NC NC NC NC 59 ORT ORT ORT ORT ORT ORT ORT 60 OSC_M OSC_M OSC_M OSC_M OSC_M OSC_M OSC_M 61 - DATA CD - PHASE SD PHASE SD - PHASE SA 62 - CLK CD PHASE LCD PHASE SC PHASE SC PHASE LCD PHASE SC 63 DATA AB DATA AB DATA AB DATA AB - - PHASE SD 64 CLK AB CLK AB CLK AB CLK AB PHASE LAB PHASE LAB PHASE SB ENABLE LAB ENABLE LAB ENABLE SA -: Don’t care 6 2004-11-12 TB62217AFG ( Note:H-bridge combination (connection method) for each type of motor driver RRS VM RRS VM RS pin RS pin A-phase B-phase Load Load PGND PGND Stepping Motor single motor RRS VM RS pin RS pin Mutually connected outside the IC PGND Load PGND DC (L) Single motor … The white circle indicates an IC pin. Note1: When driving a DC motor in DC (L) mode, avoid an impedance difference outside the IC. Note2: If the impedance of wiring to mutually connected output transistors is unbalanced, the current that flows through the transistor also becomes unbalanced and may exceed the maximum rating of the transistor, thus damaging the transistor. 7 2004-11-12 TB62217AFG RRS VM RS pin Note Load PGND DC (S) Single motor … The white circle indicates an IC pin. 8 2004-11-12 TB62217AFG 1. Overall Block Diagram OSCD FBA FBB ODA DC/DC converter DC/DC cnv A ODB DC/DC converter DC/DC cnv B FBC ODC CC CSELECT DC/DC selector DC/DC converter DC/DC cnv C VM-VDD regulator POR unit (CC) VSD unit Extended setup unit SLEEP DATA selector DATA Init setup unit 16-bit latch * * These items are provided only on the A- and B-axis inputs. Logic out Current control data logic circuit 16-bit shift register Chopping reference circuit Current control 16-bit latch CLK STROBE Current setting circuit Vref Waveform shaping circuit 4-bit sine D/A (Angle control) Torque control OSC_M Chopping waveform generating circuit TH_OUT Current feedback circuit Output control unit RS COMP circuit VRS unit RS Thermal detect VM ISD unit Outputs unit (H-bridge) ORT RESET unit TSD circuit POR circuit (VM) Select Protection circuits Out X High-voltage wiring (VM) Logic DATA DC motor Stepping motor DC motor Analog DATA IC pin 9 2004-11-12 TB62217AFG 2-1. Input Equivalent Circuits (1) Logic Input Pin 21 CC * IN 150 Ω 100 kΩ * 56 To the internal logic 57 LGND GND 64: PHASE SB 63: PHASE SD 62: PHASE SC 61: PHASE SA 54: ENABLE SA 53: ENABLE SB 50: ENABLE SC 49: ENABLE SD 1: SLEEP (2) Vref Input Pin CC 21 2 28 : Vref AB 29 : Vref CD To the DA circuit 56 57 GND (3) DC/DC Feed Back Pin (FBx) 150 Ω 30 : FBA 1.05 V 2.01 V 18 : FBC 1.5 V 20 : FBB 57 10 2004-11-12 TB62217AFG 2-2. Stepping Motor Logic Unit (with the same functions for both an A-/B-axis pair and a C-/D-axis pair) Function This circuit receives step current setting data entered from the DATA pin and transfers it to the subsequent stage. It is enabled when the SLEEP pin is high. (If the SLEEP pin is low, the IC enters the initial setup or extended setup mode.) Step current setting data logic circuit and setup logic 16-bit shift register STROBE CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Current control 16-bit latch Sleep = H Torque × 2 bits Current feedback circuit (TRQ setting) Decay × 2 bits B unit side B unit side mixed decay timing Current × 4 bits B unit side Phase × 1 bit B unit side DA circuit B-phase information Output control circuit Decay × 2 bits A unit side A unit side mixed decay timing Current × 4 bits A unit side Phase × 1 bit A unit side DA circuit A-phase information Output control circuit Once ORT is released, driving the SLEEP pin high puts the IC in a write mode for stepping motor current control data. Driving the SLEEP pin from high to low and back to high clears any latched motor control data (to all low). 11 2004-11-12 TB62217AFG 2-3. Initial Setup Logic Unit (available only for the A- / B-axis pair) Function This circuit is used to set up driver functions (initial setup) according to signals entered from the DATA pin. The functions that can be set up include motor re-configuration, digital tBLANK, DC-DC converter ON/OFF setting, and DC motor mode Vref (gain) setting. Note: Do not use the TEST mode. Keep all the corresponding bits and any unused pins at a low level. Logic circuit and setup logic 16-bit shift register STROBE AB CLK AB DATA AB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 L Initial setup 16-bit latch Sleep = L Motor select (3 bit) tBLANK AB (2 bit) tBLANK CD (2 bit) DCDC select (3 bit) DC Vref gain (2 bit) TEST (3 bit) No use (1 bit) Note: The setting entered in initial setup mode is in effect if the DATA signal is low when the STROBE signal is supplied. The initial setup mode data is cleared at POR (power-on reset). 12 2004-11-12 TB62217AFG 2-4. Extended Setup Logic Unit (available only for the A- and B-axis pair) Function This circuit sets up the monitor functions of the driver IC internal circuits according to a signal entered from the DATA pin. Extended setup logic 16-bit shift register STROBE AB CLK AB DATA AB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Extended setup 16-bit latch 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 H Sleep = L Shut down select (4 bit) Shut down mask (4 bit) Reset mask (3 bit) Pre TSD (2 bit) Reserved No use (1 bit) ISD time (1 bit) Note: The internal-signal monitoring setting (entered in extended setup mode) is in effect if the DATA signal is high when the STROBE signal is supplied. Data for the extended setup mode is cleared at POR (power-on reset). 13 2004-11-12 TB62217AFG Current Feedback Circuit and Current Setting Circuit for Motor Driver Function The current setting circuit is used to set the reference voltage of the output current using the step current setting data entered from the serial input pin. The current feedback circuit is used to deliver a signal to the output control circuit when the output current reaches the set current. This is done by comparing the reference voltage delivered from the current setting circuit with the potential difference generated when current flows through the current sense resistor (RRS) connected between RS and VM. The chopping waveform generator, to which a capacitor is connected, generates the OSC M (OSC-CLK) as a chopping frequency reference. If the Osc_M pin becomes open, the open condition detection function works, thus shutting down the IC. If the pin is shorted to GND when the IC starts operating, the detection function also works and the IC does not operate. Vref From the logic unit 100% 85% 70% 50% Torque control circuit Current 0~3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSC_D Chopping reference waveform generator circuit OSCM Step current selector circuit Waveform shaper circuit 4-bit DA circuit VRS circuit 1 (detects voltage difference between RS and VM) Mixed decay timing circuit Chopping reference generator circuit Output stop signal (ALL OFF) Current setting circuit RS DSC Open Short Detect Unit COSCM Torque 0.1 RRS 3. RS COMP circuit NF (set current reached signal) Output control unit Current feedback circuit VM Note: The RE COMP circuit compares the set current with the output current and generates a signal when the output current reaches the set current. 14 2004-11-12 TB62217AFG 4. Output Control Circuit, Current Feedback Circuit, and Current Setting Circuit for Motor Driver Step current setting data logic circuit Current feedback circuit Decay mode Phase Output control circuit NT set current reached signal Mixed decay timing circuit OSC counter Charge start Mixed decay timing Current setting circuit Chopping reference generator circuit OSC counter (2) U1 Output stop signal Output driver circuit U2 L1 Output control signal L2 Output reset signal Output circuit ISD circuit VM VM-VCC regulator CC POR circuit (VM) CC monitoring circuit Reset signal selector circuit TSD circuit VSD circuit Th_out Protection circuits Latched-data clear signal VSD VMR ISD TSD : DC-DC output voltage monitor : VM power monitor : Over current protection circuit : Over-temperature protection circuit Logic 15 2004-11-12 TB62217AFG 5. Output Equivalent Circuit for Motor Driver RSA To VM RRS A Output driver circuit From output control circuit U1 U2 L1 L2 U1 U2 OUT A L1 L2 Phase A VM RSB Output driver circuit From output control circuit U1 U2 L1 L2 OUT A U1 RRS B U2 OUT B M OUT B L1 L2 Phase B MGND The motor output H switch block consists of the upper P-channel DEMOS FET and lower N-channel DEMOS FET. Each output DEMOS FET is connected to an over current sense circuit (ISD detection circuit) in parallel. 16 2004-11-12 TB62217AFG DC-DC Converter Circuit When an open detection circuit is available, Osc_D pin is set to open, the IC shuts down. If the pin is shorted to GND at startup, the IC fails to start operating. (It does not detect in a default.) In the DC-DC converter operating mode, channel B starts operating before channel A or C. OSC_D CR control circuit A ch ch Ach Bch Cch DC-DC converter A control circuit LDA (330 µH) FBA VSD 750mA 400mA 400mA To output C_DC_A (100 µF) ODA Maximum Rating RDCA2 RDCA1 VDIN COSC_D (120 pF) DGND DC-DC converter B control circuit LDB (330 µH) C ch RDCB2 RDCB1 FBB VSD C_DC_B (100 µF) ODB ※SBD To output DC-DC converter C control circuit LDC (330 µH) ODC To output FBC VSD RDCC2 RDCC1 B ch C_DC_C (100 µF) 6. DGND ※Please Insert a SBD( Schottky Barrier Diode : Recommended "TSB CRS04) between "ODB" Pin to "D-GND" pin. 17 2004-11-12 TB62217AFG Reset Circuit (ORT) This circuit has an open-drain output. If the output is pulled up with a resistor to the supply voltage, its level becomes low (internally on) at reset and high (internally Hi-Z) during normal operation (at a non-reset). 8. DC/DC conv 3.3 V ORT 1 kΩ 7. DC-DC Converter Select Circuit (C_SELECT) *: Each internal circuit resistance varies by ±30%. CC 200 kΩ To internal 5 V supply voltage 150 Ω C_SELECT 200 kΩ is added if the voltage is 2.5 V 9. Set Temperature Detection Output Pin (TH-OUT) Ｖcc TH-out It is not necessary to connect a pull-up resistor when choosing ANALOG output mode ( terminal :OPEN) 10. Internal Logic Signal Select Output Pin (LOGIC OUT) Both the TH-OUT and LOGIC OUT circuits have the same open-drain circuit as the ORT circuit. If their output pins are pulled up with a resistor to the supply voltage, their levels become low (internally on) at reset and high (internally Hi-Z) during normal operation (at non-reset). 18 2004-11-12 TB62217AFG 16-Bit Serial Input Signals Three different pieces of data can be entered and set up by combining the CLK, DATA, STROBE and SLEEP pin inputs. (1) Extended setup mode (for setting up protection circuits) (2) Initial setup mode (for setting up motor drive modes) (3) Stepping motor drive mode (normal drive mode) Setup Mode Specifications (Initial setup and extended setup modes) SLEEP STROBE CLK DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: The internal-signal monitoring setting (entered in extended setup mode) is in effect if the DATA signal is high when the STROBE signal is supplied. If the DATA signal is low, initial setup is in effect (initial setup mode). 19 2004-11-12 TB62217AFG (1) Extended Setup Mode Function (write enabled only when SLEEP = L and Setup Select = H) • In the extended setup mode, the protection circuits are set up and a monitor setup (output of a Lo_out pin) of a shutdown signal etc. is performed. Data Bit 0 Name Function Default Value Setting SD SELECT 0 1 SD SELECT 1 2 SD SELECT 2 3 SD SELECT 3 4 Unused 5 DCDC VSD SD MASK 6 Motor ISD SD MASK 7 TSD SD MASK 8 RESET MASK C 9 RESET MASK B 0 Selecting a signal at shut-down These 4 bits select what shut-down signal to produce. See the next item for explanations about the 4-bit data combinations. 0 0 0 ⎯ ⎯ 0 0 0: Normal operation. See the corresponding item below for explanations about the 3-bit data combinations. Shut-down signal mask 0 0 Disabling the RESET signal at the shut-down of the corresponding DC-DC converter. 0: Normal operation. 1: If the DC-DC converter concerned is shut down: (1) The RESET signal is not generated. (2) All DC-DC converters other than the DC-DC converter of interest operate normally. (3) The DC-DC converter concerned returns to normal when the SLEEP signal changes from low to high. 12 0 0 1 1 10 RESET MASK A 11 PRE TSD 0 12 PRE TSD 1 Generating a low signal at the Th_out pin at a temperature of the TSD temperature − X. 13 Unused Unused 14 OSCM/D Watch Dog Setting Specifying whether to cause OSC_M and OSC_D to run. 15 Unused Unused 11 (← bit) 0: TSD-20°C 1: TSD-30°C 0: TSD-40°C 1: Analog 0 0 0 0 ⎯ 0: OFF (watchdog disabled) 1: ON (watchdog enabled) ⎯ 20 0 0 0 0 2004-11-12 TB62217AFG [Shut-down signal output (SD select)] These 4 bits are used to select what shut-down signal to generate. Alternatively, they are used to indicate vendor or version code. The shut-down select signals are released when the SLEEP signal changes form low to high. Data Function Data (3) Data (2) Data (1) Data (0) Bit L L L L Generate the shut-down signal when the channel A DC-DC converter is shut down with DC-DC VSD_H or DC-DC VSD_L. L L L H Generate the shut-down signal when the channel B DC-DC converter is shut down with DC-DC VSD_H or DC-DC VSD_L. L L H L Generate the shut down signal when the channel C DC-DC converter is shut down with DC-DC VSD_H or DC-DC VSD_L. L L H H Unused L H L L Generate the shut-down signal when the DC-DC converter is shut down with “DC-DC VSD_H”. L H L H Generate the shut-down signal when the DC-DC converter is shut down with “DC-DC VSD_L”. L H H L Generate the shut-down signal when the DC-DC converter is shut down with “Motor ISD”. L H L H Generate the shut-down signal when the DC-DC converter is shut down with “TSD”. H L L L Revision (0) Deliver bit 0 of the version code. H L L H Revision (1) Deliver bit 1 of the version code. H L H L Revision (2) Deliver bit 2 of the version code. H L H H Vender code: Always deliver “detected” in the TB62217FG. H H L L Unused H H L H Unused H H H L Unused H H H H Unused *: Data (3 to 0) = “0000” to “0111” are used to indicate a signal filtered in the internal dead-zone time circuit. [Shut-down mask] These 3 bits are used to disable the shut-down function concerned. (One bit corresponds to one function. When a bit is high, the corresponding function is disabled. Their default value is “LLLL”.) Data (7): If this bit is high, “TSD” is disabled. Data (6): If this bit is high, “Motor ISD” is disabled. Data (5): If this bit is high, “DC-DC VSD” is disabled. *: Data (4): Unused. 21 2004-11-12 TB62217AFG [RESET output mask] These 3 bits are used as a signal to specify whether to produce the RESET when the respective DC-DC converters are shut down. No low signal is produced as the RESET even if Data (X) = H and one DC-DC channel = H. The default value of these bits is “L, L, L”. (When a DC-DC converter is shut down, the RESET is driven low, and all DC-DC channels are turned off.) If the DC-DC converter concerned is shut down: (1) No RESET (ORT) is produced. (2) All DC-DC converters other than that concerned operate normally (rather than being shut down) (3) Changing the SLEEP signal from low to high restarts the DC-DC converter. Data (10): DC-DC converter channel A Data (9): DC-DC converter channel B Data (8): DC-DC converter channel C [PRE TSD] A low signal is generated at the TH_OUT pin if the current temperature is X degrees lower than the TSD temperature. In analog output mode, a very low voltage proportional to the temperature is generated. (The analog output mode is dedicated for test use; its specification is not guaranteed and therefore it may not be able to be used in usual operation.) Data (12, 11) = 0, 0: TH_OUT is generated (low level) at the TSD temperature − 20°C. Data (12, 11) = 0, 1: TH_OUT is generated (low level) at the TSD temperature − 30°C. Data (12, 11) = 1, 0: TH_OUT is generated (low level) at the TSD temperature − 30°C. Data (12, 11) = 1, 1: Analog output mode. TH-out characteristic (for reference) Voltage（ｍＶ） 0.8 About -1.5mV/ OC 0.7 0.6 0.5 0.4 0 20 40 60 80 100 120 temperature（ C） O [Revision and vender] The revision and vendor codes are specific to an individual version of product. For example: Revision (0, 1, 2) = (L, L, L) and Vendor = (H) for Toshiba #1.0 Revision (0, 1, 2) = (H, L, L) and Vendor = (H) for Toshiba #1.1 Revision (0, 1, 2) = (L, H, L) and Vendor = (H) for Toshiba #1.2 Revision (0, 1, 2) = (H, H, L) and Vendor = (H) for Toshiba #1.3 Revision (0, 1, 2) = (L, L, H) and Vendor = (H) for Toshiba #2.0 22 2004-11-12 TB62217AFG [OSC_M/OSC_D open-state detection circuit] The OSC_M/OSC_D open-state detection circuit tries to detect when a capacitor comes off the OSC_M or OSC_D for some reason by monitoring to see if the frequency gets out of the rated frequency range. When it detects such an event, it shuts down the IC. The open-state detection circuit is initially off when the power is turned on. (To cause it to run, a serial signal must be supplied to make the corresponding bit high.) The frequency range settings are stated below. (1) Shut down if the current frequency does not fall in the range: OSC_M frequency/64 > OSC_D frequency > OSC_M frequency/2 (2) Shut down if the current frequency does not fall in the range: OSC_D frequency × 32 > OSC_M frequency > OSC_D frequency × 2 Example 1: If the OSC_M frequency is 800 kHz The IC is shut down when OSC_D frequency > 400 kHz or OSC_D frequency < 12.5 kHz. 2: If the OSC_D frequency is 100 kHz The IC is shut down when OSC_M frequency > 3200 kHz or OSC_M frequency < 200 kHz. 23 2004-11-12 TB62217AFG Initial Setup Mode Select (write enabled only when SLEEP = L and Setup Select = L) (2) Data Bit Name 0 Motor Select0 1 Motor Select1 2 Motor Select2 3 TBlank AB 0 4 TBlank AB 1 5 TBlank CD 0 6 TBlank CD 1 7 Function Setting Default Value Motor pairing setting (See the corresponding pin assignment table.) D2 D1 D0 0 0 0: Stepper × 2 0 0 1: Stepper × 1 + DCL × 1 0 1 0: Stepper × 1 + DCS × 2 0 1 1: DCL × 1 + DCS × 2 1 0 0: DCL × 2 1 0 1: DCS × 4 Channels A and B Noise rejection dead band time setting (See Note below.) D4 D3 0 0: (1 ÷ fChop) ÷ 8 × 5 0 1: (1 ÷ fChop) ÷ 8 × 2 1 0: (1 ÷ fChop) ÷ 8 × 3 1 1: (1 ÷ fChop) ÷ 8 × 4 0 0 Channels C and D Noise rejection dead band time setting (See Note below.) D6 D5 0 0: (1 ÷ fChop) ÷ 8 × 5 0 1: (1 ÷ fChop) ÷ 8 × 2 1 0: (1 ÷ fChop) ÷ 8 × 3 1 1: (1 ÷ fChop) ÷ 8 × 4 0 0 DC/DC A SW DC-DC converter channel A operation 0: ON 1: OFF (Note) 8 DC/DC B SW DC-DC converter channel B operation 0: ON 1: OFF (Note) 9 DC/DC C SW DC-DC converter channel C operation 0: ON 1: OFF (Note) 10 (A- and B-axis) DC motor Vref (gain) Channels A and B Internal Vref attenuation ratio setting for constant current in DC motor mode 0: 1/10 1: 1/20 0 11 (C- and D-axis) DC motor Vref (gain) Channels C and D Internal Vref attenuation ratio setting for constant current in DC motor mode 0: 1/10 1: 1/20 0 12 Test IC internal test mode setting Always keep this bit low. 0 13 Test IC internal test mode setting Always keep this bit low. 0 14 Test IC internal test mode setting Always keep this bit low. 0 15 Unused This bit is not in use. Always keep it low. 0 ⎯ 0 0 0 Note: The initial setting for DATA bits 7, 8, and 9 is determined according to the value of C_SELECT when the VM power is turned on. 24 2004-11-12 TB62217AFG tBLANK (noise rejection dead band time) The TB62217FG incorporates two different dead band times (blanking times) for different motors to be driven so as to prevent malfunction because of switching noise. (1) Analog tBLANK (for stepping motor mode) The noise rejection dead band time (analog tBLANK), defined by the motor's AC characteristics, is fixed within the IC. It is used mainly to avoid misjudging Irr (diode recovery time) when a stepping motor is driven with constant current. It is fixed within the IC; it cannot be altered. (2) Digital tBLANK (for DC motor mode) Unlike the analog tBLANK, this tBLANK time, specified when the initial setup mode is selected, is generated digitally from an external chopping period. It is used mainly to avoid misjudging the varistor recovery current that occurs when a DC motor is driven by PWM in the DC motor drive mode. If the Motor Select signal selects the stepping motor mode, the digital tBLANK is nullified (0 µs), thus enabling only the analog tBLANK time provided within the IC. Because the digital tBLANK is generated in reference to the OSC_M, it can be changed by altering the OSC_M. (Note that altering the OSC_M also changes other items (motor chopping frequency, dead band time at the time of starting).) Digital tBLANK time In the initial setup mode, the tBLANK time can be set to 4 different levels for A-B and C-D pairs as follows: (1) Immediately after the PHASE has changed If the PHASE changes, the following time is needed for synchronization with an OSC_M edge and internal synchronization. tBLANK time = time need for synchronization between OSC_M and PHASE + set tBLANK time = internal processing time (OSC_M × 1) + synchronization time (below OSC_M × 1) + set time (2) Charging in constant-current operation (limiter operation) tBLANK time = set tBLANK time The set tBLANK time is as follows: tBLANK AB (0, 1) & tBLANK CD (0, 1) =: 0 0: OSC_M period × 5 0 1: OSC_M period × 2 1 0: OSC_M period × 3 1 1: OSC_M period × 4 Caution: For #2.0 and after, tBLANK (0, 0) = OSC_M period × 5. 25 2004-11-12 TB62217AFG Digital tBLANK Timing in DC Motor Drive Mode Phase Digital tBLANK Digital tBLANK Digital tBLANK Digital tBLANK Digital tBLANK Iout Charge Iout = 0 Charge start timing in constant-current control Phase switching point Phase switching point The digital tBLANK time begins immediately after the external PHASE signal is switched or at the charge start timing of the constant-current chopper. The digital tBLANK is effective only in the DC motor drive mode. The decay mode for DC motor driving is “Fast Decay”. 26 2004-11-12 TB62217AFG (3) Data for Normal Stepping Motor Operation The TB62217FG signals for normal stepping motor operation can be entered in much the same manner as the drive data of the Toshiba TB62202AF. Data Bit Name Function 0 Torque A0/B0 1 Torque A1/B1 2 Decay Mode B0 3 Decay Mode B1 4 Current B0 5 Current B1 6 Current B2 7 Current B3 8 Phase B 9 Decay Mode A0 10 Decay Mode A1 11 Current A0 12 Current A1 13 Current A2 14 Current A3 15 Phase A Setting Current range setting A1/B1 0 0 1 1 A0/B0 0 : 50% 1 : 70% 0 : 85% 1 : 100% Channel B current attenuation ratio setting (Mixed Decay Mode) B1 0 0 1 1 Channel B current setting 4-bit current data (Using 4 data bits can divide each step into 16.) (“0000”: All-output OFF mode) See Setting Table (3). Channel B current phase information 1: OUT B+ is high. 0: OUT B− is high. Channel A current attenuation ratio setting (Mixed Decay Mode) A1 0 0 1 1 Channel A current setting 4-bit current data (Using 4 data bits can divide each step into 16.) (“0000”: All-output OFF mode) See Setting Table (4). Channel A phase information 1: OUT A+ is high. 0: OUT A− is high. B0 0 : 12.5% Decay Mode 1 : 37.5% Decay Mode 0 : 75% Decay Mode 1 : Fast Decay Mode(100%) A0 0 : 12.5% Decay Mode 1 : 37.5% Decay Mode 0 : 75% Decay Mode 1 : Fast Decay Mode(100%) SLEEP STROBE CLK DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 The initial setup latch, extended setup latch, or normal motor latch is selected as a write latch according to the logical level of the SLEEP signal and the polarity of the DATA signal at an STROBE signal edge. If the SLEEP signal is low, the setup latch is selected when the STROBE changes from low to high (initial setup if DATA = low and extended setup if DATA = high). If the SLEEP is high, the normal motor latch is selected. Don't care the level of the SLEEP during data transfer. The stepping motor latches (for both A-B and C-D pairs) are initialized when the SLEEP signal changes from high to low or from low to high. All registers are initialized at POR. The pins used to write during SLEEP include the DATA AB, CLOCK AB, and STROBE AB pins. 27 2004-11-12 TB62217AFG Setting Table (1) D0 and D1 Torque setting The peak torque current can be switched using 2-bit data. (Switching is the same for both the A-B and C-D pairs.) Data Bit 0 1 Name Function Torque0 Torque1 Torque 1 Torque 0 Setting Torque (typ.) 0 0 50% 0 1 70% 1 0 85% 1 1 100% Sets current range Setting Table (2) D2, D3, D9, and D10 Decay mode x1 and x0 settings A value of 37.5% is recommended for a typical condition. Data of (0, 0) specifies a 12.5% decay mode. Data Bit 2 3 9 10 Name Function Decay Mode A1/A0 Decay Mode 1 Decay Mode 0 Setting Decay mode 0 0 Mixed Decay Mode: 12.5% 0 1 Mixed Decay Mode: 37.5% 1 0 Mixed Decay Mode: 75% 1 1 Fast Decay Mode (100%) Sets mixed decay Decay Mode B1/B0 Setting Table (3) D4, D5, D6, and D7 Current B setting Data Bit Step Current B3 Current B2 Current B1 Current B0 Set angle (degrees) Current (%) 4 5 6 7 16 1 1 1 1 90 100 15 1 1 1 1 84 100 14 1 1 1 0 79 98 13 1 1 0 1 73 96 12 1 1 0 0 68 92 11 1 0 1 1 61 88 10 1 0 1 0 56 83 9 1 0 0 1 51 77 8 1 0 0 0 45 71 7 0 1 1 1 39 63 6 0 1 1 0 34 56 5 0 1 0 1 28 47 4 0 1 0 0 23 38 3 0 0 1 1 17 29 2 0 0 1 0 11 20 1 0 0 0 1 6 10 0 0 0 0 0 0 0 28 2004-11-12 TB62217AFG Setting Table (4) D11, D12, D13, and D14 Current A setting Data Bit Step Current A3 Current A2 Current A1 Current A0 Set angle value (degrees) Current (%) 11 12 13 14 16 1 1 1 1 90 100 15 1 1 1 1 84 100 14 1 1 1 0 79 98 13 1 1 0 1 73 96 12 1 1 0 0 68 92 11 1 0 1 1 61 88 10 1 0 1 0 56 83 9 1 0 0 1 51 77 8 1 0 0 0 45 71 7 0 1 1 1 39 63 6 0 1 1 0 34 56 5 0 1 0 1 28 47 4 0 1 0 0 23 38 3 0 0 1 1 17 29 2 0 0 1 0 11 20 1 0 0 0 1 6 10 0 0 0 0 0 0 0 Setting Table (5) D8 and D15 Phase A setting (this table applies also to phase B.) The polarity of the phase A current of a stepping motor is determined as listed below. Data Bit Name 8 15 Phase B Phase A Function Phase Setting Phase 0 OUT A: L, OUT A-: H OUT B: L, OUT B-: H 1 OUT A: H, OUT A-: L OUT B: H, OUT B-: L Switches phase 29 2004-11-12 TB62217AFG Functions of External Input Pins (1) PHASE Input Pin (PHASE X) This pin indicates the polarity of the H switch used in driving a DC motor. PWM can be applied by performing time control (duty control) on this pin. Pin No. 61 64 62 63 Name PHASE SB SC SD Function Logical Level SA Switches phase Setting Phase L OUT X: L, OUT X-: H H OUT X: H, OUT X-: L (2) ENABLE Input Pin (ENABLE X) This pin indicates whether to supply the power to a DC motor to be driven. Pin No. 54 53 50 49 Name ENABLE SB SC SD SA Function Logical Level Setting Enable Whether to activate the output L OFF (All transistors for the H switch are off.) H Active (3) SLEEP Input Pin When the level of this pin is switched from high to low or low to high, all motor drive registers are cleared (all bits of the 16-bit latch for selecting a motor drive are cleared to low). After the IC is shut down in motor ISD operation, changing the SLEEP signal from high to low and to high again causes the IC to return to normal. Pin No. Name Function Logical Level 1 SLEEP Power saving mode Setting Sleep L Power consumption reduction mode and initial setup mode H Motor operation mode (4) C_SELECT Input Pin This pin determines which DC-DC converter to run (ON-OFF combinations) when the power is turned on. Pin No. 48 Name C_SELECT Function Logical Level DC-DC converter mode at start Setting Phase Low A ch: OFF B ch: OFF C ch: OFF Mid A ch: ON B ch: ON C ch: OFF High A ch: OFF B ch: ON C ch: ON Note: If the C_SELECT pin is on the mid level, channel B is turned on before channel A. If it is high, channel B is turned on before channel C. 30 2004-11-12 TB62217AFG Protection Operations (1) When the RESET output mask is “1” in the extended setup mode Detected Error and Detection Block DC/DC A DC/DC B DC/DC C Operation State Reset Output Reset Method Motor Entire IC VSD VSD VSD ISD TSD Not detected Not detected Not detected Not detected Not Normal Normal Normal Normal detected operation operation operation operation H ⎯ Detected Not detected Not detected Not detected Not detected H SLEEP/POR Not detected Detected Not detected Not detected Not Normal detected operation H SLEEP/POR Not detected Not detected Detected Not detected Not Normal Normal detected operation operation Normal operation H SLEEP/POR Not detected Not detected Not detected Detected Not Normal Normal Normal detected operation operation operation OFF L pulse SLEEP/POR Not detected Not detected Not detected Not detected Detected Shut down L POR DC/DC A DCDC OFF Shut down DC/DC B DC/DC C Motor Normal Normal Normal operation operation operation DCDC OFF Shut down Normal Normal operation operation DCDC OFF Shut down Stop state in the protection operations listed above • Shut-down = all the functions stop as a failure related to the entire system occurs. They can be restarted only by initializing using the POR when the VM power is turned on again. • OFF = only the motor block stops operating. It can be restarted by changing the SLEEP signal from high to low and to high again. • L Pulse: The ORT keeps producing low pulses for 40 ms (if OSCM = 800 kHz). • DC-DC OFF = only the DC-DC converter concerned stops operating. It can be restarted as stated below depending on the logic level on which the SLEEP signal is when the converter stops operating. (1) If the SLEEP is low when the DC-DC converter stops, it can be restarted by changing the SLEEP signal from low to high. (2) If the SLEEP is high when the DC-DC converter stops, it can be restarted by changing the SLEEP signal from high to low and to high again. 31 2004-11-12 TB62217AFG (2) When the RESET output mask is “0” in the extended setup mode Detected Error and Detection Block DC/DC A DC/DC B DC/DC C Operation State Motor Entire IC TSD DC/DC A DC/DC B DC/DC C Motor Reset Output Reset Method VSD VSD VSD ISD Not detected Not detected Not detected Not detected Not Normal Normal Normal Normal detected operation operation operation operation H ⎯ Detected Not detected Not detected Not detected Not detected Shut Down Shut Down Shut Down Shut Down L POR Not detected Detected Not detected Not detected Not detected Shut Down Shut Down Shut Down Shut Down L POR Not detected Not detected Detected Not detected Not detected Shut Down Shut Down Shut Down Shut Down L POR Not detected Not detected Not detected Detected Not Normal Normal Normal detected operation operation operation OFF L Pulse SLEEP/POR Not detected Not detected Not detected Not detected Detected Shut Down L POR Shut Down Shut Down Shut Down Stop state in the protection operations listed above • Shut-down = all the functions stop as a failure related to the entire system occurs. They can be restarted only by initializing using the POR when the VM power is turned on again. • OFF = only the motor block stops operating. It can be restarted by changing the SLEEP signal from high to low and to high again. • Low Pulse: Low pulses are generated for 40 ms (if OSCM = 800 kHz). Protection Circuit Dead Band Time (example in which the reference clock (Osc_M) frequency is 800 kHz) Protection Function Block Detected Protection Mask Width Example: Time for OSCM = 800 kHz Reset Method TSD Entire IC 12 to 16CLK 15 to 20 µs Supplying VM power again DC-DC converter No function is available ⎯ ⎯ Motor 4 to 8CLK 5 to 10 µs Driving the SLEEP pin low or supplying VM power again DC-DC converter 12 to 16CLK 15 to 20 µs Supplying VM power again ISD VSD Note: To put protection into effect, the protection circuit must keep operating for at least the time stated above. 32 2004-11-12 TB62217AFG (1) Extreme Voltage Drop Protection Function VSD (when detected, the IC is shut down) Set voltage +40% (typ.) Set voltage Set voltage −30% (typ.) DC-DC converter Channel A/B/C output 12~16 CLK GND Reset output GND (2) Extreme Voltage Drop Protection Function VSD During Current Limiter Operation (when detected, the IC is shut down) Set voltage +40% (typ.) OSC_D: 3 CLK Set voltage DC-DC converter Channel A/B/C output GND Current limiter operation −30% Set voltage −15% (typ.) Limiter state GND Reset output GND (3) IC Overheat Protection Function (TSD) (when detected, the IC is shut down) Overheat protection value IC junction temperature 12~16 CLK Reset output GND Note: A low-pulse period of 40 ms is applied when OSC_DM frequency = 800 kHz and clock = 1.25 µs. 4) Motor Over Current Protection Function (when detected, only the motor is stopped) Over current Motor output current 4~8 CLK GND 32768 clock (40 ms typ.) Reset output GND 33 2004-11-12 TB62217AFG Power Supply Sequence If the C_SELECT pin is driven mid or high The 1st DC-DC converter represents channel B, and the 2nd DC-DC converter, channel A or C. 6V 6V 10 µs POR POR Internal logic start Internal logic 10 ms 20 ms 1st DC-DC converter operation start 1st DC-DC converter 20 ms 2nd DC-DC converter operation start 2nd DC-DC converter Protection mask end Protection mask ORT 100 ms ORT Serial data acceptable max 320 ms Note: If the C_SELECT pin specifies that all DC-DC converters be off, the ORT reset time is 320 ms. If serial data specifies DC-DC converters be turned on after the power is turned on (C_SELECT: Low) DC-DC converter channel A operation start Channel A protection mask 100 ms DC-DC converter channel B operation start Channel B protection mask 100 ms DC-DC converter channel C operation start Channel C protection mask 100 ms 34 2004-11-12 TB62217AFG Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Motor output voltage VM 50 V Motor output current IOST 1.3 A/phase IOSAP 8? A DC motor S (500 ns) DC motor S (100 ms) (Note 1) (Note 2) Remark Stepper IOSAE 3 A ICO A 750 mA IDC B 400 mA IDC C 400 mA Current detection pin voltage VRS VM ± 4.5 V Reset pin supply voltage VRST 5 V Reset output current IRST −60 mA Logic input voltage VIN −0.4 to 6.0 V 1.25 W When Ta exceeds 25°C, this figure must be de-rated by 10.0mW /°C. (Note 3) 4.2 W When Ta exceeds 25°C, this figure must be de-rated by 33.65mW /°C. (Note 4) DC-DC converter output current Power dissipation PD Operating temperature Topr −40 to 85 °C Storage temperature Tstg −55 to 150 °C Junction temperature Tj 150 °C Note 1: See other tables for pairing. Note 2: Peak maximum during DC motor drive (below 500 ns) Note 3: Stand-alone measurement (Ta = 25°C) Note 4: When the IC is mounted on a dedicated board (Ta = 25°C) Ta: IC ambient temperature Topr: IC ambient temperature during operation Tj: IC chip temperature during operation The maximum Tj value is limited by the TSD (thermal shut-down circuit) temperature 35 2004-11-12 TB62217AFG Recommended Operating Conditions (Ta = 0 to 85°C) Characteristics Symbol Min Typ. Max Unit 6 (Note 1) 27 40 V Motor block 18 27 40 Per phase (in single-axis drive) at Ta = 25°C ⎯ 0.6 1.0 Per H-bridge with peak of 500 ns at Ta = 25°C ⎯ 0.8 6.4 Per H-bridge with pulse of 100 ms at Ta = 25°C ⎯ 0.8 2.4 IDCi A Before the ORT signal is output (Note 2) ⎯ ⎯ 100 mA IDCi B IDCi C Before the ORT signal is output (Note 2) ⎯ ⎯ 100 mA IDC A After the ORT signal is output ⎯ ⎯ 600 mA IDC B IDC C After the ORT signal is output ⎯ ⎯ 300 mA GND 3.3 5.0 V 1.0 ⎯ 25 MHz ⎯ 100 ⎯ kHz ⎯ 800 ⎯ ⎯ 0.8 2.0 3.0 V VM supply voltage VM IOLA Stepper Output current DC IOSL DC-DC converter initial output current DC-DC converter output current Logic input voltage VIN Clock frequency fCLK Motor chopping frequency range fchop ⎯ Vref reference voltage input range ⎯ Test Condition Excluding motor block ⎯ VM = 40 V Vref A Note 1: A voltage of 7 V or higher is recommended for typical use. A VM voltage range between 6 V (POR voltage) and 7 V inclusive allows the DC-DC converter to exhibit much the same characteristics as when VM = 7 V (except that the voltage error becomes ±10%). However, it is recommended to use the IC at 7 V or higher (partly to allow for a margin of stability), because both the rising POR (power-on reset voltage) and falling POR (shut-down voltage) are 6 V. Note 2: When the power is turned on, soft start is put in effect by limiting the current to the DC-DC converter input block. The limited current results in the output current being limited. If an attempt is made to turn on the power with a load current flowing, it is likely that the DC-DC converter may fail to start or that the output voltage may abruptly increase when the soft-start current is switched. 36 2004-11-12 TB62217AFG Motor Block Electrical Characteristics 1 (unless otherwise specified, Ta = 25°C and VM = 18V ~ 40 V) Characteristics Logic input voltage Symbol HIGH VIH LOW VIL Logic input clamp voltage Test Circuit Min Typ. Max CLK, STROBE, DATA, ENABLE, SLEEP, and PHASE logic input pins 2.0 ⎯ ⎯ ⎯ ⎯ 0.8 IIK = −10 mA ⎯ ⎯ −0.4 DC CLK, STROBE, DATA, ENABLE, and SLEEP input pins 0.1 0.2 0.3 DC Vin = 3.3 V at each of the CLK, STROBE, DATA, ENABLE, and SLEEP logic input pins ⎯ ⎯ 60 ⎯ ⎯ 60 ⎯ ⎯ 2 DC VIK Logic input hysteresis VIN(HIS) IIN(H) Logic input current IIN(L) Sleep Mode Sleep = L, ALL DC/DC = OFF (IC bias Current) IM1 IM2 Sleep = H OSC_D = 100 kHz, Motor = OFF DC/DC_A = OFF DC/DC_B = 1.5 V DC/DC_C = 3.3 V Iout_chB + Iout_chC = 10 mA ⎯ ⎯ 15 IOH VRS = VM = 40 V, Vout = 0 V, Output OFF Mode 0 ⎯ 1 VRS = VM = Vout = 40 V Output OFF Mode −1 ⎯ 1 Vref = 2.0 V, Vref (gain) = 1/10, TORQUE = (H.H) = 100% ⎯ 100 ⎯ Vref = 2.0 V, Vref (gain) = 1/10, TORQUE = (L.H) = 85% 83 85 87 Operating current (VM pin) Output standby current Output leakage current Comparator reference voltage ratio DC Upper side Lower side Test Condition DC IOL V V µA mA µA HIGH (reference) VRS (HH) MIDDLE HIGH VRS (HL) MIDDLE LOW VRS (LH) Vref = 2.0 V, Vref (gain) = 1/10, TORQUE = (H.L) = 70% 68 70 72 LOW VRS (LL) Vref = 2.0 V, Vref (gain) = 1/10, TORQUE = (L.L) = 50% 48 50 52 DC Unit % Output current difference between channels in constant-current mode ∆Iout1 DC Output current difference between adjacent channels at Iout = 600 mA −5 ⎯ 5 % Constant-current output setting difference ∆Iout2 DC Iout = 600 mA −5 ⎯ 5 % IRS DC VRS = 40 V, VM = 40 V ⎯ ⎯ 10 µA RON (D-S) 1 Iout = 0.6 A, Tj = 25°C, normal direction ⎯ 0.6 0.72 RON (D-S) 1 Iout = 0.6 A, Tj = 25°C, reverse direction ⎯ 0.6 0.72 RON (D-S) 2 Iout = 0.6 A, Tj = 105°C, normal direction ⎯ 0.78 1.01 RON (D-S) 2 Iout = 0.6 A, Tj = 105°C, reverse direction ⎯ 0.78 1.01 RS pin current On-state resistance between motor output transistor drain and source DC 37 Ω 2004-11-12 TB62217AFG Motor Block Electrical Characteristics 2 (unless otherwise specified, Ta = 25°C and VM =18V ~ 40 V) Symbol Test Circuit Vref input voltage Vref DC Vref input current Iref Characteristics Vref attenuation ratio Motor power return voltage Recommended capacitance for OSC_M pin Operating current for motor over current protection circuit Vref (Gain10) Vref (Gain20) VMR (Up) VMR (Down) Cosc_M ISD (Note) Test Condition Min Typ. Max Unit When motor output is active 0.8 ⎯ 3.0 V DC When motor output is inactive and Vref = 2.0 V ⎯ ⎯ 1.0 µA When motor output is active and Vref = 2 V 1/9.6 1/10 1/10.4 DC 1/19.2 1/20 1/20.8 ⎯ 14 15 ⎯ ⎯ V DC 13 14 ⎯ ⎯ External capacitance at fosc_M = 800 kHz ⎯ 220 ⎯ pF DC fchop = 100 kHz 3.0 5.0 6.0 A Note: Over current protection circuit If an abnormal current higher than the corresponding rating flows through a motor, the overcurrent protection circuit triggers the internal shut-down circuit to turn off the output block. In this case, the currently latched function data is cleared. The overcurrent protection circuit is kept tripped for the motor block until (1) the power is turned on again or (2) the SLEEP returns to a high level. If ISD comes in effect, the output becomes inactive (ALL OFF state) and is kept so until a normal condition is recovered. However, be sure to insert a fuse into the power supply for sake of fail-safe. 38 2004-11-12 TB62217AFG Electrical Characteristics DC_3 (unless otherwise specified, Ta = 25°C, VM =18V ~ 40 V, and motor Iout = 1.0 A) Characteristics Chopper current vector Symbol ⎯ Test Circuit DC Test Condition Min Typ. Max θA = 90 (θ16) ⎯ 100 ⎯ θA = 84 (θ15) ⎯ 100 ⎯ θA = 79 (θ14) 93 98 ⎯ θA = 73 (θ13) 91 96 ⎯ θA = 68 (θ12) 87 92 97 θA = 62 (θ11) 83 88 93 θA = 56 (θ10) 78 83 88 θA = 51 (θ9) 72 77 82 θA = 45 (θ8) 66 71 76 θA = 40 (θ7) 58 63 68 θA = 34 (θ6) 51 56 61 θA = 28 (θ5) 42 47 52 θA = 23 (θ4) 33 38 43 θA = 17 (θ3) 24 29 34 θA = 11 (θ2) 15 20 25 θA = 6 (θ1) 5 10 15 θA = 0 (θ0) ⎯ 0 ⎯ 39 Unit 2004-11-12 TB62217AFG Electrical Characteristics DC_4 (unless otherwise specified, Ta = 25°C and VM = 40 V) Characteristics Symbol Test Circuit Vcc DC Internal logic supply voltage TSD operating temperature PRE TSD detection temperature Th_out output voltage LOGIC OUT TjTSD (Note 1) PRE TSD Test Condition (Automatically created within the IC) External capacitance: Under consideration ⎯ DC DC Min Typ. Max Unit 4.5 5.0 5.5 V 130 150 170 °C −20°C (serial setting) 110 150 −30°C (serial setting) 100 140 −30°C (serial setting) 90 130 VTHO (H) H 3.2 ⎯ ⎯ VTHO (L) L 0 ⎯ 0.4 LO (H) H 3.2 ⎯ ⎯ LO (L) L 0 ⎯ 0.4 °C V When pull up to 3.3 V with an external resistance of 1 kΩ V Note: The maximum Tj should not exceed 120°C. Thermal shut-down (TSD) circuit TSD comes in effect if the IC junction reaches a rated temperature. It causes the internal reset circuit to operate, thus turning off the output block. (Only one TSD circuit is mounted on the IC.) The TSD operating temperature can be set anywhere in a range between 130°C (min) and 170°C (max). When TSD comes in effect, the currently latched function data is initialized and the output is stopped. Once the supply voltage drops to or below the POR voltage to shut down the IC, increasing the supply voltage above the POR reset voltage initializes and restarts the IC. 40 2004-11-12 TB62217AFG DC-DC Converter Block Electrical Characteristics (Tj = 0 to 120°C and VM = 7 to 40 V) Characteristics Output voltage error DC-DC converter output-off leakage current On-state resistance between output transistor drain and source (large DCDC Unit: Ach) On-state resistance between output transistor drain and source (small DCDC Unit: B, Cch) Current limiter value (steady state) Current limiter value (starting) Symbol Test Circuit Min Typ. Max Unit VM = 6.5 V~40 V Tj = 0~120°C 0.5 mA~600 mA (large) 0.5 mA~300 mA (small) DCDC output = 1.5 to 5 V −7.0 0 7.0 % VM = 40 V, upper side −0.1 ⎯ 0.1 VM = 40 V, lower side −0.1 ⎯ 0.1 Iout = 300 mA, Tj = 25°C, reverse direction ⎯ 0.7 0.84 RON (DS) A2 Iout = 300 mA, Tj = 105°C, reverse direction ⎯ 0.9 1.1 RON (DS) BC1 Iout = 150 mA, Tj = 25°C, reverse direction ⎯ 1.4 1.7 Iout = 150 mA, Tj = 105°C, reverse direction ⎯ 1.8 2.2 0.8 1.2 1.6 ∆Vout DC IOL_DC DC RON (DS) A1 DC RON (DS) BC2 DC ILIM (L) DC (large) ILIM (S) DC (small) ILIM (L) DC (large) VSD (LU) Feedback voltage Cosc_D ⎯ VFB DC 0.85 0.2 0.3 0.4 0.2 0.3 0.4 In reference to the set voltage. The current limiter is inactive. +30 +40 +50 −40 −30 −20 In reference to the set voltage. The current limiter is active. +30 +40 +50 −20 −15 −5 External capacitor value 47 120 ⎯ pF ⎯ 1.5 ⎯ V ⎯ 0 0.8 DC/DC A, Bch ON 1.25 2.5 3.75 DC/DC Bch, Cch ON 4.5 5.0 ⎯ ⎯ ⎯ DC/DC A, B, Cch All OFF C_SELECT voltage VC_sel DC A 0.6 ILIM (S) DC (small) VSD (LL) OSC_D capacitor value Ω 0.5 DC VSD (L) µA Ω ⎯ VSD (U) Abnormal-voltage protection circuit Test Condition A % % V Reset Block Electrical Characteristics DC (Tj = 0 to 120°C and VM = 7 to 40 V) Characteristics Symbol Test Circuit VMR POR output voltage for VM supply voltage detection ORT signal output current ORT output pin voltage (ALL, Up) DC VMR (ALL, Down) IRST Vort (H) Vort (L) Test Condition Min Typ. Max Rising side. All functions change from OFF to ON. 5.2 ⎯ 6.0 Falling side. All functions change from ON to OFF. 5.2 ⎯ 6.0 2 ⎯ ⎯ 3.2 ⎯ ⎯ 0 ⎯ 0.4 DC Reset pin voltage = 0.4 V DC Pulled up to 3.3 V with an external resistance of 1 kΩ 41 Unit V mA V 2004-11-12 TB62217AFG Motor Block AC Electrical Characteristics (Ta = 25°C, VM = 40 A, and motor impedance = 6.8 mH/5.7 Ω) Characteristics Input clock frequency Symbol Test Circuit fCLK AC Test Condition Min Typ. Max Unit 1.0 ⎯ 25 MHz 40 ⎯ ⎯ 20 ⎯ ⎯ twn (CLK) 20 ⎯ ⎯ tSTROBE 40 ⎯ ⎯ 20 ⎯ ⎯ 20 ⎯ ⎯ 10 ⎯ ⎯ 10 ⎯ ⎯ 10 ⎯ ⎯ 10 ⎯ ⎯ 6.8 mH/5.7 Ω load (Small mode) 0.1 0.3 0.5 0.1 0.3 0.5 6.8 mH/5.7 Ω load (Large mode) 0.1 0.3 0.5 0.1 0.3 0.5 Step Motor mode 6.8 mH/5.7 Ω load between STROBE (↑) and OUT ⎯ 15 ⎯ ⎯ 10 ⎯ Step Motor mode 6.8 mH/5.7 Ω load between Osc down edge and OUT ⎯ 1.2 ⎯ DC Motor mode Between ENABLE edge and OUT 0.3 ⎯ 0.9 0.3 ⎯ 0.9 0.3 ⎯ 0.9 0.3 ⎯ 0.9 Vin = 3.3 V CLK input pin tw (CLK) Minimum clock pulse width Minimum STROBE pulse width twp (CLK) tSTROBE (H) AC AC Vin = 3.3 V Vin = 3.3 V tSTROBE (L) Data setup time Data hold time tsuSIN-CLK tsuST-CLK thSIN-CLK thCLK-ST AC Vin = 3.3 V AC Vin = 3.3 V Tr(s) Tf(s) Tr(L) Tf(L) tpLH (STB) tpHL (STB) Output switching time tpLH (OscM) AC tpHL (OscM) tpLH (ENA) tpHL (ENA) tpLH (PHASE) DC Motor mode Between PHASE edge and OUT tpHL (PHASE) ns ns ns ns µs 2.5 Noise rejection analog dead band time tBLANK (Analog) AC Iout = 0.6 A 200 300 400 ns Motor chopper reference signal oscillation frequency fOSC_M AC C_OSC_M = 220 pF 600 800 1000 kHz Frequency range in which motor chopping is supported fchop (Typ.) Output active (Iout = 0.6 A) with fixed steps 40 100 150 kHz Output active (Iout = 0.6 A) M_osc CLK = 800 kHz ⎯ 100 ⎯ kHz fchop (Min) fchop (Max) Motor chopping setting frequency fchop (M) AC 42 2004-11-12 TB62217AFG Control signal timing chart tw(CLK) CLOCK 50％ 50% tsuST-CLK STROBE thCLK-ST twn(CLK) twp(CLK) 50% tSTROBE(H) tSTROBE(L) tSTROBE thCLK-ST tsuSIN-CLK DATA 50% DATA15 DATA0 50% DATA1 OSCM tpHL(OSCM) fOSC_M tpHL(STB) OUT A（-） 50% tpLH(OSCM) tpLH(STB) 90% OUT A（+） 50% 10% tr PHASE tf 50% tpHL(PHASE) OUT A（-） 50% tpLH(PHASE) OUT A（+） ENABLE 50% 50% tpLH(ENA) OUT A（+） 50% tpHL(ENA) 50% PHASE OUT A ｔＢＬＡＮＫ tＢＬＡＮＫ 43 2004-11-12 TB62217AFG DC-DC Converter AC Electrical Characteristics (Tj = 0 to 120°C and VM = 40 V) Characteristics Symbol Output transistor switching characteristic (large) tr_D(L) Output transistor switching characteristic (small) tr_D(S) Output transistor feed-through prevention time DC-DC setting frequency Test Circuit Test Condition Min Typ. Max ⎯ 0.1 ⎯ ⎯ 0.1 ⎯ ⎯ 0.1 ⎯ ⎯ 0.1 ⎯ 100 300 Unit AC VM = 40 V, DCDC Ach (Large) AC VM = 40 V, DCDC B/Cch (small) tOFF AC VM = 40 V fchop_D (OSC_D) AC ⎯ ⎯ 100 200 kHz AC The DC-DC converter is turned on independently of others, using serial data. fosc_M = 800 kHz and after the STROBE signal has been accepted ⎯ 100 ⎯ ms AC At fosc_M = 800 kHz and after VM becomes 6 V or higher but before the first DC-DC converter starts. ⎯ 20 ⎯ ms ⎯ 20 ⎯ ms tf_D(L) tf_D(S) tStrart Protection circuit dead band (MASK) time at startup _Mask Initial startup delay time tstart1 µs ns Initial startup delay time 2 tstart2 AC At fosc_M = 800 kHz and after the first DC-DC converter has started but before the second DC-DC converter starts. Startup soft mode period tsoft AC fosc_M = 800 kHz ⎯ 20 ⎯ ms LVCO detection dead band time tLVCO AC At fosc_M = 800 kHz and after VM becomes 6 V or lower but before the ORT becomes low. ⎯ 10 ⎯ µs POR detection dead band time tPOR AC At fosc_M = 800 kHz and after VM becomes 6 V or lower but before the internal logic starts. ⎯ 10 ⎯ ms VM 90% Active Pch （ G) Pch GATE Non- Active ODX 10% tr D(L) tf D(L) tr D(S) tf D(S) Active Nch GATE Nch （G) DGND Non- Active ｔOFF H STROBE L Active DC/DC output Non- Active tStart_Mask Mask signal Active Non- Active OSCD fchop_D 44 2004-11-12 TB62217AFG Other Electrical Characteristics AC (Tj = 0 to 120°C and VM = 7 to 40 V) Symbol Test Circuit trst1 (Init) AC Startup reset release time 2 (with no DC-DC converter in use) trst2 (DCDC OFF) ORT output low-pulse width when the motor ISD is active ORT signal output delay time Characteristics Min Typ. Max Unit From VM power-on POR release fosc_M = 800 kHz (114688 clock pulses) ⎯ 140 ⎯ ms AC From VM power-on POR release fosc_M = 800 kHz (262144 clock pulses) ⎯ 320 ⎯ ms trst(ON) AC fosc_M = 800 kHz (32768 clock pulses) 40 ⎯ ⎯ ms tRST (Delay) AC IRST = 20 mA Pulled up to CC with a resistance of 200 Ω Ccc = 0.1 µF ⎯ 50 ⎯ ns tInit_time AC fosc_M = 800 kHz After POR release ⎯ 10 ⎯ ms SLEEP pulse width tSleep (ON) AC fosc_M = 800 kHz 10 ⎯ ⎯ µs SLEEP release delay time tSleep (delay) AC fosc_M = 800 kHz ⎯ ⎯ 10 µs Startup reset release time 1 (Protection mask time) Internal initial setup timing Test Condition tLVCO VM POR tPOR Active POR tInit_time Non- Active Active Internal logic Non- Active 1’stDC/DC t_start1 Active t_soft t_start2 2’ndDC/DC t_soft Non- Active H trst1 / trst2 ORT Non- Active Active L Active Overcurrent detection Non-Active Active ORT Non-Active tRST （Delay) trst（ON) 45 2004-11-12 TB62217AFG Calculating the Motor Setting Constant Current The motor setting current value is determined by RRS and Vref as follows: Iout (max) = Vref (gain) × Vref (V) × serial data ) Torque (Torque = 100, 85, 70, 50% : input 入力シリアルデータ RRS ( Ω ) × 100% Assume, for example: Vref (gain) = 1/10: The attenuation ratio is typically 1/10 when Vref = 1/10. Vref =2 (V) Torque =100 (%) Producing Iout = 1.0 A requires RRS = 0.20 Ω (at least 0.2 W). The Vref (gain) is fixed at 1/10 for stepping motors and selectable from 1/10 and 1/20 for DC motors. The error of constant current setting is 5 % when excluding Vref and Rs . Calculating the Oscillation Frequency (chopping reference frequency) for the Motor and DC-DC Converter Blocks (1) Calculating the OSC Reference Frequency for the Motor Block (typical) fosc_M = 61820 × C (pF) ^ −0.8043 (kHz) Hence, the OSC frequency for the motor block is about 810 kHz when Cosc_M = 220 pF. The chopping frequency for stepping motors is about 1/8 the above frequency, that is, 810/8 (= 101) kHz. In addition, only the fast decay mode is available for DC motor drive. (2) Calculating the OSC Frequency for the DC-DC Converter Block (typical) f OSCD = 5315.3 × C (pF) ^ −0.8341 (kHz) Hence, the OSC frequency for the DC-DC converter block is about 100 kHz when Cosc_D = 120 pF. 46 2004-11-12 TB62217AFG Power Supply Sequence (1) If C_SELECT = low VM POR release VM voltage POR Soft start mode 20 ms 0 DC/DC status Active ALL OFF Full mode Non-active 10 ms Init DATA Extended DATA H 320 ms ORT L Re-writable All clear Initial value Rewritten with serial data All cleared Initialize DC/DC control Re-writable DC/DC all off (C_Sel = L) All cleared Rewritten with serial data Active OSC_M Non-active Active OSC_D Non-active 47 2004-11-12 TB62217AFG (2) Normal Start (C_SELECT = mid or high) VM VM = 15.0 V POR release VM voltage POR Soft start mode 20ms 0 DC/DC status Active ALL OFF Full mode Non-active 10 ms 10 ms Ｈ ORT Ｌ Init DATA Extended DATA Re-writable All clear Initial value Rewritten with serial data All cleared Initialize Ｈ SLEEP Ｌ Controlled by C SELECT DC/DC control Controlled with serial data All cleared DC/DC control start Motor driver control Re-writable OFF (Data cleared) OFF (Data cleared) Operable (if VM = 15 V or higher) Active OSC_M Non-active Active OSC_D Non-active Note: POR release → Initialize 10 ms Initialize → first DCDC start 10 ms DCDC soft start mode 20 ms 48 2004-11-12 TB62217AFG (3) If VM Voltage Drops at Startup (C_SELECT = mid or high) VM VM voltage POR 10 ms Soft start mode 20 ms Below 10 µs 0 DC/DC status Active ALL OFF Full mode Non-active 10 ms Initialize H ORT L Re-writable Init DATA Extended DATA All clear DC/DC control All clear Initial value Rewritten with serial data All cleared Controlled by C_SELECT Re-writable Controlled with serial data All cleared Active OSC_M Non-active Active OSC_D Non-active 49 2004-11-12 TB62217AFG (4) VM Voltage Drop (normal) VM VM = 15.0 V VM voltage POR VM = 0 V DC/DC status Active Full mode ALL OFF Non-active 10 µs H ORT L Re-writable Init DATA Extended DATA Rewritten with serial data ALL L DC/DC control Rewritten with serial data ALL OFF Motor driver control All cleared Re-writable Operable (if VM = 15 V or higher) All cleared OFF (Data cleared) Active Non-active Active OSC_M Non-active Active OSC_D Non-active 50 2004-11-12 TB62217AFG (5) Supply Voltage Drop (if the VM supply voltage does not cross the POR level) VM = 15 V VM voltage POR VM = 0 V DC/DC status Active Full mode Non-active H ORT ORT = H L Re-writable Init DATA Extended DATA Rewritten with serial data DC/DC control Rewritten with serial data Motor driver control All cleared Re-writable All cleared Active Not operating (if VM = 15 V or lower) Non-active Active OSC_M Non-active Active OSC_D Non-active 51 2004-11-12 TB62217AFG (6) Supply Voltage Drop (if the VM supply voltage crosses the POR level) VM = 15 V Shut down (ALL OFF) VM voltage POR Initialize DCDC start VM = 0 V Soft start mode 20 ms 10 µs DC/DC Status Full mode Full mode ALL OFF Active Non-active 10 ms 10 ms H ORT L Init DATA Extended DATA Rewritten with serial data ALL = L DC/DC control Rewritten with serial data ALL = L Motor driver control Not operating (if VM = 15 V or lower) Initial value Controlled by C_SELECT OFF (DATA = ALL L) Rewritten with serial data Rewritten with serial data Not operating (if VM = 15 V or lower) Re-writable All cleared Re-writable All cleared Active Non-active Active OSC_M Non-active Active OSC_D Non-active 52 2004-11-12 TB62217AFG Mixed decay Mode Current Waveform and Setting In constant-current control, the current fluctuation width (current pulsating component) decay mode can be set to any of four points, 0 to 3, using 2-bit serial data. The abbreviation “NF” stands for “negative feedback”. It refers to a point where the output current has reached the set current value. The lower the mixed decay timing value, the lower is the current ripple component (current crest value), leading to a lower current decay ability. fchop CR pin internal clock waveform Set current value DECAY MODE 0 NF 12.5% MIXED DECAY MDT CHARGE MODE → NF: Set current value reached → SLOW MODE → MIXED DECAY TIMMING → FAST MODE → CHARGE MODE DECAY MODE 1 Set current value NF 37.5% MIXED DECAY MDT CHARGE MODE → NF: Set current value reached → SLOW MODE → MIXED DECAY TIMMING → FAST MODE → CHARGE MODE DECAY MODE 2 75% MIXED DECAY Set current value NF MDT CHARGE MODE → NF: Set current value reached → SLOW MODE → MIXED DECAY TIMMING → FAST MODE → CHARGE MODE DECAY MODE 3 Set current value FAST DECAY CHARGE MODE → NF: Set current value reached → FAST MODE 100% 75% 50% 53 25% 0 2004-11-12 TB62217AFG Relationships Between the OSC_M and Output Drive Timing OSC-charge delay OSC-fast delay H fosc _M L tchop Output voltage A Output voltage A H 50% L H 50% 50% L Set current Output current L Charge Slow Fast OSC_M and Charge Delay A delay of up to 1.25 ns (when fchop = 100 kHz and fCR = 800 kHz) can occur between the OSC waveform and internal OSC_M CLK, because the rising level of the OSC waveform is used in converting the OSC waveform to the internal M_CLK. CR-CR CLK delay CR waveform Internal M_CLK 54 2004-11-12 TB62217AFG VSD Threshold Change Timing During DC-DC Converter Block Current Limiter Operation When the limiter enters an operating state, the VSD circuit starts operating if this state continues for 3 OSC_D periods. OSC_D OSC_D_CLK (Internal signal) Case 1 Limiter operating state (1) Normal operation continued VSD threshold change (L: −15%) Case 2 Limiter operating state (1) (2) Normal operation continued VSD threshold change (L: −15%) Case 3 Limiter operating state (1) (2) (3) Normal operation continued VSD threshold change (L: −15%) Case 4 Limiter operating state (1) (2) (3) VSD threshold change (L: −15%) (4) VSD detected → shut-down 55 2004-11-12 TB62217AFG Output-stage Transistor Operation Mode RRS RRS RS pin RS pin RS pin U1 U2 U1 OFF OFF L1 L2 L1 OFF ON ON ON VM RRS VM VM Note Note Load U2 U1 OFF OFF L2 ON L1 L2 ON OFF PGND Change mode ON Note Load Load PGND U2 PGND Slow mode Fast mode Output-stage Transistor Operation Functions CLK U1 U2 L1 L2 CHARGE ON OFF OFF ON SLOW OFF OFF ON ON FAST OFF ON ON OFF Note: The above table summarizes how each transistor behaves when the current flows in the indicated direction. The table below summarizes how each transistor behaves when the current flows in the opposite direction. CLK U1 U2 L1 L2 CHARGE OFF ON ON OFF SLOW OFF OFF ON ON FAST ON OFF OFF ON 56 2004-11-12 TB62217AFG PD-Ta (package power dissipation) This item to be revised once package characteristics are fixed. Transient thermal resistance of THQFP64 stand-alone and on a PC board (for reference only) 5 Rth (stand-alone) Rth (4-layer board) (for reference only) Power dissipation PD (W) 4 3 2 1 0 0 25 50 75 100 125 150 175 Temperature (°C) THQFP64-P-1010-0.50 Note: The board assumed in simulation is Toshiba's ideal board (for reference only). 57 2004-11-12 TB62217AFG Operating Time of The Motor Over Current Protection Circuit (ISD dead band time and ISD operating time) fosc_M oscillation (chopping reference waveform) Output stop (RESET state) Fosc (OSC_M) min Dead band time max ISD operating time ISD BLANK time Time when over current starts flowing through the output stage (over current state start) Reference diagram: Timing chart showing over current flowing through a motor The over current protection circuit has the dead band time to avoid detecting over current accidentally from current spikes in switching. The dead band time is in synchronization with the frequency of the OSC for setting up the chopping frequency (OSC_M). The time between the instant when over current starts flowing through the output stage and the instant when the output stops is as follows: When dead band time = 4 × fosc_M period Minimum: 4 × fosc_M period Maximum: 8 × fosc_M period (+ synchronization time + 1 fosc_M time) However, the operating time stated above applies when the over current flows ideally. The over current circuit may not work depending on the output control mode and timing. Therefore, a protection fuse needs to be inserted in the VM power supply. (The required rating of the fuse varies depending on the conditions under which the IC is used. Therefore, select a rating that will not cause the maximum power dissipation of the IC to be exceeded and that will not pose any problem.) 58 2004-11-12 TB62217AFG Application Circuit Example M M 0.1ohm 0.1ohm For C_SEL:2.5V C N C N D N G M + D S T U O 1 D S R D D 2 S N D T G S U M R O ENABLE SD TEST ENABLE SC ODA Th_OUT FB T C E L E S _ C LOGIC_OUT NC ORT NC LGND VREF SCD LGND VREF SAB NC 100uF 330uH 2V VM(27V) VM + VDIN2 NC OSCM - VDIN1 OSCD from ASIC ENABLE SB from ASIC ENABLE SA CC from ASIC PHASE SD ODB from ASIC PHASE SC FBB from ASIC PHASE SB ODC from ASIC PHASE SA FBC 120pF RB1 330μH RB2 ▲ RC1 RC2 D N G M C N + C D A N N G M T U O 2 A S R 1 A S R A T U O SBD 0.1ohm 100uF 330uH 0.1uF + B 1 2 B B B T S T S U R R U O O D N G M P E E L S from ASIC - RA2 D N G M 220pF + RA1 2 D N G D 1kohm + C S D N T G U O M 1kohm 2 C S R 1kohm 1 C S R 3.3V from ASIC C S T U O from ASIC 1 D D N N G G D M 200kohm + 100uF + - 100uF 0.1ohm M M 59 Output Voltage RA1/RB1/RC1 RA2/RB2/RC2 1.5V 0ohm nothing 3.3V 1.2kohm 1.0kohm 5.0V 5.6kohm 2.4kohm 2004-11-12 TB62217AFG Marking Vendor Name (TOSHIBA) TOSHIBA 217AF ４26GA11 Product Name （TB62~ omitted.） Weekly Code JAPAN Country of Manufacture 1PIN Mark 1PIN Lot traceability correspondence ４ ２ ６ G Ａ １ １ lot code Weekly Manufacture year Wafer / Assembly 1 figure traceability code Production factory Ｇ：Toshiba Oita factory 60 2004-11-12 TB62217AFG Package Dimensions (THQFP64-P-1010-0.50) Heat sink Weight: 0.45 g (typ.) Note: The heat sink provided on the bottom surface of the package is 5.5 mm × 5.5 mm (tentative). 61 2004-11-12