POWERINT DI-117

Design Idea DI-117
®
TinySwitch-III
15 W, 12 V Adapter with <100 mW No-Load Consumption
Application
Device
Power Output
Input Voltage
Output Voltage
Topology
Adapters / General Purpose
TNY279P
15 W
90-265 VAC
12 V
Flyback
Design Highlights
•
•
•
•
•
•
•
The internal MOSFET in U1 conducts current through
the primary winding of T1 during each enabled switching
cycle. When the primary current reaches the MOSFET
current limit, the controller turns it off, and the energy
in T1 is transferred to the output. Schottky diode D7 and
capacitor C8 rectify and filter the output. Inductors L3 and
capacitor C9 attenuate the switching ripple on the output.
Capacitor C3 selects the standard current limit of U1. For
higher efficiency, the next larger (TNY280P) device may
be used. In this case, the value of C3 would be changed to
1 µF, selecting the reduced current limit for the larger device,
but no other circuit changes would be required.
Simple, low cost, low parts count solution
Low input power at no-load: <100 mW at 265 VAC
High efficiency >81% at 90 VAC
Meets CEC requirements for active mode efficiency
(79 % vs. 73.5 % requirement)
>10 dBµV margin to EN55022B conducted EMI limits
Simple, primary-side output overvoltage latching shutdown protects load under fault conditions
Low line frequency leakage current <10 µA
Operation
The primary clamp (D5, R1, C5, R5 and R6) limits the
maximum peak drain voltage below the 700 V breakdown
voltage of U1's internal MOSFET. Resistor R1 dampens the
high-frequency ringing of the T1 leakage inductance.
The TNY279 (U1) in the 8-pin DIP package selected for the
flyback design in Figure 1 is ideal for adapter applications.
The arrangement of the four SOURCE pins on one side of
the package allows a small metal heatsink to be inserted.
This allows the device to operate in a sealed adapter with an
external ambient of 40 °C.
C5
1 nF
R5
R6
1 kV 240 kΩ 240 kΩ
L4
1 mH
D1
1N4005GP
F1
3.15 A
90-265
VAC
C6
68 pF
250 VAC
D2
1N4005
3
C1
10 µF
400 V
D4
1N4005
L3
Ferrite Bead
3.5 × 7.6 mm
10
D7
SB580
9
NC
C2
22 µF
400 V
R1
100 Ω
C8
680 µF
25 V
+12 V, 1.25 A
C9
220 µF
25 V
5
RTN
D6
1N4148
4
EF20
D5
FR107
D3
1N4005GP
T1
1
C11
R7
1 nF
100 V 20 Ω
R8
56 Ω
C7
1 µF
50 V
VR3
BZX79-B6V8
6.8 V
L5
3.3 µH
R4
47 Ω
TinySwitch-III
U1
TNY279P
D
R2
100 Ω
S
R9
1 kΩ
R3
10 kΩ
R11
39 kΩ
1%
EN/UV
C10
220 nF
50 V
BP/M
S
C4
33 pF
1 kV
U2-B
C3
100 nF
50 V
U2-A
PC817A
U3
LM431
R10
3 kΩ
R12
10 kΩ
1%
PI-4417-051106
Figure 1. 15 W, 12 V Output Supply Using TNY279P.
DI-117
September 2006
DI-89 DI-117
The built-in frequency jitter and E-ShieldTM techniques allow
simple EMI filtering to comply with EN55022B. Resistor R2
and C4 form an RC snubber to reduce high-frequency EMI.
Output overvoltage protection (OVP) is provided on the primary
side by sensing the voltage of the auxiliary transformer winding.
Should the main feedback loop open due to failure of U2, then U1
will latch off once the current into the BP/M pin (via VR3) exceeds
6.5 mA. Diode D6 and capacitor C7 rectify and smooth the
output of the auxiliary winding. The value of VR3 is selected
to trigger the OVP latch when the main output, and hence the
auxiliary output voltage, rises above the normal regulation range.
Once triggered, cycling the AC power resets the OVP latch.
To reduce no-load input power and thus increase light load
efficiency, resistor R3 feeds the supply current for U1 from the
auxiliary winding on the transformer.
PI-4415-050806
35
30
Voltage (V)
25
20
Key Design Points
•
•
•
Verify maximum drain voltage is <650 V at high line,
maximum overload. Adjust values of R5, R6 and C5
accordingly. However, avoid making the clamp too
dissipative (low value of R5 and R6, and high value of
C5) as this will increase no-load consumption.
To prevent an increase in no-load consumption or false
OVP triggering, VR3 should be selected to conduct
only when the output voltage is outside the normal
regulation range. Resistor R4 prevents excessive current
from flowing into the BP/M pin.
Fast recovery glass-passivated diodes were selected for
D1 and D3 to reduce low frequency conducted EMI.
Fast diodes such as FR107 are also suitable.
TRANSFORMER PARAMETERS
Core Material
Bobbin
5
0
Winding Details
Winding Order
(Pin Numbers)
3 mm tape margin, shield
(1-NC), tape, primary (3-1),
tape, bias (5-4), tape, 12 V
(10-9), tape
Inductance
-5
0
50
Time (ms)
Figure 2. Worst-Case Open Loop Output Overvoltage
(85 VAC, Full Load).
100
5+5 pin horizontal
Shield: 24T, 28 AWG
Primary: 62T, 31 AWG
Bias: 5T, 4 × 28 AWG
12 V: 7T, 23 AWG T.I.W.
15
10
EF20, N67 or equivalent, gap
for ALG of 203 nH/T2
Primary: 790 µH ±7%
Leakage: 30 µH (max)
Primary Resonant
650 kHz (min)
Frequency
Table 1. Transformer Design Parameters.
T.I.W.: Triple Insulated Wire, NC: No Connection
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Rev. A 09/06