19-1813; Rev 0; 10/00 KIT ATION EVALU LE B A IL A AV Low-Voltage, Low-Power, 16-Bit Smart ADC Functional Diagram appears at end of data sheet. Pin Configuration appears at end of data sheet. Features ♦ Low-Voltage Operation (2.4V to 3.6V) ♦ Low-Noise, 310µA Single-Chip Sensor Signal Conditioning ♦ High-Precision Front End Resolves <400nV of Differential Input Signal ♦ On-Chip DSP and EEPROM Provide Digital Correction of Sensor Errors ♦ 16-Bit Signal Path Compensates Sensor Offset and Sensitivity and Associated Temperature Coefficients ♦ 12-Bit Parallel Digital Output ♦ Analog Output ♦ Compensates a Wide Range of Sensor Sensitivity and Offset ♦ Single-Shot Automated Compensation Algorithm—No Iteration Required ♦ Built-In Temperature Sensor ♦ Three-State, 5-Wire Serial Interface Supports High-Volume Manufacturing ________________________Applications Hand-Held Instruments Piezoresistive Pressure and Acceleration Transducers and Transmitters Industrial Pressure Sensors and Calibrators Smart Battery Charge Systems Weigh Scales and Strain-Gauge Measurement Flow Meters Dive Computers and Liquid-Level Sensing Hydraulic Systems Automotive Systems Ordering Information PART TEMP. RANGE MAX1462CCM 0°C to +70°C PIN-PACKAGE 48 TQFP Customization Maxim can customize the MAX1462 for unique requirements. With a dedicated cell library of more than 90 sensor-specific functional blocks, Maxim can quickly provide customized MAX1462 solutions, including customized microcode for unusual sensor characteristics and 2.2V operation. Contact Maxim for further information. Windows is a registered trademark of Microsoft Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1462 General Description The MAX1462 implements a revolutionary concept in signal conditioning, where the output of its 16-bit analog-to-digital converter (ADC) is digitally corrected over the specified temperature range. This feature can be readily exploited by automotive, industrial, and medical market segments, in applications such as sensors and smart batteries. Digital correction is provided by an internal digital signal processor (DSP) and on-chip 128bit EEPROM containing user-programmed calibration coefficients. The conditioned output is available as a 12-bit digital word and as a ratiometric (proportional to the supply voltage) analog voltage using an on-board 12-bit digital-to-analog converter (DAC). The uncommitted op amp can be used to filter the analog output. The analog front end includes a 2-bit programmablegain amplifier (PGA) and a 3-bit coarse-offset (CO) DAC, which condition the sensor’s output. This coarsely corrected signal is digitized by a 16-bit ADC. The DSP uses the digitized sensor signal, the temperature sensor, and correction coefficients stored in the internal EEPROM to produce the conditioned output. Multiple or batch manufacturing of sensors is supported with a completely digital test interface. Built-in testability features on the MAX1462 result in the integration of three traditional sensor-manufacturing operations into one automated process: • Pretest: Data acquisition of sensor performance under the control of a host test computer. • Calibration and compensation: Computation and storage of calibration and compensation coefficients determined from transducer pretest data. • Final test operation: Verification of transducer calibration and compensation, without removal from the pretest socket. The MAX1462 evaluation kit (EV kit) allows fast evaluation and prototyping, using a piezoresistive transducer (PRT) and a Windows®-based PC. The user-friendly EV kit simplifies small-volume prototyping; it is not necessary to understand fully the test-system interface, the calibration algorithm, or many other details to evaluate the MAX1462 with a particular sensor. Plug the PRT into the EV kit, plug the EV kit into a PC parallel port, connect the sensor to an excitation source (such as a pressure controller), and run the MAX1462 EV kit software. An oven is required for thermal compensation. MAX1462 Low-Voltage, Low-Power, 16-Bit Smart ADC ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD to VSS......................................-0.3V to +6V All Other Pins ...................................(VSS - 0.3V) to (VDD + 0.3V) Short-Circuit Duration, All Outputs .............................Continuous Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C )......1000mW Operating Temperature Range...............................0°C to +70°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.4V to 3.6V, VSS = 0, fXIN = 2MHz, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Supply Voltage (Note 1) VDD During operation Supply Current (Note 2) IDD Continuous conversion 2.4 2.7 3.6 V 310 500 µA 15 Throughput Rate Hz ANALOG INPUT 1.0 MΩ Gain Temperature Coefficient (TC) ±40 ppm/°C Input-Referred Offset TC ±700 nV/°C 90 dB Input Impedance Common-Mode Rejection Ratio RIN CMRR From VSS to VDD PGA AND COARSE-OFFSET DAC (Notes 3, 4) PGA Gain PGA Gain Coarse Offset PGA gain code = 00 43 46 49 PGA gain code = 01 59 61 64 PGA gain code = 10 74 77 80 PGA gain code = 11 90 93 96 CO-DAC code = 111 -164 -149 -134 CO-DAC code = 110 -111 -96 -81 CO-DAC code = 101 -62 -47 -32 CO-DAC code = 100 -10 5 20 CO-DAC code = 000 -20 -5 10 CO-DAC code = 001 32 47 62 CO-DAC code = 010 81 96 111 CO-DAC code = 011 134 149 164 V/V % VDD ADC (Notes 3, 4) 16 Resolution Integral Nonlinearity (Note 5) INL PGA gain code = 00, CO-DAC code = 000 Input-Referred Noise Output-Referred Noise 5kΩ input impedance Bits 0.006 % 1700 nVRMS 3 LSBRMS 260 LSB/°C 1.3 °C TEMPERATURE SENSOR (Note 6) Resolution Linearity 2 TA = 0°C to +70°C _______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC (VDD = +2.4V to 3.6V, VSS = 0, fXIN = 2MHz, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OUTPUT DAC (Note 7) DAC Resolution 12 Bits Integral Nonlinearity INL 1 LSB Differential Nonlinearity DNL 0.5 LSB UNCOMMITTED OP AMP Op Amp Supply Current Input Common-Mode Range Open-Loop Gain 80 VSS + 1.3 CMR AV Offset Voltage (as Unity-Gain Follower) VOS µA VDD - 0.9 60 VIN = max [(VSS + 2.3), (VDD - VSS) / 2] (no load) Output Voltage Swing No load Output Current Range VOUT = (VSS + 0.2V) to (VDD - 0.2V) -30 30 VSS + 0.05 V dB VDD - 0.05 ±200 mV V µA DIGITAL INPUTS: START, CS1, CS2, SDIO (Note 8), RESET, XIN (Note 9), TEST Input High Voltage 80 VIH Input Low Voltage % VDD VIL Input Hysteresis 20 % VDD 1.0 VHYST V Input Leakage IIN VIN = 0 or VDD ±10 µA Input Capacitance CIN (Note 10) 50.0 pF Output Voltage Low VOL ISINK = 200µA 80 % VDD Output Voltage High VOH ISOURCE = 200µA DIGITAL OUTPUTS: D[11...0] Three-State Leakage Current Three-State Output Capacitance IL COUT 20 % VDD CS_ = VSS ±10 µA CS_ = VSS (Note 10) 50.0 pF DIGITAL OUTPUTS: SDIO (Note 8), SDO, EOC, OUT Output Voltage Low VOL ISINK = 200µA 10 % VDD Output Voltage High VOH ISOURCE = 200µA 90 % VDD ±10 µA Three-State Leakage Current Three-State Output Capacitance IL COUT CS_ = VSS CS_ = VSS (Note 10) 50.0 pF Note 1: EEPROM programming requires a minimum VDD = 4.75V. IDD may exceed its limits during this time. Note 2: This value does not include the sensor or load current. This value does include the uncommitted op amp current. Note that the MAX1462 will convert continuously if REPEAT MODE is set in the EEPROM. Note 3: See the Analog Front End, Including PGA, CO-DAC, ADC, and Temperature Sensor section. Note 4: The signal input to the ADC is the output of the PGA plus the output of the CO-DAC. The reference to the ADC is VDD. The plus full-scale input to the ADC is +VDD and the minus full-scale input to the ADC is -VDD. This specification shows the contribution of the CO-DAC to the ADC input. Note 5: See Figure 2 for ADC outputs between ±85%. Note 6: The sensor and the MAX1462 must always be at the same temperature during calibration and use. Note 7: The Output DAC is specified using the external lowpass filter (Figure 8). Note 8: SDIO is an input/output digital pin. It is only enabled as a digital output pin when the MAX1462 receives from the test system the commands 8 hex or A hex (Table 4). Note 9: XIN is a digital input pin only when the TEST pin is high. Note 10: Guaranteed by design. Not subject to production testing. _______________________________________________________________________________________ 3 MAX1462 ELECTRICAL CHARACTERISTICS (continued) Low-Voltage, Low-Power, 16-Bit Smart ADC MAX1462 Pin Description 4 PIN NAME FUNCTION 1, 2, 12, 13, 18, 19, 31, 32, 36, 41–45 N.C. 3 AGND Analog Ground. Connect to VDD and VSS using 10kΩ resistors (see Functional Diagram). 4 START Optional conversion start input signal, used for extending sensor warm-up time. Internally pulled to VDD with a 1MΩ (typ) resistor. 5 I.C. Internally Connected. Leave unconnected. 6 D6 Parallel Digital Output - Bit 6 7 D7 Parallel Digital Output - Bit 7 8 D8 Parallel Digital Output - Bit 8 9 D9 Parallel Digital Output - Bit 9 10 D10 Parallel Digital Output - Bit 10 11 D11 Parallel Digital Output - Bit 11 (MSB) 14, 37, 38 VDD Positive Supply Voltage Input. Connect a 0.1µF bypass capacitor from VDD to VSS. Pins 14, 37, and 38 must all be connected to the positive power supply on the PC board. 15 VSS Negative Supply Input 16, 17 CS1, CS2 Chip-Select Input. The MAX1462 is selected when CS1 and CS2 are both high. When either CS1 or CS2 is low, all digital outputs are high impedance and all digital inputs are ignored. CS1 and CS2 are internally pulled high to VDD with a 1MΩ (typ) resistor. 20 SDIO Serial Data Input/Output. Used only during programming/testing, when the TEST pin is high. The test system sends commands to the MAX1462 through SDIO. The MAX1462 returns the current instruction ROM address and data being executed by the DSP to the test system. SDIO is internally pulled to VSS with a 1MΩ (typ) resistor. SDIO goes high impedance when either CS1 or CS2 is low and remains in this state until the test system initiates conversion. 21 SDO Serial Data Output. Used only during programming/testing. SDO allows the test system to monitor the DSP registers. The MAX1462 returns to the test system results of the DSP current instruction. SDO is high impedance when TEST is low. 22 RESET Reset Input. When TEST is high, a low-to-high transition on RESET enables the MAX1462 to accept commands from the test system. This input is ignored when TEST is low. Internally pulled high to VDD with a 1MΩ (typ) resistor. 23 EOC End of Conversion Output. A high-to-low transition of the EOC pulse can be used to latch the Parallel Digital Output (pins D[11...0]). 24 D0 Parallel Digital Output - Bit 0 (LSB) 25 D1 Parallel Digital Output - Bit 1 26 D2 Parallel Digital Output - Bit 2 No Connection. Not internally connected. _______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC PIN NAME FUNCTION 27 D3 Parallel Digital Output - Bit 3 28 D4 Parallel Digital Output - Bit 4 29 D5 Parallel Digital Output - Bit 5 30 OUT 33 AMPOUT 34 AMP+ Noninverting Input of General-Purpose Operational Amplifier 35 AMP- Inverting Input of General-Purpose Operational Amplifier 39 XOUT Internal Oscillator Output. Connect a 2MHz ceramic resonator (Murata CST200) or crystal from XOUT to XIN. 40 XIN Internal Oscillator Input. When TEST is high, this input must be driven by the test system with a 2MHz, 50% duty cycle clock signal. The resonator does not need to be disconnected in test mode. 46 INP Positive Sensor Input. Input impedance is typically >1MΩ. Rail-to-Rail® input range. 47 TEST Test/Program Mode Enable Input. When high, enables the MAX1462 programming/testing operations. Internally pulled to VSS with a 1MΩ (typ) resistor. 48 INM Negative Sensor Input. Input impedance is typically >1MΩ. Rail-to-Rail input range. Output DAC. The bitstream on OUT, when externally filtered, creates a ratiometric analog output voltage. OUT is proportional to the 12-bit parallel digital output. General-Purpose Operational Amplifier Output Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Detailed Description The main functions of the MAX1462 include: • Analog front end: Includes PGA, CO-DAC, ADC, and temperature sensor. • Test system interface: Writes calibration coefficients to the DSP registers and EEPROM. • Test system interface: Observes the DSP operation. The sensor signal enters the MAX1462 and is adjusted for coarse gain and offset by the analog front end. Five bits in the configuration register set the CO-DAC and the coarse gain of the PGA (Tables 1 and 2). These bits must be properly configured for the optimum dynamic range of the ADC. The digitized sensor signal is stored in a read-only DSP register. The on-chip temperature sensor also has a 3-bit CODAC that places the temperature signal in the ADC operating range. Digitized temperature is also stored in a read-only DSP register. The DSP uses the digitized sensor, the temperature signals, and the correction coefficients to calculate the compensated and corrected output. The MAX1462 supports an automated production environment, where a test system communicates with a batch of MAX1462s and controls temperature and sensor excitation. The three-state digital outputs on the MAX1462 allow parallel connection of transducers, so that all five serial interface lines (XIN, TEST, RESET, SDIO, and SDO) can be shared. The test system selects an individual transducer using CS1 and CS2. The test system must vary the sensor’s input and temperature, calculate the correction coefficients for each unit, load the coefficients into the MAX1462 nonvolatile EEPROM, and test the resulting compensation. The MAX1462 DSP implements the following characteristic equation: D = Gain (1 + G1T + G2T (Signal + Of 2 ) × 0 + Of1T + Of2T 2 )+D OFF _______________________________________________________________________________________ 5 MAX1462 Pin Description (continued) MAX1462 Low-Voltage, Low-Power, 16-Bit Smart ADC Analog Front End, Including PGA, CO-DAC, ADC, and Temperature Sensor where Gain corrects the sensor’s sensitivity, G1 and G2 correct for Gain-TC, T and Signal are the digitized outputs of the analog front end, Of0 corrects the sensor’s offset, Of1 and Of2 correct the Offset-TC, and DOFF is the output offset pedestal. The test system can write the calibration coefficients into the MAX1462 EEPROM or write to the DSP registers directly. The MAX1462 can begin a conversion using either the EEPROM contents or the register contents. When the test system issues commands, the MAX1462 is a serially controlled slave device. The test system observes the MAX1462 DSP operation in order to acquire the temperature and signal ADC results, to verify the calibration coefficients, and to get the output D. The MAX1462 places the contents of several important DSP registers on the serial interface after the tester issues a Start Conversion command. After calibration, compensation, and final test, the MAX1462 is adapted to its sensor and the pair can be removed from the test system. Use the resulting transducer by applying power and the START signal. Latch the 12-bit parallel digital output using the EOC pulse. The maximum conversion rate of the MAX1462 is 15Hz, using a 2MHz resonator. If an analog output is desired, build a simple lowpass filter using the OUT pin, the uncommitted op amp, and a few discrete components (Figure 8). Before the sensor signal is digitized, it must be gained and CO corrected to maximize the ADC dynamic range. There are 2 bits (four possible settings) in the configuration register for the PGA gain, and 3 bits (eight possible settings) for the CO-DAC. The flowchart (Figure 1) shows a procedure for finding the optimum analog front-end settings when the sensor’s characteristics are unknown. Use the tabulated values (Tables 1 and 2) if the peak sensor excursions are known. See the Test System Interface section for details on writing these analog front-end bits. The PGA gain and the CO are very stable but are not accurate. Manufacturing variances on the gain and offset of the MAX1462 analog front-end superposition the residual sensor errors and are later removed during final calibration. For example, suppose the sensor’s sensitivity is +10mV/V with an offset of -12mV/V. Let the supply voltage be +3V. The full-scale (-FS) output of the sensor is then +3V(-12mV/V) = -36mV; +FS is then +3V (-12mV/V + 10mV/V) = -6mV. Following through the flowchart, the PGA gain setting is +3 (gain = +93V/V) and the CO correction setting is +1 (+15mV RTI) - (Referred-to-Input). The coarsely corrected -FS input to the ADC is (-36mV + 15mV)93 = -1.953V. The +FS input to the ADC is (-6mV + 15mV)93 = +0.837V. The input range of the ADC is ±VDD. Thus, the maximum and minimum digitized sensor signals become -1.953 / 3 = -0.651 and +0.837 / 3 = +0.279. Notice that the bridge multiplies the signal by VDD, and the ADC divides the signal by VDD. Thus, the system is ratiometric and not dependent on the DC value of VDD. The ADC output clips to ±1.0 when input values exceed ±VDD. The best signal-to-noise ratio (SNR) is achieved when the ADC input is within ±85% of VDD (Figure 2). Table 1. Nominal PGA Gain Settings PGA SETTING PGA-1 PGA-0 NOMINAL GAIN (V/V) 0 0 0 46 1 0 1 61 2 1 0 77 3 1 1 93 Table 2. Typical Coarse Offset DAC Settings CO-0 % VDD (at ADC INPUT) PGA SETTING 0 (mV RTI) (VDD = 3V) PGA SETTING 1 (mV RTI) (VDD = 3V) PGA SETTING 2 (mV RTI) (VDD = 3V) PGA SETTING 3 (mV RTI) (VDD = 3V) 1 1 -149 -97 -73 -58 -48 1 0 -96 -62 -47 -37 -31 1 0 1 -47 -31 -23 -19 -15 1 0 0 5 3 2 2 1 +0 0 0 0 -5 -3 -2 -2 -1 +1 0 0 1 47 31 23 19 15 +2 0 1 0 96 62 47 37 31 +3 0 1 1 149 97 73 58 48 CO SETTING CO-S CO-1 -3 1 -2 1 -1 -0 6 _______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC temperature. This is done to maximize the dynamic range of the thermal-calibration coefficients (Table 3). Test-System Interface: Writing Calibration Coefficients to the DSP Registers and EEPROM To make the MAX1462 respond to commands from the test system, raise the TEST pin and drive XIN with a –MAKE A TEST SYSTEM VARIABLE CALLED “NoMoreGain.” –SET THE TEMPERATURE TO WHERE THE SENSOR’S SENSITIVITY IS HIGHEST. THIS IS NORMALLY COLD FOR SILICON PRTs. –SET THE PGA GAIN SETTINGS TO MINIMUM. –CLEAR THE VARIABLE “NoMoreGain.” –APPLY MIDSCALE EXCITATION TO THE SENSOR. –FIND THE COARSE OFFSET DAC SETTING WHERE THE DIGITIZED SIGNAL REGISTER IS CLOSEST TO ZERO (MIDSCALE). –APPLY MINIMUM SENSOR EXCITATION. –TEST FOR CLIPPING (DIGITIZED SIGNAL < -0.85). –APPLY MAXIMUM SENSOR EXCITATION. –TEST FOR CLIPPING (DIGITIZED SIGNAL > 0.85). THE SENSOR SENSITIVITY VDD IS TOO LARGE. ADD A RESISTOR BETWEEN THE SERIES TOP OF THE BRIDGE RESISTOR AND VDD , THEN START OVER. YES DID ADC CLIP? IS THE PGA AT MINIMUM GAIN? YES SENSOR NO NO –REDUCE THE PGA GAIN ONE STEP. –SET THE VARIABLE “NoMoreGain.” IS THE PGA AT MAXIMUM GAIN? NO NO IS “NoMoreGain” SET? YES INCREASE THE PGA GAIN ONE STEP. YES RECORD THE PGA AND COARSE OFFSET SETTINGS. CAUTION: CLIPPING IS STILL POSSIBLE FOR LARGE SENSOR’S OFFSET TC AND LARGE TEMPERATURE RANGES. IF NECESSARY, GUARD BAND AGAINST CLIPPING BY REDUCING THE ±0.85 CLIPPING CONSTANTS ABOVE. Figure 1. Flowchart for Determining PGA and CO Settings _______________________________________________________________________________________ 7 MAX1462 The MAX1462 includes an internal temperature-sensing bridge allowing the MAX1462 temperature to be used as a proxy for the sensor temperature. For this reason, the MAX1462 must be mounted in thermal proximity to the sensor. The output of the temperature-sensing bridge is also corrected by a 3-bit coarse-offset DAC and processed by the ADC. The selection of the temperature sensor offset (TSO) bits in the configuration register should be made so that the digitized temperature signal is as close to 0.0 as possible at midscale MAX1462 Low-Voltage, Low-Power, 16-Bit Smart ADC 0.010 4 3 0.006 ERROR (16-BIT LSBs) NONLINEARITY ERROR (% FS) 0.008 0.004 0.002 0 -0.002 -0.004 0 -1 -3 -0.010 -4 -100 -80 -60 -40 -20 0 20 40 60 80 100 SENSOR SIGNAL INPUT OR ADC INPUT/OUTPUT RANGE (%) Figure 2a. Analog Front-End Integrated Nonlinearity (INL) (typ) -100 -80 -60 -40 -20 0 20 40 60 80 100 SENSOR SIGNAL INPUT OR ADC INPUT RANGE (%) Figure 2b. Analog Front-End Differential Nonlinearity (DNL) (typ) two register fields, and command 2 hex requires an EEPROM address. The command word fields are: • Register Data Field: Holds the calibration coefficients to be written into the MAX1462 16-bit registers • EEPROM Address Field: Holds the hexadecimal address of the EEPROM bit to be set (from 00 hex to 7F hex) • Register Address Field: Contains the address of the register (0 to 7) where the calibration coefficient is to be written • Command Field: Instructs the MAX1462 to take a particular action (Table 4) 4.0 NOISE STANDARD DEVIATION (16-BIT LSBs) 1 -2 -0.006 -0.008 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -100 -80 -60 -40 -20 0 20 40 60 80 100 SENSOR SIGNAL INPUT OR ADC INPUT/OUTPUT RANGE (%) Figure 2c. Analog Front-End Noise Standard Deviation of the Samples (typ) 2MHz clock signal. It is not necessary to remove the resonator. RESET must be low for at least 16 clock cycles to initialize the MAX1462. Then, a rising transition on RESET begins a 32-bit serial transfer of the testsystem command word through SDIO. The test system transitions SDIO on falling edges of the XIN clock; the MAX1462 latches data on the rising edge (Figure 3). The 32-bit command word generated by the test system is divided into four fields (Figure 3). The 4-bit command field is interpreted in Table 4. The other fields are usually ignored, except that command 1 hex uses the 8 2 Writing to the DSP Registers Command 1 hex writes calibration coefficients from the test system directly into the DSP registers. Tester commands 8 hex and C hex cause the MAX1462 to start a conversion using the calibration coefficients in the registers. This direct use of the registers speeds calibration and compensation because it does not require EEPROM write-access time. Bringing RESET low clears the DSP registers, so the test system should always write to the registers and start a conversion in a single command timing sequence. As shown in Table 5, seven registers hold the calibration coefficients of the characteristic equation: [DOUT = Gain (1 + G1T + G2T2) (Signal + Of0 + Of1T + Of2T2) + DOFF] implemented by the MAX1462 DSP. All of the registers are 16-bit, two’s complement coding format. When a register is interpreted as an integer, the decimal range is from -32768 (8000 hex) to +32767 (7FFF _______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC 00 01 02 03 29 30 31 00 01 02 03 29 30 31 00 01 02 03 29 30 31 MAX1462 MIN 16 CLK CYCLES 00 01 02 03 29 30 31 XIN TEST RESET D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU SDIO COMMAND 1 COMMAND 2 COMMAND 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E0 E1 LSB MSB LSB REGISTER DATA FIELD COMMAND n E2 E3 E4 E5 E6 R0 R1 R2 C0 C1 C2 C3 NU NU EEPROM ADDRESS FIELD MSB LSB MSB LSB MSB REG. COMMAND ADD NOTE: ALL TRANSITIONS MUST OCCUR WITHIN 100ns OF THE XIN CLOCK EDGE. Figure 3. Test-System Command Timing Diagram Table 3. TSO Settings TSO TSO-2 SETTING TSO-1 TSO-0 TEMPERATURE BRIDGE OFFSET 0 0 0 0 Maximum 1 0 0 1 — 2 0 1 0 — 3 0 1 1 — 4 1 0 0 — 5 1 0 1 — 6 1 1 0 — 7 1 1 1 Minimum hex). Fractional coefficient values range from -1.0 (8000 hex) to +0.99997 (7FFF hex). The register at address 0 is called the Configuration Register. It holds the CO, PGA gain, Op Amp PowerDown, temperature-sensor offset, repeat mode, and reserved bits, as shown in Table 6. The functionality of the CO, PGA gain, and temperature-sensor bits is described in the Analog Front End, Including PGA, CODAC, ADC, and Temperature Sensor section. The Op Amp Power-Down bit enables the uncommitted op amp when set. The repeat-mode bit is tested by the last instruction of the DSP microcode, and, if set, immediately initiates another conversion cycle. The Maxim reserved bits should not be altered. Writing to the Internal EEPROM The test system writes to the EEPROM with commands 4 hex (Block-Erase the entire EEPROM), 2 hex (Write 1 to a single EEPROM bit), and 0 hex (NOOP). The minimum VDD required for all EEPROM write operations is 4.75V. During normal operation (when the TEST pin is low) or when the test system issues instructions A hex or E hex (Start Conversion from EEPROM values), the DSP reads the Calibration Coefficients from the EEPROM. In the normal production flow, determine the calibration coefficients using direct register access. Then load the calibration coefficients into the EEPROM with tester instruction 2 hex. Instruction 4 hex block-erases the EEPROM and is necessary only for a rework or reclaim operation. For each part, the Maxim reserved bits in the Configuration Register should be read before instruction 4 hex is issued, and restored afterwards. The MAX1462 is shipped with its internal EEPROM uninitialized, except for the reserved bits. _______________________________________________________________________________________ 9 MAX1462 Low-Voltage, Low-Power, 16-Bit Smart ADC Table 4. Test System Commands HEX CODE C3 C2 C1 C0 Write a calibration coefficient into a DSP register. COMMAND 1 hex 0 0 0 1 Block-Erase the entire EEPROM (writes “0” to all 128 bits). 4 hex 0 1 0 0 Write 1 to a single EEPROM bit. 2 hex 0 0 1 0 NOOP (NO-OPeration). 0 hex 0 0 0 0 Start Conversion command. The registers are not updated with EEPROM values. SDIO and SDO are enabled as DSP outputs. 8 hex 1 0 0 0 Start Conversion command. The registers are updated with EEPROM values. SDIO and SDO are enabled as DSP outputs. A hex 1 0 1 0 Start Conversion command. The registers are not updated with EEPROM values. SDIO and SDO are disabled. C hex 1 1 0 0 Start Conversion command. The registers are updated with EEPROM values. SDIO and SDO are disabled. E hex 1 1 1 0 3, 5, 6, 7, 9, B, D, F hex — — — — Reserved Table 5. DSP Calibration Coefficient Registers COEFFICIENT REGISTER ADDRESS FUNCTION RANGE Gain 1 Gain correction -32768 to +32767 Integer G1 2 Linear TC gain -1.0 to +0.99997 Fraction G2 3 Quadratic TC gain -1.0 to +0.99997 Fraction Of0 4 Offset correction -1.0 to +0.99997 Fraction Of1 5 Linear TC offset -1.0 to +0.99997 Fraction Of2 6 Quadratic TC offset -1.0 to +0.99997 Fraction DOFF 7 Output midscale pedestal -32768 to +32767 Integer The internal 128-bit EEPROM is arranged as eight 16bit words. These eight words are the configuration register and the seven calibration-coefficient values (Table 7). The MAX1462 EEPROM is bit addressable. The final calibration coefficients must be mapped into the EEPROM locations that are to be set. There is no bitclear instruction. Any EEPROM write operation is necessarily long because the internal charge pump must create and maintain voltages above 20V long enough to cause a reliably permanent change in the memory. Writing an EEPROM bit requires 6ms, so writing the EEPROM typically requires <400ms. Do not decrease the EEPROM write times. To write an EEPROM bit, VDD must be raised to 5.0V (nominal) and the test system must be compliant with the Command Timing Diagram shown in Figure 3. With the 10 FORMAT appropriate driving voltage levels for this new value of supply voltage, perform the following operations: 1) Issue command 0 hex, including the EEPROM address field of the bit to be written. 2) Issue command 2 hex, with the address field used in step 1. Continuously repeat this command 375 times (6ms). 3) Issue command 0 hex, including the EEPROM address field used in steps 1 and 2. The procedure for using command 4 hex (Block-Erase the EEPROM) is similar. Record the Maxim Reserved bits in the configuration register prior to using this command, and restore them afterwards. The number of Block-Erase operations should not exceed 100: 1) Issue command 0 hex. 2) Issue command 4 hex. Continuously repeat this command 375 times (6ms). ______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC EEPROM ADDRESS (HEX) BIT POSITION 01 0 (LSB) CO-0 (LSB) 02 1 CO-1 (MSB) 03 2 CO-S (Sign) 04 3 PGA-1 (MSB) 05 4 PGA-0 (LSB) 06 5 Maxim Reserved 07 6 Maxim Reserved 08 7 Op Amp Power-Down 09 8 Maxim Reserved 0A 9 TSO-0 (LSB) 0B 10 TSO-1 0C 11 TSO-2 (MSB) 0D 12 Maxim Reserved 0E 13 Maxim Reserved 0F 14 Maxim Reserved 10 15 (MSB) DESCRIPTION Repeat Mode 3) Issue command 0 hex. The value of VDD should be lowered to its normal operating values (2.4V to 3.6V) after the EEPROM programming sequence is completed. Test System Interface: Observing the DSP Operation Test system commands 8 hex and A hex initiate a conversion while allowing the test system to observe the operation of the DSP. To calibrate a unit, the test system must know the digitized temperature and sensor signals, stored in DSP registers 8 and 9, and the calibrated and compensated output stored in DSP register 10. The test system should also verify the EEPROM contents, registers 0–7. All these signals pass through DSP register S during the execution of the instruction ROM microcode. The SDO pin outputs the S register values, and the SDIO pin tells the tester which signal is currently on S. There are three internal DSP registers that are directly observable on the SDIO and SDO pins: • S: 16-bit DSP Scratch or Accumulator register, containing the result of the execution of the current microcode instruction. • P: 8-bit DSP Program Pointer register, which holds the address of the instruction ROM microcode. • PS: 8-bit DSP Program Store register. PS is the instruction that the DSP is currently executing. PS is the instruction ROM data at address P. The DSP instructions relevant to the test system are listed in Table 8. After the test system sends the Start Conversion commands 8 hex or A hex, SDIO and SDO are both enabled as MAX1462 serial outputs. The test system should disable (high impedance) its SDIO driver to avoid a bus conflict at this time so that the MAX1462 can drive the pin. After the DSP executes each one of the microcode instructions, the contents of the S, P, and PS registers are output in a serial format (Figure 4). A new DSP instruction and a new state of the S, P, and PS registers are delivered every 16n + 9 clock cycles, where n = 0, 1, 2... after the Start Conversion command completes. The tester should latch the SDIO and SDO bits on the falling edge of the XIN clock signal. When the P and PS registers in Table 8 appear on SDIO, the tester should save the corresponding SDO data. The conversion timing of the MAX1462 is shown in Figure 5 and Table 9. In the figure, the conversion is initiated by a rising transition on the START pin. Equivalently, conversion can be initiated in TEST mode after completion of tester commands 8 hex or A hex, or reinitiated by the state of the Repeat Mode bit in the configuration register. After a conversion is initiated, the 16-bit ADC digitizes the temperature and sensor signals during tADC. Then, the DSP executes the instruction ROM microcode during tDSP. In TEST mode, and during tDSP, SDIO and SDO outputs carry useful information. At 130,586 clock cycles after the Start Conversion command is received, the LSB of the S and P DSP registers is available on SDO and SDIO. The last DSP instruction is D0 hex. The tester can now start a new communication sequence by lowering RESET for at least 16 clock cycles, and then resume driving SDIO. SDIO becomes high impedance when RESET is low. Applications Information Calibration and Compensation Procedure Perform fine calibration by characterizing the sensor/ MAX1462 pair using the test system and then finding the calibration coefficients Gain, G1, G2, Of0, Of1, and Of2 using the equations below. This simple fine-calibration procedure requires three temperatures, denoted A, B, and C, and two sensor excitations, named S and L for small and large. Thus, there are six data points (AS, AL, BS, BL, CS, and CL); six unknown calibration coefficients; and six versions of the characteristic equation, in the form: ______________________________________________________________________________________ 11 MAX1462 Table 6. Configuration Register Bitmap MAX1462 Low-Voltage, Low-Power, 16-Bit Smart ADC Table 7. EEPROM Memory Map EE Address (hex) 10 Contents MSB EE Address (hex) 20 Contents MSB EE Address (hex) 30 Contents MSB EE Address (hex) 40 Contents MSB EE Address (hex) 50 Contents MSB EE Address (hex) 60 Contents MSB EE Address (hex) 70 Contents MSB EE Address (hex) 00 Contents MSB 0F 0E 0D 0C 0B 09 08 07 06 05 04 03 02 Configuration 1F 1E 1D 1C 1B 1A 19 18 2F 2E 2D 2C 2B 2A 29 28 17 16 15 14 13 12 3E 3D 3C 3B 3A 39 27 26 25 24 23 22 4E 4D 4C 4B 4A 38 49 37 36 35 34 33 32 5E 5D 5C 5B 5A 48 59 47 46 45 44 43 42 6E 6D 6C 6B 6A 58 69 57 56 55 54 53 52 7E 7D 7C 7B 7A 79 68 67 66 65 64 63 62 PROGRAM COUNTER (P) (HEX) D0 66 or 6C D1 47 Register 1—Gain D2 11 Register 2—G1 D3 2E Register 3—G2 D4 38 Register 4—Of0 D5 03 Register 5—Of1 D6 22 Register 6—Of2 D7 56 Register 7—DOFF D8 01 Register 8—Temperature Signal D9 3B Register 9—Sensor Signal EA 65 or 6B Register 10—Compensated Output D S REGISTER VALUE Register 0—Configuration 61 LSB 78 77 76 75 74 73 72 DOFF INSTRUCTION CODE (PS) (HEX) 51 LSB Of2 7F 41 LSB Of1 6F 31 LSB Of0 5F 21 LSB G2 4F 11 LSB G1 3F 01 LSB Gain Table 8. Subset of DSP Instruction 12 0A 71 LSB Equation (1) DL − DOFF = Gain 1 + G1TC + G2TC2 Signal + Of + Of T + Of T 2 CL 0 1 C 2 C where DL, DS, and DOFF are determined by the end product specification. DL is the desired MAX1462 output corresponding to the L sensor excitation; DS is the desired MAX1462 output corresponding to the S sensor excitation; D OFF is the desired midscale output; SignalCL is the digitized sensor reading at temperature C with the L sensor excitation applied; and TC is the digitized temperature reading at temperature C. Unstable digitized temperature readings indicate that thermal equilibrium has not been achieved, necessitating increased soak times or a better thermal control. Averaging many readings from the MAX1462 will help filter out AC variations in the sensor excitation and oven temperature. Begin calibration by soaking the sensor and the MAX1462 pair at the first temperature, A, and apply the L excitation to the sensor. Start a conversion and record the digitized temperature TA and the digitized ______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC MAX1462 (16 n + 9)th CLOCK CYCLE (16 (n + 1) + 9)th CLOCK CYCLE XIN LSB MSB SDO S12 S13 S14 S15 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 SDIO PS4 PS5 PS6 PS7 P0 P1 P2 P3 P4 P5 P6 P7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 P0 P1 P2 P3 P4 P5 P6 P7 PS0 PS1 PS2 PS3 LSB MSB LSB DSP CYCLE n-1 MSB DSP CYCLE n DSP CYCLE n+1 NOTE: ALL TRANSITIONS MUST OCCUR WITHIN 100ns OF THE XIN CLOCK EDGE. Figure 4. DSP Serial Output Timing Diagram tCONV VDD tWARM START (OPTIONAL) tADC SDIO & SDO (TEST MODE) tDSP D [11...0] EOC tEOC Figure 5. MAX1462 Conversion Timing signal, SignalAL. Apply the S sensor excitation, and record the digitized signal SignalAS. Repeat this procedure for temperatures B and C, recording TB, SignalBL, SignalBS, TC, SignalCL, and SignalCS. The AL and AS versions of equation 1 may be ratioed to obtain: Similarly, Equation (2a) Equation (2c) SignalAL − ( x ⋅ SignalAS ) + Of0 + Of1TA + Of2TA 2 = 0 1−x SignalCL − ( x ⋅ SignalCS ) Equation (2b) SignalBL − ( x ⋅ SignalBS ) 1− x 1− x + Of0 + Of1TB + Of2TB2 = 0 + Of0 + Of1TC + Of2TC2 = 0 ______________________________________________________________________________________ 13 MAX1462 Low-Voltage, Low-Power, 16-Bit Smart ADC Table 9. MAX1462 Conversion Timing PARAMETER SYMBOL MIN MAX UNITS tWARM 35 — ms ADC Time tADC 130,585 130,585 XIN clk cycles DSP Time tDSP 3220 3364 XIN clk cycles EOC Pulse Width tEOC 8 8 XIN clk cycles Conversion Time tCONV 133,805 133,949 XIN clk cycles Sensor Warmup Time where Equation (3) x= DL − DOFF DS − DOFF Equations 2a, 2b, and 2c form a system of three linear equations, with three unknowns, Of 0, Of 1, and Of2. Solve for Of0, Of1, and Of2. The small sensor excitation versions of equation 1 can be ratioed to obtain: Equation (4a) (YCS − YAS ) + G1(TAYCS − TCYAS ) + G2 TA 2YCS − TC2YAS = 0 Equations 4a and 4b form a system of two linear equations and two unknowns, G1 and G2. Solve for G1 and G2. Equation 1 can now be readily solved for the last unknown, Gain. Arithmetic manipulation can magnify measurement errors and noise. Quantization of the calibration coefficients is another reason to consider adjusting the Gain and DOFF coefficients. To do this, load the MAX1462 registers with the calculated coefficients Gain, G1, G2, Of0, Of1, Of2, and DOFF. Assuming the oven is still at temperature C and the S sensor excitation is still applied, measure the output DCS. Change to the L sensor excitation, and measure DCL. Compute the new Gain coefficient using equation 6. Remeasure DCL, and compute the new DOFF coefficient, given by equation 7. Equation (6) GAINnew = Gain Equation (4b) (YCS − YBS ) + G1(TBYCS − TCYBS ) + G2 TB2YCS − TC2YBS = 0 where: Equation (5a) YAS = DS − DOFF SignalAS + Of0 + Of1TA + Of2 TA 2 Equation (5b) YBS = DS − DOFF SignalBS + Of0 + Of1TB + Of2 TB 2 Equation (5c) YCS = 14 DL − DS DCL − DCS Equation (7) DOFFnew = DOFF + DL − DCL The final calibration coefficients may now be written into the MAX1462 EEPROM. The unit is now ready for final test. This algorithm minimizes the error directly at the six test conditions, AS, AL, BS, BL, CS, and CL. Space the temperatures A, B, and C widely to minimize the SNR of the measurement. If there is a large error remaining in the finished product, move the calibration temperatures closer to the peak error temperatures. Similarly, full-scale sensor excitation may not be the best calibration condition if the sensor has nonlinearities. Move S and L away from full scale. DS − DOFF SignalCS + Of0 + Of1TC + Of2 TC2 ______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC 10 8 ERROR (%FSO) 6 4 2 0 FSO -2 -4 OFFSET -6 -8 -10 0 10 20 30 40 50 60 70 TEMPERATURE (°C) Figure 6. Sensor Characteristics Before Compensation COMPENSATED TRANSDUCER ERROR 0.20 ERROR (% SPAN, 4000 CODES) 0.15 0.10 0.05 FSO 0 OFFSET -0.05 -0.10 67ms. If the Repeat Mode bit is set, conversions repeat at a rate of 15Hz. If the sensor requires more than 35ms of warmup time, START may be used to initiate conversion (Figure 5). If the Repeat Mode bit is set, START should remain high. If the Repeat Mode bit is reset, START may be used to control externally the conversion rate of the MAX1462. After the 12-bit parallel output D is latched, end the conversion by taking START low for at least one clock cycle. The output DAC converts the parallel digital output into a serial bitstream on OUT. A simple external lowpass filter, using the MAX1462 op amp, converts the OUT bitstream into a ratiometric analog voltage (Figure 8). The filter shown is an inverting configuration, but the Gain and DOFF coefficients of the characteristic equation can be adjusted to obtain either polarity. If the op amp is not used, it can be powered down using the Op Amp Power-Down bit in the configuration register. The MAX1462 requires a minimum of external components: • One power-supply bypass capacitor (C1) from VDD to VSS. • One 2MHz ceramic resonator (X1). • Two 10kΩ resistors for the AGND pin. • If an analog output is desired, two 500kΩ resistors and a 1µF capacitor are needed for filtering. MAX1462 Evaluation/ Development Kit -0.15 -0.20 0 10 20 30 40 50 60 70 TEMPERATURE (°C) Figure 7. Compensated Sensor/MAX1462 Pair Figure 6 shows the characteristics of an individual Lucas-NovaSensor model NPH8-100-EH, 0 to 15psig, silicon pressure sensor. Figure 7 shows the result of the compensated sensor/MAX1462 pair. Using the Compensated Sensor/MAX1462 Pair After calibration and removal from the test system, the MAX1462 and the sensor form a mated pair. The START pin can be connected to VDD or left unconnected if the sensor does not require a significant warmup time. Now operation is simple: just apply power and latch the parallel output D when EOC falls. Temperature is digitized during the first half of tADC, so the MAX1462 provides a minimum sensor warmup time of 35ms. Using a 2MHz resonator, the conversion time (tCONV) is nominally The MAX1462 evaluation kit (EV kit) speeds the development of MAX1462-based transducer prototypes and test systems. First-time users of the MAX1462 are strongly encouraged to use this kit, which includes: 1) Evaluation board, with a MAX1462 sample and a silicon pressure sensor, ready for customer evaluation. 2) Interface board that must be connected to a PC parallel port. 3) MAX1462 communication/compensation software (Windows compatible), which enables programming of the MAX1462 one module at a time. 4) Detailed Design/Applications manual, developed for sensor-test engineers. The evaluation kit order number is MAX1462EVKIT. Chip Information TRANSISTOR COUNT: 59,855 SUBSTRATE CONNECTED TO VSS ______________________________________________________________________________________ 15 MAX1462 UNCOMPENSATED SENSOR ERROR Pin Configuration VDD VDD 37 38 39 N.C. XIN XOUT 41 40 N.C. N.C. 43 42 N.C. N.C. 45 44 TEST INP 46 INM 47 34 AMPAMP+ 4 33 AMPOUT I.C. 5 32 N.C. D6 6 31 D7 D8 7 30 N.C. OUT 8 29 D5 D9 9 28 D10 D11 N.C. 10 27 11 26 D4 D3 D2 12 25 D1 23 24 D0 22 RESET EOC 21 20 SDIO SDO 13 Figure 8. Filtering the Output DAC MAX1462 19 RD2 10k 3 18 AMP+ FILTERED ANALOG OUTPUT AGND START N.C. N.C. AMPOUT N.C. 35 17 AGND 36 2 16 MAX1462 OP AMP 1 N.C. CS1 CS2 AMP- N.C. 15 OUT UNFILTERED BIT STREAM 14 RD1 10k RF 500k R1 500k VDD 48 CF 1µF N.C. VDD VSS MAX1462 Low-Voltage, Low-Power, 16-Bit Smart ADC Functional Diagram CS1 CS2 START TEST RESET SDIO SDO EOC AMP- AMP+ VDD 10k AGND 16-BIT INTERFACE TO ALL SIGNALS MAX1462 10k 2MHz RESONATOR XIN X1 VDD OP AMP OSCILLATOR CONTROL LOGIC EEPROM INSTRUCTION ROM XOUT VDD REF = VDD CONFIGURATION REGISTER C1 0.1µF TEMPERATURE SENSOR AMPOUT CORRECTION COEFFICIENTS REGISTERS DAC 16-BIT DIGITAL SIGNAL PROCESSOR (DSP) OUT D [11...0] 12-BIT DIGITAL OUTPUT INP PGA & COARSE OFFSET CORRECTION REF = VDD 16-BIT ADC MUX TEMPERATURE & SENSOR SIGNAL REGISTERS INM VSS SENSOR Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.