MAXIM MAX16060

19-4099; Rev 0; 4/08
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
Features
The MAX16060/MAX16061/MAX16062 are 1% accurate,
quad-/hex-/octal-voltage µP supervisors in a small thin
QFN package. These devices provide supervisory functions for complex multivoltage systems. The MAX16060
monitors four voltages, the MAX16061 monitors six voltages, and the MAX16062 monitors eight voltages.
These devices offer independent outputs for each monitored voltage along with a reset output that asserts
whenever any of the monitored voltages fall below their
respective thresholds (down to 0.4V) or the manual
reset input is asserted. The reset output remains asserted for the reset timeout after all voltages are above their
respective thresholds and the manual reset input is
deasserted. The minimum reset timeout is internally set
to 140ms or can be adjusted with an external capacitor.
o Fixed Thresholds for 3.3V, 2.5V, and 1.8V Systems
o Adjustable Thresholds Monitor Low Voltages
(Down to 0.4V)
o 1% Accurate over Temperature
o Open-Drain Outputs with Internal Pullups Reduce
the Number of External Components
o Fixed 140ms (min) or Capacitor-Adjustable Reset
Timeout
o Manual Reset, Margin Enable, and Tolerance
Select Inputs
o Watchdog Timer
1.6s (typ) Timeout Period
54s Startup Delay After Reset
o Monitors Four (MAX16060), Six (MAX16061), or
Eight (MAX16062) Voltages
o RESET Output Indicates All Voltages Present
o Independent Voltage Monitors
o Guaranteed to Remain Asserted Down to VCC = 1V
o Small (4mm x 4mm) Thin QFN Package
All open-drain outputs have internal 30µA pullups that
eliminate the need for external pullup resistors.
However, each output can be driven with an external
voltage up to 5.5V. Other features offered include a
manual reset input, a tolerance pin for selecting 5% or
10% input thresholds, and a margin enable function for
deasserting the outputs during margin testing.
An additional feature is a watchdog timer that asserts
RESET when the watchdog timeout period (1.6s typ) is
exceeded. The watchdog timer can be disabled by
leaving WDI unconnected.
These devices are offered in 16-, 20-, and 24-pin thin
QFN packages (4mm x 4mm) and are fully specified
from -40°C to +125°C.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX16060_TE+
-40°C to +125°C
16 TQFN-EP*
MAX16061_TP+
-40°C to +125°C
20 TQFN-EP*
MAX16062_TG+
-40°C to +125°C
24 TQFN-EP*
Note: The “_” is a placeholder for the input voltage threshold.
See Table 1. The MAX16060/MAX16061/MAX16062 are available in factory-preset thresholds/configuration combinations.
Choose the desired combination and complete part number
from Table 1.
+Denotes a lead-free package.
For tape-and-reel, add a “T” after the “+.” Tape-and-reel are
offered in 2.5k increments.
*EP = Exposed pad.
Applications
Storage Equipment
Multivoltage ASICs
Servers
Automotive
Networking/Telecommunication Equipment
Typical Operating Circuit
VIN1
VCC
IN1
VIN2
IN2
VIN3
IN3
SRT
MARGIN
RESET
RST
μP
WDI
I/O
MAX16061A
VIN4
IN4
VIN5
IN5
OUT1
OUT2
OUT3
VIN6
OUT4
IN6
OUT5
OUT6
MR
GND
TOL
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX16060/MAX16061/MAX16062
General Description
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
ABSOLUTE MAXIMUM RATINGS
VCC, OUT_, IN_, RESET to GND ..............................-0.3V to +6V
TOL, MARGIN, MR, SRT, WDI to GND ...........-0.3V to VCC + 0.3
Input/Output Current (RESET, MARGIN,
SRT, MR, TOL, OUT_, WDI).........................................±20mA
Continuous Power Dissipation (TA = +70°C)
16-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
20-Pin TQFN (derate 16.9mW/°C above +70°C) ......1355mW
24-Pin TQFN (derate 16.9mW/°C above +70°C) ......1666mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Operating Voltage Range
VCC
Supply Current (Note 3)
ICC
UVLO (Undervoltage Lockout)
UVLO Hysteresis
VUVLO
CONDITIONS
(Note 2)
MIN
TYP
1.0
MAX
UNITS
5.5
V
VCC = 3.3V, OUT_, RESET not asserted
45
65
VCC = 5V, OUT_, RESET not asserted
50
70
1.80
1.98
VCC rising
1.62
VUVLO_HYS
65
µA
V
mV
IN_ (See Table 1)
3.3V threshold, TOL = GND
Threshold Voltages (IN_ Falling)
Adjustable Threshold
(IN_ Falling)
IN_ Hysteresis
IN_ Input Current
2
VTH
VTH
VTH_HYS
3.069
3.102
3.135
3.3V threshold, TOL = VCC
2.904
2.937
2.970
2.5V threshold, TOL = GND
2.325
2.350
2.375
2.5V threshold, TOL = VCC
2.200
2.225
2.250
1.8V threshold, TOL = GND
1.674
1.692
1.710
1.8V threshold, TOL = VCC
1.584
1.602
1.620
TOL = GND
0.390
0.394
0.398
TOL = VCC
0.369
0.373
0.377
IN_ rising
0.5
Fixed thresholds
Adjustable thresholds
3
-100
_______________________________________________________________________________________
V
V
% VTH
16
µA
+100
nA
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
(VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RESET
Reset Timeout
tRP
SRT = VCC
140
200
280
CSRT = 1500pF (Note 4)
2.43
3.09
3.92
ms
nA
CSRT = 100pF
0.206
CSRT = open
SRT Ramp Current
ISRT
VSRT = 0V
SRT Threshold
50
600
740
1.173
1.235
1.293
SRT Hysteresis
IN_ to Reset Delay
tRD
RESET Output-Voltage Low
VOL
RESET Output-Voltage High
VOH
MR Input-Voltage Low
VIL
MR Input-Voltage High
VIH
IN_ falling
mV
20
µs
0.3
VCC = 2.5V, ISINK = 6mA, RESET asserted
0.3
VCC = 1.2V, ISINK = 50µA, RESET asserted
0.3
VCC ≥ 2.0V, ISOURCE = 6µA, RESET
deasserted
0.8 x
VCC
V
V
0.3 x
VCC
V
0.7 x
VCC
V
1
µs
MR Glitch Rejection
100
MR to Reset Delay
200
Pulled up to VCC
V
100
VCC = 3.3V, ISINK = 10mA, RESET asserted
MR Minimum Pulse Width
MR Pullup Resistance
µs
460
12
20
ns
ns
28
kΩ
OUTPUTS (OUT_ )
OUT_ Output-Voltage Low
VOL
OUT_ Output-Voltage High
VOH
IN_ to OUT_ Propagation Delay
tD
VCC = 3.3V, ISINK = 2mA
0.3
VCC = 2.5V, ISINK = 1.2mA
0.3
VCC ≥ 2.0V, ISOURCE = 6µA
(VTH + 100mV) to (VTH - 100mV)
0.8 x
VCC
V
V
20
µs
_______________________________________________________________________________________
3
MAX16060/MAX16061/MAX16062
ELECTRICAL CHARACTERISTICS (continued)
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C). (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.3 x
VCC
V
WATCHDOG TIMER
WDI Input-Voltage Low
VIL
WDI Input-Voltage High
VIH
WDI Pulse Width
Watchdog Timeout Period
0.7 x
VCC
(Note 5)
tWDI
Watchdog Startup Period
Watchdog Input Current
VWDI = 0 to VCC (Note 5)
V
50
ns
1.12
1.60
2.40
s
35
54
72
s
+1
µA
0.3 x
VCC
V
-1
DIGITAL LOGIC
TOL Input-Voltage Low
VIL
TOL Input-Voltage High
VIH
TOL Input Current
V
TOL = VCC
MARGIN Input-Voltage Low
VIL
MARGIN Input-Voltage High
VIH
MARGIN Pullup Resistance
MARGIN Delay Time
0.7 x
VCC
nA
V
0.7 x
VCC
Pulled up to VCC
tMD
100
0.3 x
VCC
Rising or falling (Note 6)
12
V
20
50
28
kΩ
µs
Note 1: Devices are tested at TA = +25°C and guaranteed by design for TA = TMIN to TMAX.
Note 2: The outputs are guaranteed to remain asserted down to VCC = 1V.
Note 3: Measured with WDI, MARGIN, and MR unconnected.
Note 4: The minimum and maximum specifications for this parameter are guaranteed by using the worst case of the SRT ramp current and SRT threshold specifications.
Note 5: Guaranteed by design and not production tested.
Note 6: Amount of time required for logic to lock/unlock outputs from margin testing.
4
_______________________________________________________________________________________
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
45
40
VCC = 5V
50
45
VCC = 3.3V
40
VCC = 2.5V
35
35
1.5
2.0
2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
5.0
1.0025
1.0000
0.9975
0.9950
0.9900
1.5
VOUT_ (mV)
50
0.997
25
600
400
OUT_ LOW
0
2
3
4
5
6
SINK CURRENT (mA)
7
0
8
400
300
200
100
197
196
5
10
15
20
SOURCE CURRENT (μA)
25
30
RESET TIMEOUT DELAY
MAX16060/1/2 toc09
MAX16060/1/2 toc08
OUTPUT GOES LOW
ABOVE THIS LINE
500
198
RESET TIMEOUT PERIOD (ms)
MAX16060/1/2 toc07
600
1
RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION
vs. INPUT OVERDRIVE
MAXIMUM TRANSIENT DURATION (μs)
OUT_ HIGH
0
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
5.5
200
0.996
0.995
5.0
800
VCC - VOUT_ (mV)
75
0.998
2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
1000
MAX16060/1/2 toc05
100
0.999
2.0
OUTPUT VOLTAGE vs. SOURCE CURRENT
OUTPUT VOLTAGE vs. SINK CURRENT
MAX16060/1/2 toc04
NORMALIZED THRESHOLD
1.000
1.0050
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
5.5
NORMALIZED THRESHOLD
vs. TEMPERATURE
1.001
1.0075
0.9925
30
30
MAX16060/1/2 toc03
55
1.0100
MAX16060/1/2 toc06
50
WDI, MARGIN, AND MR UNCONNECTED
NORMALIZED THRESHOLD
SUPPLY CURRENT (μA)
55
60
MAX16060/1/2 toc02
WDI, MARGIN, AND MR UNCONNECTED
SUPPLY CURRENT (μA)
MAX16060/1/2 toc01
60
NORMALIZED THRESHOLD
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
IN1
5V/div
195
OUT1
2V/div
194
193
192
RESET
2V/div
191
SRT = VCC
190
0
1
10
100
INPUT OVERDRIVE (mV)
1000
MAX16060/MAX16061/MAX16062
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
40ms/div
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
RESET TIMEOUT PERIOD
vs. CSRT
10
1
0.1
MAX16060/1/2 toc11
100
1.60
1.59
WATCHDOG TIMEOUT PERIOD (s)
MAX16060/1/2 toc10
1000
tRP (ms)
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
1.50
0.01
0.01
0.1
1
10
100
1000
CSRT (nF)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
MARGIN DISABLE FUNCTION
MARGIN ENABLE FUNCTION
MAX16060/1/2 toc13
MAX16060/1/2 toc12
OUT_ AND RESET ARE
BELOW RESPECTIVE
THRESHOLDS
100μs/div
6
MARGIN
2V/div
MARGIN
2V/div
OUT_
2V/div
OUT_
2V/div
RESET
2V/div
RESET
2V/div
OUT_ AND RESET ARE BELOW RESPECTIVE
THRESHOLDS
100μs/div
_______________________________________________________________________________________
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
PIN
NAME
1
IN3
Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
FUNCTION
2
IN4
Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
3
WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET
is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on WDI is detected.
The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset.
Leave WDI unconnected to disable the watchdog timer. The WDI unconnected-state detector uses a
small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than
200nA. Note that the leakage current specification for most three-state drivers exceeds 200nA.
4
GND
Ground
5
VCC
Unmonitored Power-Supply Input
6
OUT3
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at
IN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to V CC .
7
OUT4
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at
IN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
8
MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset
timeout period after MR is deasserted. MR is pulled up to VCC through a 20kΩ resistor.
9
SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset
timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 106 (Ω) x CSRT (F). For the internal timeout period of 140ms (min), connect
SRT to VCC.
10
MARGIN
11
OUT2
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at
IN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
12
OUT1
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at
IN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
13
RESET
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its
respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all
monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output
has a 30µA internal pullup.
14
IN1
Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
15
IN2
Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
16
TOL
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC
to select 10% threshold tolerance.
—
EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low
thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state),
regardless of the voltage at any monitored input.
_______________________________________________________________________________________
7
MAX16060/MAX16061/MAX16062
Pin Description (MAX16060)
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
MAX16060/MAX16061/MAX16062
Pin Description (MAX16061)
8
PIN
NAME
1
IN4
Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
FUNCTION
2
IN5
Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
3
IN6
Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
4
WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is
asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling
edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to
occur before a reset. Leave WDI unconnected to disable the watchdog timer.
The WDI unconnected-state detector uses a small 400nA current. Therefore, do not connect WDI to anything
that will source or sink more than 200nA. Note that the leakage current specification for most three-state
drivers exceeds 200nA.
5
GND
Ground
6
VCC
Unmonitored Power-Supply Input
7
OUT4
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at
IN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
8
OUT5
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at
IN5 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
9
OUT6
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at
IN6 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
10
MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout
period after MR is deasserted. MR is pulled up to VCC through a 20kΩ resistor.
11
SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset
timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 106 (Ω) x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to
VCC.
12
MARGIN
Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage
at any monitored input.
13
OUT3
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at
IN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
14
OUT2
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at
IN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
15
OUT1
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at
IN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
16
RESET
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective
threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages
exceed their respective thresholds and MR is deasserted. This open-drain output has a 30µA internal pullup.
17
IN1
Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
18
IN2
Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
19
IN3
Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
20
TOL
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to
select 10% threshold tolerance.
—
EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal
resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
_______________________________________________________________________________________
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
PIN
NAME
1
IN5
Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
FUNCTION
2
IN6
Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
3
IN7
Monitored Input Voltage 7. See Table 1 for the input voltage threshold.
4
IN8
Monitored Input Voltage 8. See Table 1 for the input voltage threshold.
5
WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is
asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling edge on
WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before
a reset. Leave WDI unconnected to disable the watchdog timer. The WDI unconnected state detector uses a
small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than 200nA. Note
that the leakage current specification for most three-state drivers exceeds 200nA.
6
GND
Ground
7
VCC
Unmonitored Power-Supply Input
8
OUT5
9
OUT6
10
OUT7
11
OUT8
12
MR
13
SRT
14
MARGIN
15
OUT4
16
OUT3
17
OUT2
18
OUT1
19
RESET
20
IN1
Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
21
IN2
Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
22
IN3
Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
23
IN4
Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
24
TOL
—
EP
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at IN5
exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at IN6
exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
Output 7. When the voltage at IN7 falls below its threshold, OUT7 goes low and stays low until the voltage at IN7
exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
Output 8. When the voltage at IN8 falls below its threshold, OUT8 goes low and stays low until the voltage at IN8
exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period
after MR is deasserted. MR is pulled up to VCC through a 20kΩ resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout
period can be calculated as follows:
Reset Timeout (s) = 2.06 x 106 (Ω) x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to VCC.
Margin Disable Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at
any monitored input.
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4
exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3
exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2
exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1
exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective
threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages
exceed their respective thresholds and MR is deasserted. This open-drain output has a 30µA internal pullup.
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select
10% threshold tolerance.
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance
path from the IC junction to the PCB. Do not use as the electrical connection to GND.
_______________________________________________________________________________________
9
MAX16060/MAX16061/MAX16062
Pin Description (MAX16062)
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
Table 1. Input-Voltage-Threshold Selector
PART
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
MAX16060A
3.3
2.5
ADJ
1.8
—
—
—
—
MAX16060B
3.3
ADJ
ADJ
1.8
—
—
—
—
MAX16060C
ADJ
2.5
ADJ
1.8
—
—
—
—
MAX16060D
3.3
2.5
ADJ
ADJ
—
—
—
—
MAX16060E
ADJ
ADJ
ADJ
ADJ
—
—
—
—
MAX16061A
3.3
2.5
ADJ
1.8
ADJ
ADJ
—
—
MAX16061B
3.3
ADJ
ADJ
1.8
ADJ
ADJ
—
—
MAX16061C
3.3
2.5
ADJ
ADJ
ADJ
ADJ
—
—
MAX16061D
ADJ
2.5
ADJ
1.8
ADJ
ADJ
—
—
MAX16061E
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
—
—
MAX16062A
3.3
2.5
ADJ
1.8
ADJ
ADJ
ADJ
ADJ
MAX16062B
3.3
ADJ
ADJ
1.8
ADJ
ADJ
ADJ
ADJ
MAX16062C
3.3
2.5
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
MAX16062D
ADJ
2.5
ADJ
1.8
ADJ
ADJ
ADJ
ADJ
MAX16062E
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
Note: Other fixed thresholds may be available. Contact factory for availability.
10
______________________________________________________________________________________
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
WDI
MR
SRT
VCC
VCC
WATCHDOG
TIMER CIRCUIT
TIMING
RESET CIRCUIT
RESET
IN1
OUT1
IN2
OUT2
OUTPUT
DRIVER
IN3
OUT3
EN
OUT4
IN4
VCC
TOL
VCC
REFERENCE
UNDERVOLTAGE LOCKOUT
MAX16060D
VCC
MARGIN
Figure 1. MAX16060D Functional Diagram
______________________________________________________________________________________
11
MAX16060/MAX16061/MAX16062
Functional Diagrams
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
Functional Diagrams (continued)
WDI
MR
SRT
VCC
VCC
WATCHDOG
TIMER CIRCUIT
TIMING
RESET CIRCUIT
RESET
IN1
OUT1
IN2
OUT2
IN3
OUT3
OUTPUT
DRIVER
IN4
OUT4
IN5
OUT5
IN6
EN
VCC
TOL
REFERENCE
OUT6
VCC
UNDERVOLTAGE LOCKOUT
MAX16061C
VCC
MARGIN
Figure 2. MAX16061C Functional Diagram
12
______________________________________________________________________________________
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
WDI
MR
SRT
VCC
VCC
WATCHDOG
TIMER CIRCUIT
TIMING
RESET CIRCUIT
RESET
IN1
OUT1
IN2
OUT2
IN3
OUT3
OUTPUT
DRIVER
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
IN8
EN
VCC
TOL
REFERENCE
OUT8
VCC
UNDERVOLTAGE LOCKOUT
MAX16062C
VCC
MARGIN
Figure 3. MAX16062C Functional Diagram
______________________________________________________________________________________
13
MAX16060/MAX16061/MAX16062
Functional Diagrams (continued)
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
Detailed Description
The MAX16060/MAX16061/MAX16062 are 1% accurate
low-voltage, quad-/hex-/octal-voltage µP supervisors in
a small thin QFN package. These devices provide
supervisory functions for complex multivoltage systems.
The MAX16060 monitors four voltages; the MAX16061
monitors six voltages; and the MAX16062 monitors eight
voltages.
These supervisors offer independent outputs for each
monitored voltage along with a reset output that asserts
whenever any of the monitored voltages fall below their
respective thresholds or the manual reset input is
asserted. The reset output remains asserted for the
reset timeout after all voltages are above their respective thresholds and the manual reset input is deasserted. The minimum reset timeout is internally set to
140ms or can be adjusted with an external capacitor.
All open-drain outputs have internal 30µA pullups that
eliminate the need for external pullup resistors.
However, each output can be driven with an external
voltage up to 5.5V. Other features offered include a
manual reset input, a tolerance pin for selecting 5% or
10% input thresholds, and a margin enable function for
deasserting the outputs during margin testing.
Window Detection
A window detector circuit uses two inputs in the configuration shown in Figure 6. External resistors set the two
threshold voltages of the window detector circuit.
External logic gates create the OUT signal. The window
detection width is the difference between the threshold
voltages (Figure 7).
5V
VCC
V1
IN1
V2
IN2
V3
IN3
V4
IN4
MAX16060
OUT1
OUT2
OUT3
OUT4
GND
Figure 4. Quad Undervoltage Detector with LED Indicators
An additional feature is a watchdog timer that asserts
RESET when the watchdog timeout period (1.6s typ) is
exceeded. The watchdog timer can be disabled by
leaving WDI unconnected.
5V
D1
Applications Information
Undervoltage-Detection Circuit
The open-drain outputs of the MAX16060/
MAX16061/MAX16062 can be configured to detect an
undervoltage condition. Figure 4 shows a configuration
where an LED turns on when the comparator output is
low, indicating an undervoltage condition. These
devices can also be used in applications such as system supervisory monitoring, multivoltage level detection,
and VCC bar-graph monitoring (Figure 5).
VIN (5V)
VCC
OUT1
OUT2
IN2
IN3
D3
MAX16060
OUT3
D4
Tolerance (TOL)
The MAX16060/MAX16061/MAX16062 feature a pinselectable threshold tolerance. Connect TOL to GND to
select 5% threshold tolerance. Connect TOL to VCC to
select 10% threshold tolerance.
IN4
OUT4
GND
Figure 5. VCC Bar-Graph Monitoring
14
D2
IN1
______________________________________________________________________________________
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
) (VTH + VTH_HYS)
R1
R2
VINTH
5V
R1
VCC
R1
R2
INPUT
IN1
OUT1
IN2
MAX16060E OUT2
IN3
R2
OUT
OUT3
VTH
R3
IN4
OUT4
R4
(VV
R1 = R2
INTH
TH
)
-1
GND
Figure 8. Setting the Adjustable Input
(
)
Adjustable Input
R3
VTH4 = 1 + R4 VTH
These devices offer several monitor options with
adjustable input thresholds (see Table 1). The threshold
voltage at each adjustable IN_ input is typically 0.394V
(TOL = GND) or 0.373V (TOL = VCC). To monitor a voltage VINTH, connect a resistive-divider network to the circuit as shown in Figure 8.
VINTH = VTH ((R1/R2) + 1)
R1 = R2 ((VINTH/VTH) - 1)
Figure 6. Window Detection
OUT1
V TH1
Large resistors can be used to minimize current through
the external resistors. For greater accuracy, use lowervalue resistors.
Unused Inputs
OUT4
V TH4
Connect any unused IN_ inputs to a voltage above its
threshold.
OUT_ Outputs
OUT
ΔV TH
Figure 7. Output Response of Window Detector Circuit
The OUT_ outputs go low when their respective IN_
inputs drop below their specified thresholds. The output
is open drain with a 30µA internal pullup to VCC. For
many applications, no external pullup resistor is required
to interface with other logic devices. An external pullup
resistor to any voltage from 0 to 5.5V overrides the internal pullup if interfacing to different logic supply voltages.
Internal circuitry prevents reverse current flow from the
external pullup voltage to VCC (Figure 9).
______________________________________________________________________________________
15
MAX16060/MAX16061/MAX16062
(
VTH1 = 1 +
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
VCC = 3.3V
5V
IN_
VTH_
VTH_
100kΩ
VCC
VCC
RESET
OUT_
90%
RESET
10%
tRD
tRP
OUT_
MAX16060
MAX16061
MAX16062
90%
10%
GND
GND
tD
Figure 9. Interfacing to a Different Logic Supply Voltage
tD
Figure 10. Output Timing Diagram
RESET Output
Manual Reset Input (MR)
RESET asserts low when any of the monitored voltages
fall below their respective thresholds or MR is asserted.
RESET remains asserted for the reset timeout period
after all monitored voltages exceed their respective
thresholds and MR is deasserted (see Figure 10). This
open-drain output has a 30µA internal pullup. An external
pullup resistor to any voltage from 0 to 5.5V overrides the
internal pullup if interfacing to different logic supply voltages. Internal circuitry prevents reverse current flow from
the external pullup voltage to VCC (Figure 9).
Many µP-based products require manual reset capability, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low, and during the reset timeout period (140ms min)
after MR returns high. The MR input has an internal
20kΩ pullup resistor to VCC, so it can be left unconnected if not used. MR can be driven with TTL or
CMOS-logic levels, or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual reset function. External
debounce circuitry is not required. If MR is driven from
long cables or if the device is used in a noisy environment, connecting a 0.1µF capacitor from MR to GND
provides additional noise immunity.
Reset Timeout Capacitor
The reset timeout period can be adjusted to accommodate a variety of µP applications. Adjust the reset timeout period (t RP ) by connecting a capacitor (C SRT )
between SRT and GND. Calculate the reset timeout
capacitor as follows:
t (s) x ISRT
CSRT (F) = RP
VTH _ SRT
Connect SRT to VCC for a factory-programmed reset
timeout of 140ms (min).
16
______________________________________________________________________________________
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
Undervoltage Lockout (UVLO)
The MAX16060/MAX16061/MAX16062 feature a VCC
undervoltage lockout (UVLO) that preserves a reset
status even if VCC falls as low as 1V. The undervoltage
lockout circuitry monitors the voltage at VCC. If VCC
falls below the UVLO falling threshold (typically
1.735V), RESET is asserted and all OUT_ are asserted
low. This eliminates an incorrect RESET or OUT_ output
state as VCC drops below the normal VCC operational
voltage range of 1.98V to 5.5V.
During power-up as V CC rises above 1V, RESET is
asserted and all OUT_ are asserted low until V CC
exceeds the UVLO threshold. As VCC exceeds the UVLO
threshold, all inputs are monitored and the correct output
state appears at all the outputs. This also ensures that
RESET and all OUT_ are in the correct state once VCC
reaches the normal VCC operational range.
Power-Supply Bypassing
In noisy applications, bypass VCC to ground with a
0.1µF capacitor as close to the device as possible. The
additional capacitor improves transient immunity. For
fast-rising VCC transients, additional capacitance may
be required.
______________________________________________________________________________________
17
MAX16060/MAX16061/MAX16062
Margin Output Disable (MARGIN)
MARGIN allows system-level testing while power supplies are adjusted from their nominal voltages. Drive
MARGIN low to force RESET and OUT_ high, regardless of the voltage at any monitored input. The state of
each output does not change while MARGIN = GND.
The watchdog timer continues to run when
MARGIN is low, and if a timeout occurs, RESET will
assert tMD after MARGIN is deasserted.
The MARGIN input is internally pulled up to VCC. Leave
MARGIN unconnected or connect to VCC if unused.
RESET 13
8
MR
IN1 14
7
OUT4
6
OUT3
15
14
13
12
11
RESET 16
10
MR
IN1 17
9
OUT6
8
OUT5
7
OUT4
6
VCC
IN2 18
MAX16060
IN2 15
SRT
9
MARGIN
10
OUT3
SRT
11
OUT2
MARGIN
12
TOP VIEW
OUT1
OUT2
TOP VIEW
OUT1
Pin Configurations
MAX16061
IN3 19
1
THIN QFN
(4mm x 4mm)
2
3
4
5
GND
4
WDI
3
IN6
2
IN4
+
GND
TOL 20
WDI
1
VCC
IN5
5
+
IN4
TOL 16
IN3
OUT4
MARGIN
SRT
18
OUT3
TOP VIEW
OUT2
OUT1
THIN QFN
(4mm x 4mm)
17
16
15
14
13
RESET 19
12
MR
IN1 20
11
OUT8
IN2 21
10
OUT7
9
OUT6
8
OUT5
7
VCC
MAX16062
IN3 22
IN4 23
+
IN7
4
5
6
GND
3
WDI
2
IN8
1
IN6
TOL 24
IN5
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
THIN QFN
(4mm x 4mm)
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
16 TQFN
T1644-4
21-0139
20 TQFN
T2044-3
21-0139
24 TQFN
T2444-4
21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.