SNR032 32M-bit Mask ROM ======== Contents ======== 1. INTRODUCTION.........................................................................................................................3 2. FEATURES ...................................................................................................................................3 3. PIN ASSIGNMENTS....................................................................................................................3 4. BUS INTERFACE ........................................................................................................................4 5. ABSOLUTE MAXIMUM RATINGS .........................................................................................5 6. ELECTRICAL CHARACTERISTICS ......................................................................................5 7. APPLICATION CIRCUIT ..........................................................................................................6 8. BONDING PAD ............................................................................................................................9 Ver. 1.2 1 October 21, 2005 SNR032 32M-bit Mask ROM AMENDENT HISTORY Version Date Description Ver 0.1 June 10, 2004 first issue Ver 1.0 September 10, 2004 Added application circuit Ver 1.1 November 1, 2004 Modify the 310 application circuit. Ver 1.2 October 21, 2005 Modify Supply Voltage from Max 6V to Max 3.6V Ver. 1.2 2 October 21, 2005 SNR032 32M-bit Mask ROM 1. INTRODUCTION The SNR032 is a signal power, 32M-bit, read only memory. It is organized as 4M bytes, operates for single 3V power supply, support static standby mode. The SNR032 embedded two different interfaces, one is a standard 8-bit/16-bit interface bus which compatible with SNL310, another one is a special 8-bit AD (address/data) bus which compatible with SNC710. SNR032 offers automatic power-down, with power-down controlled by the chip enable “CEB”. When chip enable goes to high, SNR032 will entry power-down mode in order to save the power consumption. 2. ♦ ♦ ♦ ♦ ♦ FEATURES Power supply: 2.4V ~ 3.6V Memory Size: 32M-bit Totally static operation Embedded a standard 8-bit/16-bit bus interface compatible with SNL310 or a 8-bit AD (address/data) bus interface compatible with SNC710 Access time: 200ns @3V 3. PIN ASSIGNMENTS Symbol TYPE IO I Standard Interface Bus mode select pin “1”->AD bus MODE I AD Bus Interface “1”: AD bus mode “0” for 8-bit/16-bit interface “0”: Standard mode Bus mode select pin “0”->byte mode - “1” word mode interface A[21..8] I Standard ROM A[21..8] A[[7] I Standard ROM A[7] / TESTM TESTM A[6] I Standard ROM A[6] / BS4 ~ BS2 BS4 A[5] I Standard ROM A[5] / BS4 ~ BS2 BS3 A[4] I Standard ROM A[4] / BS4 ~ BS2 BS2 A[3..2] I Standard ROM A[3..2] A[1] I Standard ROM A[1] ALECLK A[0] I Standard ROM A[0] READY D[8..15] - - I/O Data bus D[8..15] - (for word mode only) D[0..7] I/O Data bus D[0..7] AD-Bus D[0..7] CEB I Chip enable pin OEB I Output enable pin VDD P Positive Power supply (3.3volt) Positive Power supply (3.3volt) GND P Negative Power supply (3.3volt) Negative Power supply (3.3volt) Ver. 1.2 Chip enable pin - 3 October 21, 2005 SNR032 32M-bit Mask ROM 4. BUS INTERFACE SNR032 provides three different bus modes to connect to host CPU, AD-bus mode, byte mode and word mode. And the switching between different modes is depended on the pin option “TYPE” and “MODE”. The following table is shown the relation ship of “TYPE”, “MODE” pins and mode switching. Mode TYPE pin MODE pin AD-Bus Interface VDD Don’t care Byte Mode Interface GND GND Word Mode Interface GND VDD 4.1 AD-Bus Interface For 8-bit AD (address/data) bus interface, all the address and data communication between SNC710 and SNR032 are through data bus D[0..7]. SNC710 allows user to connect maximum 2 external mask ROM. The option pin “TYPE” must connected to VDD then the AD-bus interface to be enable. In AD-Bus mode, SNR032 has three bank select pins BS2~BS4 to specify the memory region of SNR032. The address region setting of SNR032 is shown as bellow. BS4~BS2 Address Region 001 0x0200000 ~ 0x03FFFFF 010 0x0400000 ~ 0x05FFFFF 011 0x0600000 ~ 0x07FFFFF 100 0x0800000 ~ 0x09FFFFF 101 0x0A00000 ~ 0x0BFFFFF 110 0x0C00000 ~ 0x0DFFFFF 111 0x0E00000 ~ 0x0FFFFFF Table-1 Note: For the address region 0x00000~0x01FFFFF are reserved, so the setting of bank select pins BS4~BS2 CAN’T be the range 0000~0x0011. Ver. 1.2 4 October 21, 2005 SNR032 32M-bit Mask ROM 5. ABSOLUTE MAXIMUM RATINGS Items Supply Voltage Input Voltage Operating Temperature Storage Temperature 6. Symbol VDD-V VIN TOP TSTG Min -0.3 GND-0.3 0 -55.0 Max 3.6 VDD+0.3 55 125.0 Unit. V V o C o C ELECTRICAL CHARACTERISTICS Item Sym. Min. Typ. Max. Unit Operating Voltage VDD 2.4 - 3.6 V Standby current ISBY - 1.5 2.0 uA Operating Current IOPR - 4 - Address access time tAA - - 150 Ver. 1.2 5 Condition VDD=3V, no load mA VDD=3V, no load ns Vdd=3V October 21, 2005 SNR032 32M-bit Mask ROM 7. Application circuit 7.1 AD Bus Interface (with SNC710) CVDD VDD 49 TEST P0.0 48 CKSEL VDD P0.1 20 P0.2 P0.3 26 XIN P0.4 P0.5 27 XOUT P0.6 P0.7 44 46 BP0 BN0 24 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 VO 23 25 AVDD AGND 330 55 330 330 56 330 57 61 330 62 330 1 2 3 4 5 6 7 8 10 11 P1.0 P1.1 TR3 14 TR4 15 TR5 16 TR6 17 TR7 18 1.5V P1.2 J1 P1.3 P1.4 P1.5 P1.6 P1.7 CE_ CEIN_ READY ALE_CLK CLKIN 37 36 35 34 32 31 30 29 28 VDD AD0 AD1 AD2 AD3 VDD3V CVDD VDD5V VDD CVDD AD0 AD1 AD2 AD3 AD4 AD5 AD4 AD5 AD6 AD7 CEB AD6 AD7 CEB READY ALECLK READY ALECLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VCC P0.1 EXTM P0.2 P0.3 XIN P0.4 27 P0.5 XOUT P0.6 P0.7 24 23 25 TR1 10 TR2 11 TR3 14 TR4 15 TR5 16 TR6 17 TR7 18 TR8 19 BP0 BN0 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 VO AVDD AGND P1.0 AD0 AD1 AD2 AD3 P1.1 P1.2 AD4 AD5 AD6 AD7 P1.3 P1.4 P1.5 P1.6 P1.7 GND GND GND GND GND GND 44 46 CE_ CEIN_ READY ALE_CLK CLKIN 50 330 54 330 55 CEB 330 56 330 57 330 60 330 61 330 62 330 1 2 3 4 5 6 7 8 1 OEB CVDD AD0 AD1 AD2 AD3 37 36 35 34 AD4 AD5 AD6 AD7 32 31 30 29 28 CEB READY ALECLK VDD VDD5V J1 VDD3V CVDD VDD5V VDD CVDD MODE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CEB READY ALECLK U3 J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CVDD AD0 AD1 AD2 AD3 AD4 AD5 CON18 31 32 33 34 35 36 37 38 41 42 43 44 45 46 47 48 AD6 AD7 CEB READY ALECLK CEB 13 38 43 47 52 59 TYPE (0x0200000~0x03FFFFF) 3V VDD3V 42 41 40 39 OEB 12 1.5V CVDD CEB 13 11 C8 0.1uF GND 26 P0.0 CKSEL D8 D9 D10 D11 D12 D13 D14 D15 CON18 OEB CVDD 1 13 11 6 VCC VDD VDD VDD D8 D9 D10 D11 D12 D13 D14 D15 CEB OEB TYPE MODE 2 12 SNR032 AD0/D0 AD1/D1 AD2/D2 AD3/D3 AD4/D4 AD5/D5 AD6/D6 AD7/D7 READYB/A0 ALECLK/A1 A2 A3 BS2/A4 BS3/A5 BS4/A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND 20 41 42 43 44 45 46 47 48 15pF 21 49 48 LXOUT TEST GND 0.1uF RST GND 49 2 51 30 32768 AD0/D0 AD1/D1 AD2/D2 AD3/D3 AD4/D4 AD5/D5 AD6/D6 AD7/D7 39 15pF 22 31 32 33 34 35 36 37 38 GND LXIN 4.7uF CVDD 27 40 50 READY 3 ALECLK READYB/A0 4 ALECLK/A1 5 A2 6 A3 7 CVDD BS2/A4 8 BS3/A5 9 BS4/A6 10 A7 14 A8 15 A9 16 A10 17 A11 18 A12 19 A13 20 A14 21 A15 22 A16 23 A17 24 A18 25 A19 26 A20 51 A21 VDD VDD VDD GND VDD 12 33 53 SNR032 49 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 30 58 47uF Ver. 1.2 (0x0200000~0x03FFFFF) CON18 39 VDD CVDD CVDD CVDD VDD 220K SPEAKER CVDD AD6 AD7 CEB READY ALECLK SNC710 VDD C8 0.1uF AD0 AD1 AD2 AD3 AD4 AD5 GND 9 45 110K READY ALECLK CVDD U1 U2 75K 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 23 24 25 26 51 CVDD VDD VDD MODE CVDD J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CON18 13 38 43 47 52 59 19 AD4 AD5 AD6 AD7 CEB OEB TYPE 27 40 50 3V VDD3V CVDD 42 41 40 39 11 GND TR8 AD0 AD1 AD2 AD3 GND GND GND GND GND GND TR1 13 12 VDD5V TR2 1 OEB CVDD 330 60 CEB 29 SPEAKER 330 54 GND 110K 50 D8 D9 D10 D11 D12 D13 D14 D15 29 75K EXTM 41 42 43 44 45 46 47 48 GND 0.1uF LXOUT 2 RST 15pF 21 READYB/A0 ALECLK/A1 A2 A3 BS2/A4 BS3/A5 BS4/A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND 32768 51 VDD VDD VDD AD0/D0 AD1/D1 AD2/D2 AD3/D3 AD4/D4 AD5/D5 AD6/D6 AD7/D7 GND 15pF 22 220K 31 32 33 34 35 36 37 38 39 LXIN 4.7uF 33 53 49 VDD 47uF AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 12 GND CVDD CVDD GND CVDD VDD GND VDD 30 58 SNR032 SNC710 29 9 45 VDD VCC U1 U2 27 40 50 CVDD READY 3 ALECLK 4 5 6 7 8 CVDD 9 10 14 15 16 17 18 19 20 21 22 23 24 25 26 51 C9 0.1uF (0x0400000~0x05FFFFF) October 21, 2005 SNR032 32M-bit Mask ROM 7.2 Standard ROM interface (with SNL310) VDD VDD VDD 52 53 RST P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 CKSEL TESTM C5 15pF Y2 16MHZ 6 7 XIN XOUT C7 15pF SPEAKER A16 A17 A18 A19 A20 A21 RDB D0 D1 D2 D3 D4 D5 D6 D7 4 25 24 23 22 21 20 18 16 15 14 13 12 11 10 9 8 VO P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 GND GND GND GND GND GND GND 70 69 68 67 66 65 64 63 61 59 58 57 56 55 54 51 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 P2_8 P2_9 P2_10 P2_11 P2_12 P2_13 P2_14 P2_15 U2 D0 D1 D2 D3 D4 D5 D6 D7 31 32 33 34 35 36 37 38 41 42 43 44 45 46 47 48 CEB1 1 RDB 13 11 12 CSB2 CSB1 VDD VDD VDD AD0/D0 AD1/D1 AD2/D2 AD3/D3 AD4/D4 AD5/D5 AD6/D6 AD7/D7 READYB/A0 ALECLK/A1 A2 A3 BS2/A4 BS3/A5 BS4/A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 D8 D9 D10 D11 D12 D13 D14 D15 CEB OEB TYPE MODE VDD SNR032 27 40 50 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 23 24 25 26 28 C6 0.1uF A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 (0x0400000~0x05FFFFF) 41 46 84 50 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 27 29 30 31 32 33 34 35 36 38 39 40 42 43 44 45 5 17 28 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 BP0 BN0 90 89 88 87 86 82 81 80 78 77 76 75 74 73 72 71 P4.15 P4.14 P4.13 P4.12 P4.11 P4.10 P4.9 P4.8 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 47 49 VDD C2 15pF VDD GND C4 0.1uF 1 1.5V GND 83 LXOUT 4.7uF 49 RST 2 VDD VDD C3 GND 79 LXIN C1 15pF Y1 60 R1 220K VDD 1.5V 85 32768HZ 48 26 39 37 CVDD GND VDD CVDD VDD 30 19 SNL310 VDD GND 3 2 U1 C10 47uF 29 VDD Ver. 1.2 7 October 21, 2005 SNR032 32M-bit Mask ROM Device No. 1st external device(CS0) 2nd external device(CS1) 3rd external device(CS2) 4th external device(CS3) Start address 0x0200000 End Address 0x03FFFFF Memory Size 2M words 0x0400000 0x07FFFFF 4M words 0x0800000 0x0BFFFFF 4M words 0x0C00000 0x0FFFFFF 4M words CVDD SPEAKER A16 A17 A18 A19 A20 RDB D0 D1 D2 D3 D4 D5 D6 D7 4 25 24 23 22 21 20 18 16 15 14 13 12 11 10 9 8 VO P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 GND GND GND GND GND GND GND 70 69 68 67 66 65 64 63 61 59 58 57 56 55 54 51 1 RDB 13 12 41 46 84 50 READYB/A0 ALECLK/A1 A2 A3 BS2/A4 BS3/A5 BS4/A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 D8 D9 D10 D11 D12 D13 D14 D15 CEB OEB TYPE MODE CSB2 CSB1 D0 D1 D2 D3 D4 D5 D6 D7 31 32 33 34 35 36 37 38 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 41 42 43 44 45 46 47 48 CEB2 1 RDB 13 74AC138 27 40 50 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 23 24 25 26 28 C6 0.1uF A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 (0x0400000~0x05FFFFF) VDD VDD VDD AD0/D0 AD1/D1 AD2/D2 AD3/D3 AD4/D4 AD5/D5 AD6/D6 AD7/D7 8 READYB/A0 ALECLK/A1 A2 A3 BS2/A4 BS3/A5 BS4/A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 D8 D9 D10 D11 D12 D13 D14 D15 CEB OEB TYPE MODE VDD VDD SNR032 2 12 A_CE_ B_CE_ 15 14 13 12 11 10 9 7 VDD U2 11 Ver. 1.2 VCC 8 CEB1 11 27 29 30 31 32 33 34 35 36 38 39 40 42 43 44 45 5 17 28 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 BP0 BN0 P4.15 P4.14 P4.13 P4.12 P4.11 P4.10 P4.9 P4.8 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 47 49 41 42 43 44 45 46 47 48 VDD VDD VDD AD0/D0 AD1/D1 AD2/D2 AD3/D3 AD4/D4 AD5/D5 AD6/D6 AD7/D7 GND C7 15pF 31 32 33 34 35 36 37 38 GND XOUT D0 D1 D2 D3 D4 D5 D6 D7 GND XIN E1_ E2_ E3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 SNR032 GND 7 4 5 6 49 Y2 16MHZ 6 U2 GND TESTM C5 15pF P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 P2_8 P2_9 P2_10 P2_11 P2_12 P2_13 P2_14 P2_15 GND CKSEL 90 89 88 87 86 82 81 80 78 77 76 75 74 73 72 71 39 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 30 RST CS_ GND VCC A0 A1 A2 VDD C2 15pF VDD GND 53 1 1 2 3 1.5V 39 52 LXOUT 4.7uF 30 C4 0.1uF 2 VDD VDD C3 GND 83 LXIN C1 15pF 2 79 RST VDD 1.5V 85 U5 A22 GND GND Y1 60 CVDD 32768HZ 48 R1 220K CVDD VDD 29 37 VDD C3 104 GND 19 VDD 26 GND 3 SNL310 29 U1 C10 47uF GND VDD 49 VDD 16 VDD VDD 27 40 50 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 23 24 25 26 28 C6 0.1uF A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 (0x0600000~0x07FFFFF) October 21, 2005 SNR032 32M-bit Mask ROM 7 6 CEB 13 GND 15 14 READY/A0 16 A2 BS3/A5 17 ALECLK/A1 BS4/A6 19 18 A3 TYPE MODE A7 OEB 8 A8 9 A9 10 A10 12 11 A11 20 A12 22 21 A13 A16 A17 A18 24 23 A14 25 A15 26 A19 VDD 28 27 A20 BONDING PAD A21 8. 5 4 3 2 1 D8 49 50 VDD GND 47 48 D15 AD6/D6 45 46 GND AD5/D5 44 D14 AD4/D4 42 43 D13 41 D12 39 40 D11 37 38 D10 36 D9 35 VDD 34 AD7/D7 33 AD3/D3 AD0/D0 32 AD2/D2 31 GND 29 30 GND (0.00,0.00) Note: The substrate MUST be connected to Vss in PCB layout. Ver. 1.2 9 October 21, 2005 SNR032 32M-bit Mask ROM DISCLAIMER The information appearing in SONiX web pages (“this publication”) is believed to be accurate. However, this publication could contain technical inaccuracies or typographical errors. The reader should not assume that this publication is error-free or that it will be suitable for any particular purpose. SONiX makes no warranty, express, statutory implied or by description in this publication or other documents which are referenced by or linked to this publication. In no event shall SONiX be liable for any special, incidental, indirect or consequential damages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss of use, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or in connection with the use or performance of this publication or other documents which are referenced by or linked to this publication. This publication was developed for products offered in Taiwan. SONiX may not offer the products discussed in this document in other countries. Information is subject to change without notice. Please contact SONiX or its local representative for information on offerings available. Integrated circuits sold by SONiX are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. The application circuits illustrated in this document are for reference purposes only. SONIX DISCLAIMS ALL WARRANTIES, INCLUDING THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SONIX reserves the right to halt production or alter the specifications and prices, and discontinue marketing the Products listed at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SONIX for such application. Ver. 1.2 10 October 21, 2005