MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface General Description Features S 24-Bit Full-Scale Resolution 20.5-Bit Noise-Free Resolution at 13.75sps 19-Bit Noise-Free Resolution at 120sps S 720nVRMS Noise (MAX11202B) S 3ppm INL S No Missing Codes S Ultra-Low Power Dissipation Operating Mode Current Drain < 300µA (max) Sleep Mode Current Drain < 0.1µA S 2.7V to 3.6V Analog Supply Voltage Range S 1.7V to 3.6V Digital and I/O Supply Voltage Range S Fully Differential Signal Inputs S Fully Differential Reference Inputs S Internal System Clock 2.4576MHz (MAX11202A) 2.2528MHz (MAX11202B) S External Clock S Serial 2-Wire Interface (Clock Input and Data Output) S On-Demand Offset and Gain Self-Calibration S -40°C to +85°C Operating Temperature Range S ±2kV ESD Protection S Lead(Pb)-Free and RoHS-Compliant µMAX Package The MAX11202 is an ultra-low-power (< 300FA max active current), high-resolution, serial output ADC. This device provides the highest resolution per unit power in the industry and is optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. The MAX11202 provides a high-accuracy internal oscillator that requires no external components. When used with the specified data rates, the internal digital filter provides more than 80dB rejection of 50Hz or 60Hz line noise. The MAX11202 provides a simple 2-wire serial interface in the space-saving, 10-pin FMAXM package. The MAX11202 operates over the -40NC to +85NC temperature range. Applications Sensor Measurement (Temperature and Pressure) Portable Instrumentation Battery Applications Weigh Scales Ordering Information PART PIN-PACKAGE OUTPUT RATE (sps) MAX11202AEUB+ 10 FMAX 120 MAX11202BEUB+ 10 FMAX 13.75 Note: All devices are specified over the -40NC to +85NC operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. Selector Guide RESOLUTION (BITS) 4-WIRE SPI, 16-PIN QSOP, PROGRAMMABLE GAIN 4-WIRE SPI, 16-PIN QSOP 2-WIRE SERIAL, 10-PIN μMAX 24 MAX11210 MAX11200 MAX11201 (with buffers) MAX11202 (without buffers) 20 MAX11206 MAX11207 MAX11208 18 MAX11209 MAX11211 MAX11212 16 MAX11213 MAX11203 MAX11205 µMAX is a registered trademark of Maxim Integrated Products, Inc. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-5237; Rev 0; 4/10 MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface ABSOLUTE MAXIMUM RATINGS Any Pin to GND.....................................................-0.3V to +3.9V AVDD to GND........................................................-0.3V to +3.9V DVDD to GND.......................................................-0.3V to +3.9V Analog Inputs (AINP, AINN, REFP, REFN) to GND............................................... -0.3V to (VAVDD + 0.3V) Digital Inputs and Digital Outputs to GND............................................... -0.3V to (VDVDD + 0.3V) ESDHB (AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, SCLK, RDY/DOUT, GND)............................................. Q2kV (Note 1) Continuous Power Dissipation (TA = +70NC) 10-Pin FMAX (derate 5.6mW/NC above +70NC)...........444mW Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -55NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER ADC PERFORMANCE Noise-Free Resolution (Notes 2, 3) Noise (Notes 2, 3) Integral Nonlinearity Zero Error SYMBOL NFR VN INL VOFF CONDITIONS MIN TYP MAX11202A 19 MAX11202B 20.5 MAX11202A 2.1 MAX11202B 0.72 (Note 4) -10 After calibration, VREFP - VREFN = 2.5V -13 Zero Drift 1 MAX Bits FVRMS +10 ppmFSR +13 ppmFSR 50 After calibration, VREFP - VREFN = 2.5V (Note 5) Full-Scale Error -30 Full-Scale Error Drift 3 nV/NC +30 AVDD DC rejection 70 80 DVDD DC rejection 90 100 DC rejection 90 123 ppmFSR ppmFSR/ NC 0.05 Power-Supply Rejection UNITS dB ANALOG INPUTS/REFERENCE INPUTS Common-Mode Rejection Normal-Mode 50Hz Rejection Normal-Mode 60Hz Rejection CMR NMR50 NMR60 50Hz/60Hz rejection, MAX11202A 90 50Hz/60Hz rejection, MAX11202B 144 MAX11202B (Note 6) 65 80.5 MAX11202B (Note 6) 73 87 Common-Mode Voltage Range dB GND dB dB VAVDD V GND 30mV VAVDD + 30mV Q1 FA AIN Dynamic Input Current 5 FA REF Dynamic Input Current 7.5 FA Low input voltage Absolute Input Voltage High input voltage DC Input Leakage 2 Sleep mode (Note 2) V Maxim Integrated MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER AIN Input Capacitance SYMBOL CONDITIONS MIN REF Input Capacitance TYP 10 15 AIN Voltage Range AINP - AINN -VREF fS REF Sampling Rate MAX11202A 246 MAX11202B 225 MAX11202A 246 MAX11202B 225 Input leakage current Q1 UNITS pF pF +VREF VAVDD REF Voltage Range Input Sampling Rate MAX V V kHz kHz LOGIC INPUTS (SCLK, CLK) Input Current Input Low Voltage VIL Input High Voltage VIH Input Hysteresis LOGIC OUTPUT (RDY/DOUT) Output Low Level Output High Level 0.7 x VDVDD VHYS External Clock VOL VOH Floating State Leakage Current FA 0.3 x VDVDD V 200 MAX11202A 2.4576 MAX11202B 2.2528 IOL = 1mA; also tested for VDVDD = 3.6V IOH = 1mA; also tested for VDVDD = 3.6V mV MHz 0.4 0.9 x VDVDD Output leakage current Floating State Output Capacitance V V V Q10 FA 9 pF POWER REQUIREMENTS Analog Supply Voltage AVDD Digital Supply Voltage DVDD Total Operating Current 2.7 3.6 1.7 AVDD + DVDD 230 V 3.6 V 300 FA DVDD Operating Current 45 60 FA AVDD Operating Current 185 245 FA AVDD Sleep Current 0.4 2 FA DVDD Sleep Current 0.35 2 FA 5 MHz 2-WIRE SERIAL-INTERFACE TIMING CHARACTERISTICS SCLK Frequency SCLK Pulse Width Low SCLK Pulse Width High SCLK Rising Edge to Data Valid Transition Time Maxim Integrated fSCLK t1 t2 t3 60/40 duty cycle, 5MHz clock 80 ns 40/60 duty cycle, 5MHz clock 80 ns 40 ns 3 MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SYMBOL SCLK Rising Edge Data Hold Time t4 RDY/DOUT Fall to SCLK Rising Edge t5 Next Data Update Time; No Read Allowed t6 Data Conversion Time t7 Data Ready Time After Calibration Starts (CAL + CNV) t8 SCLK High After RDY/DOUT Goes Low to Activate Sleep Mode t9 Time from RDY/DOUT Low to SCLK High for Sleep-Mode Activation t10 Data Ready Time After Wake-Up from Sleep Mode t11 Data Ready Time After Calibration from Sleep Mode Wake-Up (CAL + CNV) t12 Note Note Note Note Note 4 CONDITIONS Allows for positive edge data read MIN TYP MAX UNITS 3 ns 0 ns MAX11202A 155 MAX11202B 169 MAX11202A 8.6 MAX11202B 73 MAX11202A 208.3 MAX11202B 256.1 Fs ms ms MAX11202A 0 8.6 MAX11202B 0 73 MAX11202A 0 8.6 MAX11202B 0 73 MAX11202A 8.6 MAX11202B 73 MAX11202A 208.4 MAX11202B 256.2 ms ms ms ms 2: These specifications are not fully tested and are guaranteed by design and/or characterization. 3: VAINP = VAINN. 4: ppmFSR is parts per million of full-scale range. 5: Positive full-scale error includes zero-scale errors. 6: The MAX11202A has no normal-mode rejection at 50Hz or 60Hz. Maxim Integrated MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface Typical Operating Characteristics (VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25NC.) TA = +85°C TA = +25°C 160 TA = -45°C 220 180 TA = +25°C 160 TA = -45°C 140 140 120 120 100 2.85 3.00 3.15 3.30 3.45 0.4 0.2 TA = +25°C TA = -45°C TA = +85°C 0 2.70 2.85 3.00 3.15 3.30 3.45 3.60 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD VOLTAGE (V) ACTIVE SUPPLY CURRENT vs. TEMPERATURE (MAX11202A) ACTIVE SUPPLY CURRENT vs. TEMPERATURE (MAX11202B) SLEEP CURRENT vs. TEMPERATURE (MAX11202A/MAX11202B) 250 0.8 VAVDD = 3.6V 150 200 CURRENT (µA) CURRENT (µA) TOTAL VAVDD = 3.6V 150 MAX11202 toc06 1.0 MAX11202 toc05 300 100 VAVDD = 3.6V VDVDD = 1.8V 0.6 0.4 100 VDVDD = 1.8V 50 VDVDD = 1.8V 50 0 0.2 -25 -5 15 35 55 75 95 VDVDD VAVDD TOTAL 0 0 -45 -25 -5 15 35 55 75 -45 95 -25 -5 15 35 55 75 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) DIGITAL ACTIVE CURRENT vs. DVDD VOLTAGE DIGITAL SLEEP CURRENT vs. DVDD VOLTAGE (MAX11202A/MAX11202B) INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE 90 80 70 MAX11202B 2.0 TA = +25°C 1.5 1.0 95 MAX11202 toc09 TA = -45°C VDVDD = 1.8V VAVDD = 3.0V 2.5 FREQUENCY (MHz) MAX11202A 2.5 2.6 MAX11202 toc08 110 VAVDD = 3.6V CURRENT (µA) VAVDD = 3.6V TA = +85°C, +25°C, -45°C 100 3.0 MAX11202 toc07 -45 CURRENT (µA) 0.6 AVDD VOLTAGE (V) TOTAL 200 3.60 MAX11202 toc04 250 120 0.8 AVDD VOLTAGE (V) 300 130 VDVDD = 1.8V 100 2.70 CURRENT (µA) TA = +85°C 200 CURRENT (µA) CURRENT (µA) 180 VDVDD = 1.8V CURRENT (µA) 220 1.0 MAX11202 toc02 VDVDD = 1.8V 200 240 MAX11202 toc01 240 ANALOG SLEEP CURRENT vs. AVDD VOLTAGE (MAX11202A/MAX11202B) ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (MAX11202B) MAX11202 toc03 ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (MAX11202A) MAX11202A 2.4 2.3 MAX11202B 2.2 TA = +85°C 60 0.5 50 40 2.1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 DVDD VOLTAGE (V) Maxim Integrated 2.0 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 DVDD VOLTAGE (V) -45 -25 -5 15 35 55 75 95 TEMPERATURE (°C) 5 MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface Typical Operating Characteristics (continued) (VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25NC.) MAX11202B MAX11202 toc11 3.0 2.0 1.5 3.0 MAX11202B -45 NOISE HISTOGRAM (MAX11202A, 120sps) NOISE HISTOGRAM (MAX11202B, 13.75sps) LONG-TERM ADC READINGS (MAX11202A) 6 4 20 30,000 CONSECUTIVE READINGS 18 16 TA = +25°C VREF = 2.5V RMS = 0.72µV MEAN = 4.1µV 14 12 10 8 6 75 TA = +25°C VIN = 0V RMS = 2.1µV 10 4 2 -25 15 ADC READING (µV) TA = +25°C VREF = 2.5V RMS = 2.1µV MEAN = 5.0µV 0.5 1.0 1.5 2.0 2.5 95 MAX11202 toc15 -2.5 -2.0 -1.5 -1.0 -0.5 0 3.60 MAX11202 toc14 3.45 NUMBER OF READINGS (%) 3.30 MAX11202 toc13 5 0 -5 -10 2 -15 0 0 2.0 4.3 6.7 9.0 2.89 3.74 4.59 5.44 6.29 0.2 0 0.4 0.6 0.8 1.0 TIME (min) LONG-TERM ADC READINGS (MAX11202B) OFFSET ERROR vs. VREF (MAX11202A/MAX11202B) OFFSET ERROR vs. TEMPERATURE (MAX11202A/MAX11202B) 2 1 0 -1 -2 -3 2.0 VREF = VREFP - VREFN 1.5 TA = +25°C 1.0 0.5 TA = +85°C 0 2.5 TA = -45°C MAX11202 toc18 ADC OUTPUT (µV) OFFSET ERROR (ppmFSR) 3 2.04 ADC OUTPUT (µV) TA = +25°C VIN = 0V RMS = 0.72µV 4 1.19 11.3 OFFSET ERROR (ppmFSR) 5 -0.3 MAX11202 toc16 -2.7 MAX11202 toc17 NUMBER OF READINGS (%) 0 -5 15 35 55 TEMPERATURE (°C) 3.15 12 ADC READING (µV) MAX11202B INPUT VOLTAGE (V) 3.00 30,000 CONSECUTIVE READINGS 8 1.5 AVDD VOLTAGE (V) 2.85 14 10 MAX11202A 2.0 0.5 0 2.70 2.5 1.0 0.5 2.1 VREF = 3.0V 3.5 MAX11202A 2.5 1.0 2.2 4.0 NOISE (µVRMS) 2.4 VREF = 2.5V 3.5 NOISE (µVRMS) FREQUENCY (MHz) MAX11202A 2.3 4.0 MAX11202 toc10 VDVDD = 1.8V 2.5 NOISE vs. TEMPERATURE NOISE vs. INPUT VOLTAGE 2.6 MAX11202 toc12 INTERNAL OSCILLATOR FREQUENCY vs. AVDD VOLTAGE CALIBRATED AT +25°C 2.0 1.5 1.0 0.5 -0.5 -4 -1.0 -5 0 2 4 6 TIME (min) 6 8 10 1.0 1.5 2.0 2.5 3.0 VREF VOLTAGE (V) 3.5 4.0 0 -45 -25 -5 15 35 55 75 95 TEMPERATURE (°C) Maxim Integrated MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface Typical Operating Characteristics (continued) (VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25NC.) TA = +85°C 2 TA = +25°C 0 -2 -4 TA = -45°C -6 -8 -2.5 -2.0 -1.5 -1.0 -0.5 0 -40 4 2 0 -2 -4 -FS ERROR -25 -5 15 35 55 -140 75 10 1 100 1k 10k 100k FREQUENCY (Hz) PSRR vs. FREQUENCY (MAX11202B) CMRR vs. FREQUENCY (MAX11202A/MAX11202B) NORMAL-MODE FREQUENCY RESPONSE (MAX11202A) 0 -20 -20 -40 VAVDD -100 GAIN (dB) CMRR (dB) -60 -60 -80 MAX11202A -100 VDVDD -120 -140 100 1k 10k 100k -80 -100 -120 MAX11202B -140 -140 10 1 FREQUENCY (Hz) 100 1k 10k 1 100k 10 -20 1k NORMAL MODE REJECTION OF 50Hz TO 60Hz (MAX11202B) 0 MAX11202 toc25 0 100 FREQUENCY (Hz) FREQUENCY (Hz) NORMAL-MODE FREQUENCY RESPONSE (MAX11202B) -20 -40 GAIN (dB) -40 -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 1 10 100 FREQUENCY (Hz) Maxim Integrated -60 MAX11202 toc26 10 MAX11202 toc24 MAX11202 toc22 0 -40 GAIN (dB) VDVDD -120 -8 -45 -40 1 VAVDD TEMPERATURE (°C) -20 -120 -80 INPUT VOLTAGE (V) 0 -80 -60 -100 -6 0.5 1.0 1.5 2.0 2.5 MAX11202 toc21 -20 -10 -10 PSRR (dB) +FS ERROR 6 0 MAX11202 toc23 INL (ppmFSR) 4 VREF = 2.5V 8 PSRR (dB) 6 10 PSRR vs. FREQUENCY (MAX11202A) MAX11202 toc20 VAVDD = 3.0V VDVDD = 1.8V VREF = 2.5V VIN(CM) = 1.5V 8 NORMALIZED FULL-SCALE ERROR (ppmFSR) 10 FULL-SCALE ERROR vs. TEMPERATURE (MAX11202A/MAX11202B) MAX11202 toc19 INTEGRAL NONLINEARITY vs. INPUT VOLTAGE (MAX11202A/MAX11202B) 1k 40 45 50 55 60 65 70 FREQUENCY (Hz) 7 MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface Functional Diagram TIMING AVDD CLOCK GENERATOR CLK DIGITAL LOGIC AND SERIALINTERFACE CONTROLLER SCLK DVDD GND AINP AINN REFP 3RD-ORDER DELTA-SIGMA MODULATOR DIGITAL FILTER (SINC4) RDY/DOUT REFN MAX11202 Pin Configuration TOP VIEW + GND 1 REFP 2 REFN AINN AINP 10 CLK 9 SCLK 3 8 RDY/DOUT 4 7 DVDD 5 6 AVDD MAX11202 µMAX Pin Description 8 PIN NAME 1 GND Ground. Ground reference for analog and digital circuitry. FUNCTION 2 REFP Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage between AVDD and GND. 3 REFN Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a voltage between AVDD and GND. 4 AINN Negative Fully Differential Analog Input 5 AINP Positive Fully Differential Analog Input 6 AVDD Analog Supply Voltage. Connect a supply voltage between +2.7V to +3.6V with respect to GND. 7 DVDD Digital Supply Voltage. Connect a digital supply voltage between +1.7V to +3.6V with respect to GND. Maxim Integrated MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface Pin Description (continued) 8 RDY/DOUT 9 SCLK 10 CLK Data Ready Output/Serial Data Output. This output serves a dual function. In addition to the serial data output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic low. RDY/DOUT changes on the rising edge of SCLK. Serial Clock Input. Apply an external serial clock to SCLK. External Clock Signal Input. The internal clock shuts down when CLK is driven by an external clock. Use a 2.4576MHz oscillator (MAX11202A) or a 2.2528MHz oscillator (MAX11202B). Detailed Description The MAX11202 is an ultra-low-power (< 240FA active), high-resolution, low-speed, serial-output ADC. This device provides the highest resolution per unit power in the industry and is optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. The MAX11202 provides a high-accuracy internal oscillator, which requires no external components. When used with the specified data rates, the internal digital filter provides more than 80dB rejection of 50Hz or 60Hz line noise. The MAX11202 provides a simple, system-friendly, 2-wire serial interface in the space-saving, 10-pin FMAX package. Analog Inputs The MAX11202 accepts two analog inputs (AINP and AINN). The modulator input range is bipolar (-VREF to +VREF). Internal Oscillator The MAX11202 incorporates a highly stable internal oscillator that provides the system clock. The system clock runs the internal state machine and is trimmed to 2.4576MHz (MAX11202A) or 2.2528MHz (MAX11202B). The internal oscillator clock is divided down to run the digital and analog timing. Reference The MAX11202 utilizes power-on reset (POR) supplymonitoring circuitry on both the digital supply (DVDD) and the analog supply (AVDD). The POR circuitry ensures proper device default conditions after either a digital or analog power-sequencing event. The MAX11202 provides differential inputs REFP and REFN for an external reference voltage. Connect the external reference directly across the REFP and REFN to obtain the differential reference voltage. The commonmode voltage range for VREFP and VREFN is between 0 and VAVDD. The differential voltage range for REFP and REFN is 1V to VAVDD. The MAX11202 performs a self-calibration operation as part of the startup initialization sequence whenever a digital POR is triggered. It is important to have a stable reference voltage available at the REFP and REFN pins to ensure an accurate calibration cycle. If the reference voltage is not stable during a POR event, the part should be calibrated once the reference has stabilized. The part can be programmed for calibration by using 26 SCLKs as shown in Figure 3. The MAX11202 contains an on-chip, digital lowpass filter that processes the 1-bit data stream from the modulator using a SINC4 (sinx/x)4 response. When the device is operating in single-cycle conversion mode, the filter is reset at the end of the conversion cycle. When operating in continuous conversion latent mode, the filter is not reset. The SINC4 filter has a -3dB frequency equal to 24% of the data rate. Power-On Reset (POR) The digital POR trigger threshold is approximately 1.2V and has 100mV of hysteresis. The analog POR trigger threshold is approximately 1.25V and has 100mV of hysteresis. Both POR circuits have lowpass filters that prevent high-frequency supply glitches from triggering the POR. The analog supply (AVDD) and the digital supply (DVDD) pins should be bypassed using 0.1µF capacitors placed as close as possible to the package pin. Maxim Integrated Digital Filter Serial-Digital Interface The MAX11202 communicates through a 2-wire interface, with a clock input and data output. The output rate is predetermined based on the package option (MAX11202A at 120sps and MAX11202B at 13.75sps). 9 MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface 2-Wire Interface The MAX11202 is compatible with the 2-wire interface and uses SCLK and RDY/DOUT for serial communications. In this mode, all controls are implemented by timing the high or low phase of the SCLK. The 2-wire serial interface only allows for data to be read out through the RDY/DOUT output. Supply the serial clock to SCLK to shift the conversion data out. The RDY/DOUT is used to signal data ready, as well as reading the data out when SCLK pulses are applied. RDY/DOUT is high by default. The MAX11202 pulls RDY/ DOUT low when data is available at the end of conversion, and stays low until clock pulses are applied at the SCLK input. On applying the clock pulses at SCLK, the RDY/DOUT outputs the conversion data on every SCLK positive edge. To monitor data availability, pull RDY/ DOUT high after reading the 24 bits of data by supplying a 25th SCLK pulse. The different operational modes using this 2-wire interface are described in the following sections. Data Read Following Every Conversion The MAX11202 indicates conversion data availability, as well as the retrieval of data through the RDY/DOUT output. The RDY/DOUT output idles at the value of the last bit read unless a 25th SCLK pulse is provided, causing RDY/DOUT to idle high. The timing diagram for the data read is shown in Figure 1. Once a low is detected on RDY/DOUT, clock pulses at SCLK clock out the data. Data is shifted out MSB first and is in binary two’s complement format. Once all the data has been shifted out, a 25th SCLK is required to pull the RDY/DOUT output back to the idle high state. See Figure 2. If the data is not read before the next conversion data is updated, the old data is lost, as the new data overwrites the old value. Data Read Followed by Self-Calibration To initiate self-calibration at the end of a data read, provide a 26th SCLK clock pulse. After reading the 24 bits of conversion data, a 25th positive edge on SCLK pulls 10 the RDY/DOUT output back high, indicating the end of the data read. Provide a 26th SCLK clock pulse to initiate a self-calibration routine starting on the falling edge of the SCLK. A subsequent falling edge of RDY/DOUT indicates data availability at the end of calibration. The timing is illustrated in Figure 3. Data Read Followed by Sleep Mode The MAX11202 can be put into sleep mode to save power between conversions. To activate the sleep mode, idle the SCLK high any time after the RDY/DOUT output goes low (that is, after conversion data is available). It is not required to read out all 24 bits before putting the part in sleep mode. Sleep mode is activated after the SCLK is held high (see Figure 4). The RDY/DOUT output is pulled high once the device enters sleep mode. To come out of the sleep mode, pull SCLK low. After the sleep mode is deactivated (when the device wakes up), conversion starts again and RDY/DOUT goes low, indicating the next conversion data is available (see Figure 4). Single-Conversion Mode For operating the MAX11202 in single-conversion mode, activate and deactivate sleep mode between conversions as described in the Data Read Followed by Sleep Mode section). Single-conversion mode reduces power consumption by shutting down the device when idle between conversions. See Figure 4. Single-Conversion Mode with Self-Calibration at Wake-Up The MAX11202 can be put in self-calibration mode immediately after wake-up from sleep mode. Self-calibration at wake-up helps to compensate for temperature or supply changes if the device is shut down for extensive periods. To automatically start self-calibration at the end of sleep mode, all the data bits must be shifted out followed by the 25th SCLK edge to pull RDY/DOUT high. On the 26th SCLK, keep it high for as long as shutdown is desired. Once SCLK is pulled back low, the device automatically performs a self-calibration and, when the data is ready, the RDY/DOUT output goes low. See Figure 5. This also achieves the purpose of single conversions with selfcalibration. Maxim Integrated MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface t1 t5 t2 SCLK 1 2 3 24 t3 t4 RDY/DOUT D22 D23 D0 t6 CONVERSION IS DONE DATA IS AVAILABLE CONVERSION IS DONE DATA IS AVAILABLE t7 Figure 1. Timing Diagram for Data Read After Conversion SCLK 1 2 3 24 25 25TH SLK RISING EDGE PULLS RDY/DOUT HIGH RDY/DOUT D23 D22 D0 CONVERSION IS DONE DATA IS AVAILABLE CONVERSION IS DONE DATA IS AVAILABLE Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK CALIBRATION STARTS ON 26TH SCLK SCLK 2 1 3 24 25 26 1 2 25TH SCLK PULLS RDY/DOUT HIGH RDY/DOUT D23 D22 D0 CONVERSION IS DONE DATA IS AVAILABLE D23 D22 CONVERSION IS DONE DATA IS AVAILABLE AFTER CALIBRATION t8 Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration Maxim Integrated 11 MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface DEVICE ENTERS SLEEP MODE SCLK 1 2 3 DEVICE EXITS OUT SLEEP MODE 1 24 2 SLEEP MODE t9 t10 RDY/DOUT D22 D23 D0 D23 CONVERSION IS DONE DATA IS AVAILABLE D22 CONVERSION IS DONE DATA IS AVAILABLE t11 Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single Conversion Timing 25TH SCLK PULLS RDY/DOUT HIGH SCLK 1 2 3 DEVICE ENTERS SLEEP MODE 24 25 DEVICE EXITS OUT SLEEP MODE AND STARTS CALIBRATION 1 26 2 SLEEP MODE t10 RDY/DOUT D23 D22 D0 CONVERSION IS DONE DATA IS AVAILABLE D23 D22 CONVERSION IS DONE DATA IS AVAILABLE AFTER CALIBRATION t12 Figure 5. Timing Diagram for Sleep Mode Activation Followed by Self-Calibration at Wake-Up 12 Maxim Integrated MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface Chip Information Applications Information See Figure 6 for the RTD temperature measurement circuit and Figure 7 for a resistive bridge measurement circuit. PROCESS: BiCMOS Package Information IREF1 = K x IREF2 IREF2 REFP MAX11202 RREF IREF1 REFN AINP For the latest package outline information and land patterns, go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 µMAX U10+2 21-0061 RRTD AINN GND Figure 6. RTD Temperature Measurement Circuit AVDD REFP REFN MAX11202 AINP AINN Figure 7. Resistive Bridge Measurement Circuit Maxim Integrated 13 MAX11202 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface Revision History REVISION NUMBER REVISION DATE 0 4/10 DESCRIPTION Initial release PAGES CHANGED — Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 14 © 2010 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.