Si85xx Si85 X X U N I D I R E C T I O N A L AC C U R R E N T S E N S O R S Features VDD2 R1 IIN R2 GND2 Si850x GND3 OUT IOUT NC MODE Applications Power supplies Motor controls Lighting equipment Industrial equipment 1 R1 Description VDD1 12-Pin QFN 1 Pin Assignments: See page 20 TRST FAULT output helps safeguard operation 1,000 VDC isolation Accurate to ±5% of measurement Large 2 VPP output pins signal at full scale High-side or low-side current sensing –40 to 125 ºC operating range (Si85x4/5/6) Small 4 x 4 x 1 mm package Low cost GND1 Single-chip ac current sensor/conditioner Low loss: Less than 1.3 mΩ primary series resistance; less than 2 nH primary inductance at 25 ºC Leading-edge noise suppression eliminates need for leading-edge blanking "Ping-Pong" output version allows one Si85xx to replace two current transformers in full-bridge applications 5, 10, and 20 A full-scale versions VDD IIN R2 R3 Si851x R4 OUT1 IOUT GND OUT2 TRST/FAULT The Si85xx products are unidirectional ac current sensors available in fullscale ranges of 5, 10, and 20 A. Si85xx products are ideal upgrades for older current-sensing technologies offering size, performance and cost advantages over current transformers, Hall effect devices, DCR circuits and other approaches. The Si85xx are extremely low loss, adding less than 1.3 mΩ of series resistance and less than 2 nH series inductance in the sensing path at 25 ºC. Current-sensing terminals are isolated from the other package pins to a maximum voltage of 1,000 VDC. Functional Block Diagram Patents pending R1 IIN R2 R3 R4 Si851x RESET LOGIC MODE LOGIC VDD VIN MODE VDD1 TRST IIN R2 GND1 Si850x OUT OUT1 METAL SLUG INTEGRATOR SIGNAL CONDITIONING R1 OUT2 PH1 IOUT GND2 Q1 L VOUT C PH2 TEMP SENSOR Q2 AUTO CALIBRATION LOGIC ADC Typical Application IOUT GND VDD Preliminary Rev. 0.1 7/07 TRST/FAULT Copyright © 2007 by Silicon Laboratories Si85xx This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA). Si85xx 2 Preliminary Rev. 0.1 Si85xx TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. Device Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.3. Integrator Reset and Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.4. Effect of Operating Frequency on Output Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. Effect of Temperature on Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.6. Leading Edge Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.7. FAULT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1. Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.2. Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.3. Single-Phase Buck Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4. Full-Bridge Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5. Push-Pull Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4. Pin Descriptions—Si85xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. Package Outline—12-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Preliminary Rev. 0.1 3 Si85xx 1. Electrical Specifications Table 1. Electrical Specifications TA = –40 to +85 ºC (typical specified at 25 ºC), VDD = 2.7 to 5.5 V Parameter Conditions Min Typ Max Unit 2.7 — 5.5 V — 4 7 mA Undervoltage Lockout (VUVLO) 2.1 2.3 2.5 V Undervoltage Lockout Hysteresis (VHYST) — 100 — mV 2.0 — — V — — 0.8 V 250 — — ns R1, R2, R3, R4 Input Rise Time (tRR) — — 30 ns R1, R2, R3, R4 Input Fall Time (tFR) — — 30 ns Measurement Watchdog Timeout (tWD) 30 50 80 µs Supply Voltage (VDD) Supply Current Logic Input HIGH Level Logic Input LOW Level Fully enabled, input frequency = 1 MHz MODE, R1, R2, R3, R4 inputs (TTL compatible) Reset Time (tR) Series Input Resistance Measured from IIN to IOUT — 1.3 — mΩ Series Inductance Measured from IIN to IOUT — 2 — nH Input/Output Delay OUT, OUT1, OUT2 delay relative to input — 50 100 ns Start-Up Self-Cal Delay (tCAL) Time from VDD = VUVLO + VHYST to cal complete — 150 200 µs Input Common Mode Voltage Range — — 1,000 V Operating Input Frequency Range (f) 50 — 1,200 kHz DC Power Supply Rejection Ratio — 80 — db Si85x1/4/7 — 400 — mV/A Si85x2/5/8 — 200 — mV/A Si85x3/6/9 — 100 — mV/A Current flow from IIN to IOUT = 0 — 10 — mV OUT, OUT1, OUT2 load = 5K || 50 pF — 50 — V/µs 30 Ω Sensitivity OUT, OUT1, OUT2 Offset Voltage (VOUTMIN) VOUT Slew Rate OUT, OUT1, OUT2 Output Resistance Measurement Error (%)—all devices (–40 to 85 ºC Temp Range) 4 20 5 to 10% of full scale –20 — +20 % 10 to 20% of full scale –10 — +10 % 20 to 100% of full scale –5 — +5 % Preliminary Rev. 0.1 Si85xx Table 1. Electrical Specifications (Continued) TA = –40 to +85 ºC (typical specified at 25 ºC), VDD = 2.7 to 5.5 V Parameter Measurement Error (%)—all devices (–40 to 125 ºC Temp Range) Conditions Min Typ Max Unit 5 to 10% of full scale –30 — +30 % 10 to 20% of full scale –25 — +25 % 20 to 100% of full scale –20 — +20 % Table 2. Absolute Maximum Ratings Parameter Storage temperature Ambient temperature under bias Symbol Min TSTG TA Supply voltage VDD Voltage on any pin with respect to ground (not including IIN, IOUT) VIN Max Units –65 +150 ºC –40 +125 ºC 5.75 V VDD + 0.5 V –0.5 Typ Lead solder temperature (10 sec.) - 260 ºC DC isolation - 1000 VDC Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Preliminary Rev. 0.1 5 Si85xx 2. Functional Overview The Si85xx AC Current Sensor family of products mimic the functionality of a traditional current transformer (CT) circuit with burden resistor, diode and output filter, but offers enhanced performance and added capabilities. These devices use inductive current sensing and onboard signal conditioning electronics to generate a 2 V full-scale output signal proportional to the ac current flowing from the IIN to the IOUT terminals. As shown in Figure 1 and Figure 2, current flowing through the metal package slug induces a signal in the pickup coil onboard the Si85xx die. This signal is applied to the input of an integrator that re-constructs the ac current flowing from IIN to IOUT. On-board circuitry provides cycle-bycycle integrator reset, and temperature and offset voltage compensation to achieve measurement accuracy to within ±5%. R1 IIN R1 RESET LOGIC METAL SLUG INTEGRATOR VDD2 METAL SLUG SIGNAL CONDITIONING GND2 GND1 AUTO CALIBRATION LOGIC VDD1 GND3 NC TRST Figure 1. Si850x (Single Output) Block Diagram 6 SIGNAL CONDITIONING OUT2 AUTO CALIBRATION LOGIC ADC GND VDD TRST/FAULT The Si85xx is superior to other current sensing approaches and benefits the system in a number of ways: OUT PICKUP COIL IOUT MODE PICKUP COIL TEMP SENSOR ADC MODE LOGIC OUT1 R2 RESET LOGIC TEMP SENSOR R4 Figure 2. Si851x (Ping Pong Output) Block Diagram Si850x INTEGRATOR R3 Si851x IOUT IIN R2 Small size: With its 4x4 mm footprint and 1 mm height, the Si85xx is among the smallest current sensors available. Large output signal: The 2.0 V full-scale output swing offers superior noise immunity versus other current sensing technologies. Low loss: The Si85xx adds only 1.3 mΩ (at 25 °C) to the sensing path making it one of the lowest loss current sensors available. Low 2 nH primary series inductance is 2,000 times lower compared to a CT, and results in significantly less ringing. High precision: The Si8501/2/3 versions are available with a max error of ±5% of reading; one of the highest accuracy current sensors available. Ping-Pong output mode (Si851x): Alternately routes the current measurements from each side of a full-bridge circuit to separate output pins for comparison, which is very useful for transformer flux balancing applications. Eliminates a second CT in a full-bridge application. Leading edge noise suppression: Filters out reflected noise due to long reverse recovery time of output rectifier. Eliminates the need for external leading edge blanking circuit. High common mode voltage: The Si85xx offers up to 1,000 VDC of isolation making it useful over a very wide voltage range. Preliminary Rev. 0.1 Si85xx FAULT output (Si8517/8/9): goes low when external reset timing is in error. Ease-of-use: Other than conventional power and grounding techniques, no special board layout considerations are required. Built-in timing interface circuits allow already available system switching signals to be used for reset—no external circuits required. 2.3. Integrator Reset and Current Measurement 2.1. Under Voltage Lockout (UVLO) To achieve specified accuracy, the integrator capacitor must be discharged (reset) for time period tR prior to the start of every measurement cycle. This cycle-by-cycle reset is implemented by connecting existing system gate control signals to the R1–R4 inputs in a way that resets the integrator when no current is flowing from IIN to IOUT. To achieve rated accuracy, the reset cycle must be completed prior to the start of the measurement cycle. For maximum flexibility, integrator reset operation can be configured in one of two ways: The Si85xx measures current flowing from the IIN to IOUT terminals. Current is allowed to flow in the opposite direction, but will not be measured (OUT1 and OUT 2 remain at their minimum values during reverse current flow. Reverse current flow will not damage the Si85xx). UVLO is provided to prevent erroneous operation during device start-up and shutdown, or when VDD is significantly below specified operating range. The Si85xx is in UVLO state when VDD < VUVLO (Figure 3). During UVLO, the output(s) are held at minimum value regardless of the amount of current flowing from IIN to IOUT and signals on integrator reset inputs R1-R4 are ignored. The Si85xx exits UVLO when VDD > (VUVLO + VHYST). 2.2. Device Start-Up Upon exit from UVLO, the Si85xx performs a voltage offset and temperature self-calibration cycle. During this time, output(s) are held at minimum value and reset inputs (R1-R4) are ignored. The reset inputs are enabled at the end of the self-calibration cycle, and an integrator reset cycle is initiated on the first occurrence of active signals on R1-R4. A current measurement is initiated immediately after the completion of the integrator reset cycle, and the resulting current waveforms appear on the output pins. This "resetmeasure-reset" pattern repeats throughout steady-state operation. Option 1: The start and duration of reset is determined by the states of the timing signals applied to R1-R4. Option 2: The timing signals applied to R1-R4 trigger the start of reset, and the duration of the reset is determined by an on-board programmable reset timer. VUVLO + VHYST VDD SUPPLY First Positive Edge Following End of Self-Cal INTEGRATOR RESET Si85xx STATUS DON’T CARE UNDER VOLTAGE LOCKOUT STATE tRP START-UP SELF-CAL CYCLE RESET tCAL Si85xx OUTPUT tRP MEASURE CURRENT RESET tR tR VOUTMIN OUT1, OUT2 VALID Figure 3. Si85xx Startup and Control Timing Preliminary Rev. 0.1 7 Si85xx Reset option 2 is selected by connecting a timing resistor (RTRST in Figure 4) from the TRST input to ground. It is typically used in applications where the gate drivers are on-board the controller. In this mode, the on-chip reset timer is triggered when the signals on R1-R4 satisfy the logic equations of Tables 3 and 4. Once triggered, the timer maintains integrator in reset for time duration tR as programmed by the value of resistor RTRST. The user must select the value of resistor RTRST to terminate the reset cycle prior to the start of measurement under worst-case timing conditions. Note that values of tR below the specified value in Section “1. Electrical Specifications” results in increased integrator output offset error and increased output noise on VOUT. Moreover, tR’s time is summarized by the following equation: tR = 10 ns/kΩ where values of RTRST that produce a reset time less than 200 ns (RTRST < 20 kΩ) should not be used. Si85xx TRST RTRST 2.4. Effect of Operating Frequency on Output Accuracy The Si85xx includes a built-in watchdog timer that disables measurement and holds OUT or OUT1 and OUT2 at their minimum values when the timer’s preset limit is exceeded. This timer limits the operation of the Si85xx in dc measurement applications. As Figure 5 illustrates, the Si85xx operates down to about 10 kHz with the nominal measurement error doubling to about 10 percent. 15% % Typical Error Integrator reset option 1 is selected by connecting TRST to VDD. In this mode, the Si85xx is held in reset as long as the signals on R1-R4 satisfy the logic equations of Tables 3 and 4. It is typically used in applications where the gate drivers are external to the system controller I.C. (the gate driver delay ensures reset is completed prior to the start of measurement). 12% 9% 6% 3% 0% 10 20 30 40 50 Frequency (kHz) Figure 5. Full-Scale Error vs. Frequency 2.5. Effect of Temperature on Accuracy Offset voltage present at the Si85xx output terminals (output offset voltage) is calibrated out each time VDD is applied to the Si85xx; so, its error contribution is minimized when the temperature at which calibration occurred is at or near the steady-state operating temperature of the Si85xx. For example, applying VDD at 25 °C (offset cal is performed) and operating at 85 °C will result in a larger offset error than operating at 50 ºC. The effect of this error is summarized in Figure 6. The chart is referenced to 25 °C. If the Si85xx is powered up at 25 °C and then operated at 125 °C with no autocalibration performed (i.e., the power is not cycled at 125 °C, which causes an auto-calibration), a 3 percent measurement error can be expected. 1.0% Figure 4. Programming Reset Time (tR) % Typical Error 0.5% 0.0% -0.5% -1.0% -1.5% -2.0% -2.5% -3.0% -3.5% 0 25 50 75 100 Temperature (Celcius) Figure 6. Differential Temperature Calibration Error 8 Preliminary Rev. 0.1 125 Si85xx Typical Series Resistance (mOhm) Figure 7 shows the Si85xx thermal characteristics over the temperature range of –40 to +125 ºC. Series inductance is constant at 2 nH (max) across this same temperature range. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 2.6. Leading Edge Noise Suppression High-amplitude spikes on the leading edge of the primary switching waveforms can cause the PWM latch to be erroneously reset at the start of the switching cycle when operating in current mode control. To prevent this problem, leading edge blanking is commonly used to disable the current comparator during the early portion of the primary-side switching cycle. The Si85xx eliminates leading-edge noise spikes by including them in the signal integration. As shown in the output waveform of Figure 8, noise present in the input waveform is eliminated without the use of blanking. 0.4 0.2 0 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 7. Series Resistance Thermal Characteristics Current Sense Transformer Si8502 Figure 8. Leading-Edge Noise Suppression Waveforms (200 kHz, 9.3A Load) (Si8502 waveform measured directly on OUT pin with no external filter) Preliminary Rev. 0.1 9 Si85xx 2.7. FAULT Output The FAULT output (Si8517/8/9) guards against Si85xx output signal errors caused by missing reset cycles. FAULT is asserted when a measurement cycle exceeds the internal watchdog timer times limit of tWD. FAULT can be used to alert a local microcontroller or digital power controller of a current sense failure, or initiate a system shutdown. To detect faults, tie a 200 kΩ resistor from TRST/FAULT to VDD. 2-wire Ping-Pong mode is useful mainly in nonoverlapping two-phase buck converters, but may also be used in full-bridge applications. In this output mode, reset inputs R1 and R2 are used, and input R3 is grounded. Measured current appears on OUT1 when R2 is high, and appears on OUT2 when R1 is high as shown in the full-bridge timing example of Figure 9. R1 3. Application Information R2 3.1. Board Layout The Si85xx is connected in the series path of the current to be measured. The Si85xx must be located as far away from away from transformer and other magnetic field sources as possible. Like other analog components, the Si85xx should be powered from a lownoise DC source, and preferably connected to a low noise analog ground plane. Recommended bypass capacitors are 1 µF in parallel with a 0.1 µF, positioned as close to the Si85xx as possible. When using the Si850x (single output versions), all 3 ground pins MUST be connected to the same ground point, and both VDD and VDD2 pins MUST be tied to VDD. 3.2. Device Configuration Configuring the Si85xx involves the following steps: 1. Selecting an output mode 2. Configuring integrator reset timing 3. Setting integrator reset time tR 3.2.1. Device Selection The Si85xx family offers three output modes: Single output (Si850x), and 2 and 4-Wire Ping Pong (Si851x). The Si851x products can be configured to operate in all three of these output modes. Si85xx State RESET tR MEASURE RESET tR OUT1 OUT2 TIME Figure 9. Full-Bridge Timing Example A 4-Wire Ping-Pong mode is recommended for full-bridge applications over 2-wire because it uses all four inputs making the reset function tolerant to single-point signal failures. In 4-Wire Ping-Pong mode, current appears on OUT2 when R1 is high and R2 is low; and appears on OUT1 when R3 is high and R4 is low as shown in the full-bridge timing example of Figure 10. Table 3 shows the states of the Mode and R4 inputs that select each output, and the resulting reset logic functions and truth tables. The Si850x products operate ONLY in Single output mode. Most half-wave and single-phase applications require only Single output mode, and will typically use the Si850x. In Single output mode, output current always appears on the OUT pin (Si850x) or the OUT1 pin (Si851x). A single integrator reset signal is typically sufficient when operating in this mode. Ping-Pong mode routes the current waveform to two different output pins on alternate measurement cycles. It is useful in full-wave and push-pull topologies where external circuitry can be used to monitor and/or control transformer flux balance. (Note: The Applications section of this data sheet (Section 3) shows design examples using both output modes in various power topologies.) 10 MEASURE Preliminary Rev. 0.1 Si85xx 3.2.2. Selecting Reset Timing Signals Reset timing signals should be chosen to meet the following conditions: R1 Satisfy reset time tR Not overlap integrator reset into the desired measurement period Not violate reset watchdog timeout period tWD R2 3.2.3. Configuring Integrator Reset R3 R4 MEASURE RESET tR MEASURE RESET tR OUT1 Per Section “2. Functional Overview”, the integrator must be reset (zeroed) prior to the start of each measurement cycle to achieve specified measurement accuracy. This reset must be synchronized with the system switch timing signals to ensure current is measured during the appropriate time, so the Si85xx integrator reset circuitry uses system timing as its reference. Timing signals connect to reset inputs R1 through R4 where built-in logic functions allow the user to choose the conditions that cause an integrator reset event. Important note: reset inputs R1–R4 are rated to a maximum input voltage of VDD. External resistor dividers must be used when connecting driver output signals to R1–R4 that swing beyond VDD. OUT2 Figure 10. Full-Bridge Timing Example B Preliminary Rev. 0.1 11 Si85xx Table 3. Si850x Reset Mode Summary Output Mode R2 R1 Reset State* Logic Expression Single-Ended 0 0 0 RESET = XOR [R1, R2] 0 1 1 1 0 1 1 1 0 *Note: Device is in reset when Reset State = 1. Table 4. Si851x Output and Reset Mode Summary Part # Output Mode Si850x Single-Ended MODE Input R4 — — R3 R2 R1 Reset State* Logic Expression — 0 0 0 RESET = XOR [R1, R2] 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 *Note: Device is in reset when Reset State = 1. 12 Preliminary Rev. 0.1 Si85xx Table 4. Si851x Output and Reset Mode Summary (Continued) Part # Output Mode Si851x Single-Ended MODE Input R4 1 0 R3 R2 R1 Reset State* Logic Expression 0 0 0 0 RESET = XOR [R1, R2] 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 1 1 0 1 2-Wire Ping Pong 1 1 0 0 1 4-Wire Ping Pong 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 RESET = XNOR [R1, R2] RESET = [R1 & R2] | [R3 & R4] *Note: Device is in reset when Reset State = 1. As shown in Table 3, the Si850x integrator reset logic is a simple XOR gate where reset is maintained (or triggered, depending on use of the TRST input) when states of reset inputs R1 and R2 are not equal. Figure 11 shows the logic for the Si851x products, where any one of three reset logic functions can cause integrator reset. The output mode (Si851x) is determined by the states of the Mode and R4 inputs, as shown in Table 4. As explained in Section 2.3, the signals applied to R1-R4 can control integrator reset in real time (option 1), or can trigger a reset event of programmable duration (option 2). Referring to Figure 11, reset timing is exclusively a function of the signals applied to R1-R4 when TRST is tied to VDD. If not connected to VDD, the reset timer is enabled and TRST MUST be connected through a resistor to ground to set the reset duration (tR). Note the reset timer is retriggerable, and generates a timed integrator discharge pulse whenever the reset logic output transitions from low to high. Preliminary Rev. 0.1 13 Si85xx MODE = 1 R4 = 0 TRST = VDD TRST = R1 to GND Reset timing determined only by inputs R1–R4. Reset triggered by inputs R1–R4. Reset time (tR) set by value of resistor RTRST. Output 1 R1 R2 MODE = 1 R4 = 1 R3 Output 2 RESET TIMER TRST PGM CLK R4 OUT 1 0 + VREF MODE = 0 Output 3 SYSTEM CONTROLLER Logic level gate control signals (to Rn inputs) INTEGRATOR External Driver Internal Driver Required if driver output voltage > VDD Logic level gate control signals (to Rn inputs) Figure 11. Si851x Integrator Reset Logic 14 Preliminary Rev. 0.1 Si85xx 3.2.4. Setting Reset Time tR The programmable reset timer is triggered when the states of the signals applied to R1–R4 cause the associated logic expression (Tables 3 and 4) to go high (transition to the TRUE state). Because this timer is re-triggerable, R1– R4 must remain TRUE for the duration of the desired tR as shown in Figure 12. Should R1–R4 transition FALSE during tR, integrator reset will be immediately halted resulting in lower measurement accuracy due to higher integrator offset error. CURRENT R1–R4 TRUE for programmed tR (minimum) TRUE R1–R4 STATE FALSE Programmed value of tR Si85xx STATUS 0 ns (min) RESET MEASURE Si85xx OUTPUT Figure 12. Correct tR Programming Using Resistor from TRST Input to Ground Preliminary Rev. 0.1 15 Si85xx 3.2.5. Measurement Watchdog Timer and FAULT Output A built-in watchdog timer disables measurement and holds OUT or OUT1 and OUT2 at their minimum values when the time between integrator resets exceeds tWD. The output signal from this watchdog is available on the FAULT output pin (Si8517/8/9 only). t1 System Timing Phase t2 Reset Trigger Measurement Period tWD Output Measurement Period tWD tWD tR tR FAULT Figure 13. Measurement Watchdog Timer Operation As shown in Figure 13, the time between integrator resets for system timing phase t1 is greater than watchdog period tWD. As a result, measurement occurs until tWD is exceeded, at which time the output is immediately forced to minimum value and FAULT transitions low. Further measurements are inhibited until the application of another integrator reset, which also resets the watchdog driving FAULT high, and enables another measurement cycle. This process continues until tWD is no longer violated, as shown in period t2 where normal operation is restored. The current measurements made in period t1 will have reduced accuracy versus those made within the specified operating frequency range. 16 Preliminary Rev. 0.1 Si85xx 3.3. Single-Phase Buck Converter Example In this example, the Si850x is configured to operate in a single-phase synchronous buck converter (Figure 14). This converter has a PWM frequency of 1 MHz, and a maximum duty cycle of 80%. VDD VIN C2 1 µF C1 0.1 µF VDD1 VDD2 GND1 IIN GND2 R2 RTRST TRST R1 Si850x IOUT GND3 2 Vpp OUT Q1 PH1 L1 VOUT PH2 Current PWM I=0 I>0 RESET MEASURE C3 Q2 PH2 Si850x State 100 ns Figure 14. Si850x Single-Phase Buck Converter This is an example of a half-wave application that can be addressed with Single-Ended output mode. The PWM period is calculated to be 1/10–6 = 1.0 µs, and the worst-case value tR is 0.2 x 1.0 x 10–6 = 200 ns at 80% maximum duty cycle (RTRST = 20 kΩ). In this example, the current measurement is made when the buck switch is on, so PH2 is chosen as the reset signal by connecting PH2 to R1 and grounding the R2 and R3. The PH2 signal can be obtained at the input of the driver external to the PWM controller, or the output of the controller's internal driver (through a resistor divider if the driver output swings beyond the device VDD range). Preliminary Rev. 0.1 17 Si85xx 3.4. Full-Bridge Converter Example The full-bridge circuit of Figure 15 uses an Si851x configured in 4-Wire Ping-Pong output mode. The switching frequency of this phase-shifted full-bridge is 150 kHz, and the maximum control phase overlap is 70%. VIN VDD IIN VDD MODE C1 0.1 µF C2 1 µF GND OUT1 OUT1 OUT2 OUT2 Si851x PH1 VDD PH2 TRST R1 R2 R3 R4 IOUT PH3 PH4 Q1 1–4 Switches Turned ON PH1 Q2 PH2 Si85xx State MEASURE 1–2 RESET 2–3 3–4 MEASURE RESET TI OUT1 PH3 PH4 Q3 Q4 OUT2 Figure 15. Full-Bridge Converter Given the 150 kHz switching frequency (duty cycle fixed at 50%), the equivalent period is 1/150 x 103 = 6.6 µs. At 70% maximum overlap, this equates to a worst-case tR value of is 0.3 x 6.6 x 10–6 = 1.98 µs; the default value for tR can therefore be used, and is selected by connecting TRST to VDD. As shown in the timing diagram of Figure 15, integrator reset occurs when current circulates between Q1 and Q2, and between Q3 and Q4 (i.e. when current is not being sourced from VIN). The external driver delay ensures reset is complete prior to the start of measurement. 18 Preliminary Rev. 0.1 Si85xx 3.5. Push-Pull Converter Example The Push-Pull converter of Figure 16 uses 2-Wire Ping Pong output mode. As shown in the timing diagram, the integrator reset occurs when the inputs of both the PH1 and PH2 drivers are low. As shown, TRST is connected to VDD, selecting the default value of tR (250 ns). Assuming an 80% maximum duty cycle, this value of tR would deliver specified accuracy over a PWM frequency range of 50 to 400 kHz. Frequencies above 400 kHz would require the selection of a lower tR value by connecting a resistor from TRST to ground. VDD VIN C1 0.1 µF C2 1 µF VDD MODE IIN OUT1 R4 TRST Si851x OUT2 IOUT GND R3 R2 R1 Q1 PH2 PH1 PH2 T1 Si85xx Status MEASURE RESET MEASURE RESET MEASURE OUT1 Q2 PH1 OUT2 Figure 16. Push-Pull Example Using Default tR Value Preliminary Rev. 0.1 19 Si85xx 4. Pin Descriptions—Si85xx VDD MODE R1 IIN 1 1 R1 VDD1 VDD2 12-Pin QFN IIN R2 R2 GND2 R3 Si850x GND3 Si851x R4 OUT OUT1 IOUT IOUT TRST/FAULT GND OUT2 GND1 TRST NC Figure 17. Example Pin Configurations Table 5. Si85xx Family Pin Descriptions 20 Pin# Si850x Pin Name Description Si851x Pin Name Description 1 R1 Integrator reset input 1 R1 Integrator reset input 1 2 R2 Integrator reset input 2 R2 Integrator reset input 2 3 GND2 Ground R3 Integrator reset input 3 4 GND3 R4 Integrator reset input 4 5 OUT 6 NC 7 Output OUT1 Output in single-ended output mode, or one of two outputs in Ping-Pong mode. No connect OUT2 Second of two Ping-Pong mode outputs TRST Reset time control TRST Reset time control 8 GND1 Ground GND Ground 9 IOUT Current output terminal IOUT Current output terminal 10 IIN 11 VDD1 12 VDD2 Current input terminal Power supply input IIN Current input terminal VDD Power supply input MODE Mode control input Preliminary Rev. 0.1 Si85xx 5. Ordering Guide P/N Full Scale Current (A) Si8501-B-GM 5 Si8502-B-GM 10 Si8503-B-GM 20 Si8504-B-IM 5 Si8505-B-IM 10 Si8506-B-IM 20 Si8511-B-GM 5 Si8512-B-GM 10 Si8513-B-GM 20 Si8514-B-IM 5 Si8515-B-IM 10 Si8516-B-IM 20 Si8517-B-GM 5 Si8518-B-GM 10 Si8519-B-GM 20 Full Scale Temp Range Error (°C) (% of Reading) Pin 7 Function Output Mode Package Single 4x4 mm QFN ±5 –40 to +85 Integrator Reset Time Programming Input ±20 –40 to +125 Integrator Reset Time Programming Input ±5 –40 to +85 Integrator Reset Time Programming Input ±20 –40 to +125 Integrator Reset Time Programming Input ±5 –40 to +85 FAULT Output Ping-Pong Note: All packages are Pb-free and RoHS compliant. Moisture Sensitivity level is MSL2 with peak reflow temperature of 260 ºC according to the JEDEC industry classification, and peak solder temperature. Preliminary Rev. 0.1 21 Si85xx 6. Package Outline—12-Pin QFN Figure 18 illustrates the package details for the Si85xx. Table 6 lists the values for the dimensions shown in the illustration. Figure 18. 12-Pin QFN Package Diagram Table 6. QFN-12 Package Diagram Dimensions 22 Dimension MIN NOM MAX A b c D e E f g k L L1 L2 aaa bbb ccc ddd eee 0.80 0.25 0.85 0.85 0.30 0.90 4.00 BSC. 0.50 BSC. 4.00 BSC. 2.45 BSC. 1.30 BSC. 0.75 BSC. 0.40 0.05 0.50 — — — — — 0.90 0.35 0.95 0.35 0.03 0.45 — — — — — Preliminary Rev. 0.1 0.45 0.08 0.55 0.05 0.05 0.08 0.05 0.05 Si85xx NOTES: Preliminary Rev. 0.1 23 Si85xx CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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