MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages General Description The MAX9679 provides multiple programmable reference voltages for gamma correction in TFT LCDs and a programmable reference voltage for VCOM adjustment. All gamma and VCOM reference voltages have a 10-bit digital-to-analog converter (DAC) and highcurrent buffer, which reduces the recovery time of the output voltages when critical levels and patterns are displayed. A programmable internal reference sets the full-scale voltage of the DACs. Two independent sets of gamma curves and VCOM codes can be stored in the IC's volatile memory; BKSEL signal selects between the two sets. The IC has multiple-time programmable (MTP) memory to store gamma and VCOM codes on the chip, eliminating the need for external EEPROM. Features S 12 Channels of Programmable Gamma Voltages with 10-Bit Resolution S Programmable VCOM Voltage with 10-Bit Resolution S Programmable Reference for DACs S Multiple-Time Programmable Memory to Store Gamma and VCOM Codes S Switching Between Two Gamma Curves and VCOM Voltages S AVDD1, AVDD2, and AVDD_AMP Supplies to Reduce Heat S I2C Interface (1MHz Fast-Mode Plus) Ordering Information Applications TFT LCDs PART MAX9679ETG+ TEMP RANGE PIN-PACKAGE -40NC to +85NC 24 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Simplified Block Diagram BKSEL MTP REG I2C REG DAC REG PROG REF PROG REF PROG REF GAMMA BANK 1 GAMMA BANK 1 GAMMA BANK 1 VCOM1 GAMMA BANK 2 GAMMA BANK 2 VCOM1 VCOM1 VCOM2 I2C VCOM2 MAX9679 PROG REF 2:1 MUX 12 DACs 12 GAMMA BUFFERS 2:1 MUX DAC VCOM AMPLIFIER 12 GAMMA OUTPUTS VCOM OUTPUT CONTROL For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-5756; Rev 2; 5/13 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Functional Diagram BKSEL AVDD1 PROG REF PROG REF 10 PROG REF PROG REF VPREF 10 10 10 GAMMA BANK 1 GAMMA BANK 1 GAMMA BANK 1 10 10 10 MTP MEMORY I2C REG DAC REG GMA3 DAC GMA4 DAC GMA5 DAC GMA6 DAC AGND 10 10 GAMMA BANK 2 GMA2 DAC 2:1 MUX 10 GAMMA BANK 2 GMA1 DAC 10 10 10 GMA7 DAC GMA8 DAC GMA9 DAC GMA10 DAC GMA11 DAC GMA12 DAC AGND VCOM1 VCOM1 VCOM1 VCOM2 VCOM2 2:1 MUX 10 AVDD2 AVDD_AMP DAC VCOM VCOM_FB DVDD SDA SCL A0 2 AGND I2C INTERFACE MAX9679 12 GAMMA, 1 VCOM Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Typical Application Circuit 12V PMIC BKSEL AVDD1 PROG REF PROG REF 10 PROG REF PROG REF VPREF 10 10 10 GAMMA BANK 1 GAMMA BANK 1 GAMMA BANK 1 10 10 10 MTP MEMORY I2C REG 10 10 GAMMA BANK 2 GAMMA BANK 2 GMA3 DAC GMA4 DAC 10 10 10 GMA6 DAC VCOM1 VCOM1 VCOM2 VCOM2 2:1 MUX 10 AVDD2 SERVICE DRIVER CHIP HVDD GMA7 DAC GMA8 DAC GMA9 DAC GMA10 DAC GMA11 DAC GMA12 DAC AGND VCOM1 SOURCE DRIVER CHIP GMA5 DAC AGND 10 TO LCD PANEL GMA2 DAC 2:1 MUX I2C REG GMA1 DAC AVDD_AMP HVDD DAC VCOM TO LCD PANEL VCOM_FB DVDD TCON SDA SCL A0 Maxim Integrated AGND I2C INTERFACE MAX9679 12 GAMMA, 1 VCOM 3 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages ABSOLUTE MAXIMUM RATINGS (All voltages are with respect to AGND.) Supply Voltages AVDD1, AVDD2, AVDD_AMP.............................-0.3V to +22V DVDD....................................................................-0.3V to +4V Outputs GMA1–GMA6....................................-0.3V to (VAVDD1 + 0.3V) GMA7–GMA12..................................-0.3V to (VAVDD2 + 0.3V) VCOM........................................ -0.3V to (VAVDD_AMP + 0.3V) Inputs SDA, SCL, A0, BKSEL..........................................-0.3V to +6V VCOM_FB.................................. -0.3V to (VAVDD_AMP + 0.3V) Continuous Current SDA, SCL...................................................................... Q20mA GMA1–GMA8.............................................................. Q200mA VCOM......................................................................... Q600mA Continuous Power Dissipation (TA = +70NC) TQFN Multilayer Board (derate 25.6mW/NC above +70NC)..........................2051.3mW Junction Temperature......................................................+125NC Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (qJA)...........39°C/W Junction-to-Case Thermal Resistance (qJC)..................6°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VAVDD1 = 18V, VAVDD2 = VAVDD_AMP = 9V, VDVDD = 3.3V, VAGND = 0V, VCOM = VCOM_FB, programmable reference code = 905, no load, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SUPPLIES AVDD1 Analog Supply Voltage Range VAVDD1 Guaranteed by PSRR 9 20 V AVDD2 Analog Supply Voltage Range VAVDD2 Guaranteed by PSRR 6 20 V VAVDD_AMP Guaranteed by PSRR 9 20 V 2.7 3.6 V AVDD_AMP Analog Supply Voltage Range Digital Supply Voltage VDVDD DVDD ramp-up time from 1.5V to 2.3V to ensure correct MTP loading Slowest DVDD Ramp-Up Time 20 25 ms AVDD1 Analog Quiescent Current IAVDD1 7 11 mA AVDD2 Quiescent Current IAVDD2 6 9 mA AVDD_AMP Quiescent Current Digital Quiescent Current IAVDD_AMP IDVDD No SCL or SDA transitions Thermal Shutdown Thermal-Shutdown Hysteresis Undervoltage-Lockout Threshold Analog Supply Voltage Range for Programming MTP 4 UVLO DVDD undervoltage-lockout threshold 2.1 15 5 8 mA 1.5 3 mA +160 NC 15 NC 2.3 2.6 V 20 V Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages ELECTRICAL CHARACTERISTICS (continued) (VAVDD1 = 18V, VAVDD2 = VAVDD_AMP = 9V, VDVDD = 3.3V, VAGND = 0V, VCOM = VCOM_FB, programmable reference code = 905, no load, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 19.96 19.98 20.00 V PROGRAMMABLE REFERENCE (VPREF) Full-Scale Voltage Referred to output, TA = +25NC Resolution 10 Bits Integral Nonlinearity Error TA = +25NC, 336 P reference code P 1007 0.5 1 LSB Differential Nonlinearity Error TA = +25NC, 336 P reference code P 1007 0.5 1 LSB DAC Resolution 10 Bits Integral Nonlinearity Error TA = +25NC, 16 P code P 1008 for gamma, 256 P code P 1008 for VCOM 0.5 1 LSB Differential Nonlinearity Error TA = +25NC, 16 P code P 1008 for gamma, 256 P code P 1008 for VCOM 0.5 1 LSB 200 mA GAMMA Short-Circuit Current Output connected to either supply rail Total Output Error TA = +25NC, code = 768 for GMA1–GMA6 and code = 256 for GMA7– GMA12 Load Regulation -5mA P ILOAD P +5mA, code = 768 for GMA1–GMA6 and code = 256 for GMA7–GMA12 Low Output Voltage Sinking 4mA, referred to lower supply rail High Output Voltage Sourcing 4mA, referred to upper supply rail GMA1–GMA6, code = 768, VAVDD1 = 9V to 20V; GMA7–GMA12, code = 256, VAVDD2 = 5V to 20V 60 GMA1–GMA6, code = 768, frequency = 120kHz; GMA7–GMA12, code = 256, frequency = 120kHz 40 Output Resistance Buffer is disabled 78 kI Maximum Capacitive Load Placed directly at output 150 pF Noise RMS noise (10MHz bandwidth) 375 FV Short-Circuit Current Output connected to either VCOM amplifier supplies 600 mA Total Output Error TA = +25NC, code = 256, VAVDD_AMP = 9V and 20V Load Regulation -80mA P ILOAD P +80mA, code = 256 0.5 mV/mA Low Output Voltage Sinking 10mA, referred to lower supply rail 0.15 0.2 V High Output Voltage Sourcing 10mA, referred to upper supply rail -0.2 -0.15 V Power-Supply Rejection Ratio 40 mV 0.5 mV/mA 0.15 0.2 V -0.2 -0.15 V 90 dB VCOM OUTPUT (VCOM) Maxim Integrated 40 mV 5 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages ELECTRICAL CHARACTERISTICS (continued) (VAVDD1 = 18V, VAVDD2 = VAVDD_AMP = 9V, VDVDD = 3.3V, VAGND = 0V, VCOM = VCOM_FB, programmable reference code = 905, no load, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS 9V P VAVDD_AMP P 20V, code = 256 Power-Supply Rejection Ratio MIN TYP 60 90 MAX UNITS dB Frequency = 120kHz, code = 256 40 Maximum Capacitive Load Placed directly at output 50 pF Slew Rate Swing 4VP-P at VCOM, 10% to 90%, RL = 10kI, CL = 50pF 100 V/Fs Bandwidth RL = 10kI, CL = 50pF 60 MHz Noise RMS noise (10MHz bandwidth) 375 FV Note 2: 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design. DIGITAL I/O CHARACTERISTICS (VDVDD = 3.3V, VAGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL Input High Voltage VIH Input Low Voltage VIL CONDITIONS MIN Low-Level Output Voltage VOL Open drain, ISINK = 3mA 0 Low-Level Output Current IOL VOL = 0.4V 20 0.05 x DVDD VIN = 0 or DVDD -10 Input Capacitance Power-Down Input Current DVDD = 0, VIN = 1.98V V V 0.4 V mA +0.01 +10 FA +10 FA 5 IIN UNITS V 0.3 x DVDD VHYS IIH, IIL MAX 0.7 x DVDD Hysteresis of Schmitt Trigger Inputs Input Leakage Current TYP -10 pF I2C TIMING CHARACTERISTICS (VDVDD = 3.3V, VAGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Serial-Clock Frequency Hold Time (REPEATED) START Condition SYMBOL CONDITIONS fSCL tHD,STA MIN 0 After this period, the first clock pulse is generated TYP MAX UNITS 1000 kHz 0.26 Fs SCL Pulse-Width Low tLOW 0.5 Fs SCL Pulse-Width High tHIGH 0.26 Fs Setup Time for a REPEATED START Condition tSU,STA 0.26 Fs Data Hold Time tHD,DAT 0 ns Data Setup Time tSU,DAT I2C-bus devices 50 ns SDA and SCL Receiving Rise Time tR 120 ns SDA and SCL Receiving Fall Time tF 120 ns SDA Transmitting Fall Time tF 120 ns 6 Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages I2C TIMING CHARACTERISTICS (continued) (VDVDD = 3.3V, VAGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL Setup Time for STOP Condition Bus Free Time Between STOP and START Conditions Bus Capacitance CONDITIONS MIN TYP MAX UNITS tSU,STO 0.26 Fs tBUF 0.5 Fs CB 550 pF Data Valid Time tVD;DAT 0.45 Fs Data Valid Acknowledge Time tVD;ACK 0.45 Fs 50 ns Pulse Width of Suppressed Spike tSP 0 Typical Operating Characteristics (VAVDD1 = 18V, VAVDD2 = VAVDD_AMP = 9V, VDVDD = 3.3V, VAGND = 0V, VCOM = VCOM_FB, programmable reference code = 905, no load, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) GAMMA LOAD REGULATION 7.92 0.2 9.02 0.1 9.00 8.98 0 -0.1 8.96 -0.2 8.94 -0.3 8.92 -0.4 -0.5 -100 -80 -60 -40 -20 0 20 40 60 80 100 0 0.3 INL (LSB) 0.1 DNL (LSB) 0.2 0 -0.1 0 -0.1 -0.2 -0.2 -0.2 -0.3 -0.3 -0.3 -0.4 -0.4 -0.4 -0.5 -0.5 CODE Maxim Integrated 800 1000 1000 0.3 0.1 600 800 0.4 0.1 400 1000 MAX9679 toc06 MAX9679 toc05 0.4 0.2 -0.1 800 0.5 0.2 0 600 VCOM INL 0.5 MAX9679 toc04 0.3 400 CODE VCOM DNL 0.4 200 200 CURRENT LOAD (mA) GAMMA INL 0.5 0 MAX9679 toc03 0.3 9.04 CURRENT LOAD (A) INL (LSB) 0.4 8.90 0.020 0.015 0.010 0.005 0 -0.005 -0.010 -0.015 7.90 -0.020 7.91 MAX9679 toc02 9.06 GAMMA DNL 0.5 DNL (LSB) 7.93 VCOM CODE x 1FF 9.08 VCOM VOLTAGE (V) 7.94 GAMMA VOLTAGE (V) VCOM LOAD REGULATION 9.10 MAX9679 toc01 7.95 -0.5 0 200 400 600 CODE 800 1000 0 200 400 600 CODE 7 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Typical Operating Characteristics (continued) (VAVDD1 = 18V, VAVDD2 = VAVDD_AMP = 9V, VDVDD = 3.3V, VAGND = 0V, VCOM = VCOM_FB, programmable reference code = 905, no load, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) BANK SWITCHING SETTLING TIME FOR VCOM GAMMA OUTPUT vs. TEMPERATURE GAMMA CODE x 1FF GAMMA OUTPUT VOLTAGE (V) 9.995 MAX9679 toc08 MAX9679 toc07 10.000 9.990 VCOM 5V/div 9.985 9.980 9.975 BKSEL 2V/div 9.970 9.965 9.960 -40 -15 10 35 60 85 400ns/div TEMPERATURE (°C) BANK SWITCHING SETTLING TIME FOR GAMMA BANK SWITCHING SETTLING TIME FOR GAMMA BANK SWITCHING SETTLING TIME FOR VCOM MAX9679 toc09 BKSEL 5V/div VCOM 5V/div BKSEL 5V/div GMA1 5V/div GMA1 5V/div 200ns/div POWER-SUPPLY REJECTION RATIO (GMA = 9V) POWER-SUPPLY REJECTION RATIO (VCOM = 9V) -10 MAX9679 toc13 0 MAX9679 toc12 0 -10 -20 PSRR (dB) -20 PSRR (dB) BKSEL 5V/div 200ns/div 200ns/div -30 -40 -30 -40 -50 -50 VAVDD_AMP = 18V Q100mVP-P VAVDD1 = 18V Q100mVP-P -60 10k 100k -60 1M FREQUENCY (Hz) 8 MAX9679 toc11 MAX9679 toc10 10M 10k 100k 1M 10M FREQUENCY (Hz) Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Typical Operating Characteristics (continued) (VAVDD1 = 18V, VAVDD2 = VAVDD_AMP = 9V, VDVDD = 3.3V, VAGND = 0V, VCOM = VCOM_FB, programmable reference code = 905, no load, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) POWER-SUPPLY REJECTION RATIO (VPREF = 2.5V) GAMMA LOAD TRANSIENT VCOM LOAD TRANSIENT MAX9679 toc15 -10 -20 PSRR (dB) MAX9679 toc16 MAX9679 toc14 0 IOUT IOUT GMA1 5V/div VVCOM 1V/div 100mA/div 200mA/div -30 -40 -50 VAVDD1 = 18V Q100mVP-P -60 10k 100k 1M 2µs/div 10M 2µs/div FREQUENCY (Hz) VCOM PROGRAM TO OUTPUT DELAY GAMMA PROGRAM TO OUTPUT DELAY MAX9679 toc18 MAX9679 toc17 SDA 2V/div SDA 2V/div SCL 2V/div SCL 2V/div GMA1 5V/div VVCOM 5V/div 20µs/div 20µs/div PROGRAMMABLE REFERENCE vs. AVDD1 SUPPLY VOLTAGE PROGRAMMABLE REFERENCE vs. TEMPERATURE 4.9635 4.9625 4.9620 4.9625 VPREF (V) VPREF (V) 4.9630 4.9620 4.9615 4.9615 4.9610 4.9605 4.9610 4.9600 4.9605 4.9600 9 10 11 12 13 14 VAVDD1 (V) Maxim Integrated MAX9679 toc20 4.9630 MAX9679 toc19 4.9640 15 16 17 18 4.9595 -55 -10 35 80 125 TEMPERATURE (°C) 9 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages 16 GMA5 17 GMA7 GMA8 18 GMA6 GMA9 TOP VIEW GMA10 Pin Configuration 15 14 13 GMA11 19 12 GMA4 GMA12 20 11 GMA3 AVDD2 21 10 GMA2 MAX9679 AVDD_AMP 22 VCOM 23 EP 4 5 6 SDA A0 DVDD 3 BKSEL 2 SCL 1 AGND VCOM_FB 24 + 9 GMA1 8 AVDD1 7 AGND TQFN Pin Description 10 PIN 1, 7 2 3 4 5 6 NAME AGND DVDD SCL SDA BKSEL A0 FUNCTION Analog Ground Digital Power Supply. Bypass DVDD with a 0.1FF capacitor to AGND. I2C-Compatible Serial-Clock Input I2C-Compatible Serial-Data Input/Output Bank Select Logic Input. Selects which bank of volatile registers are switched through to the DACs. I2C-Compatible Device Address Bit 0 (Input) 8 AVDD1 Analog Power Supply 1. The buffers for GMA1 through GMA6 operate from AVDD1. Bypass AVDD1 with a 0.1FF capacitor to AGND. 9 10 11 12 13 14 15 16 17 18 19 20 GMA1 GMA2 GMA3 GMA4 GMA5 GMA6 GMA7 GMA8 GMA9 GMA10 GMA11 GMA12 Gamma Gamma Gamma Gamma Gamma Gamma Gamma Gamma Gamma Gamma Gamma Gamma 21 AVDD2 Analog Power Supply 2. The buffers for GMA7 through GMA12 operate from AVDD2. Bypass AVDD2 with a 0.1FF capacitor to AGND. 22 23 AVDD_AMP VCOM 24 VCOM_FB — EP DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Output Output Output Output Output Output Output Output Output Output Output Output 1 2 3 4 5 6 7 8 9 10 11 12 Power Supply for VCOM Amplifier. Bypass AVDD_AMP with a 0.1FF capacitor to AGND. VCOM Output Feedback for VCOM Amplifier. VCOM_FB is the negative input terminal of the VCOM operational amplifier. Exposed Pad. EP is internally connected to AGND. EP must be connected to AGND. Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Detailed Description The MAX9679 combines gamma, VCOM, and the DAC reference voltage into a single chip. All the output voltages are programmable. Power sequencing is well behaved since a single chip generates all the various reference voltages needed for the LCD panel. Previous generations of programmable gamma chips required an external reference voltage for the digital-to-analog converters (DACs). This IC integrates a programmable reference voltage (VPREF) for the DACs, eliminating the need for an external reference voltage. Accuracy of the full-scale programmable reference voltage is ±0.1%, and resolution is 10 bits. Both the DC and AC power-supply rejection of the programmable reference voltage is extremely high since it is powered from an internal linear regulator. The gamma outputs are divided into an upper bank (GMA1–GMA6) that is powered from AVDD1 and a lower bank (GMA7–GMA12) that is powered from AVDD2. AVDD1 is the analog supply voltage for the LCD panel. AVDD2 can be connected to the same supply as AVDD1. If the IC's heat generation needs to be reduced, AVDD2 can be connected to a lower voltage such as 12V (input voltage to the LCD panel) or HVDD (half of the AVDD1 supply). The VCOM operational amplifier operates from AVDD_AMP. Similar to AVDD2, AVDD_AMP can be connected to AVDD1, 12V, or HVDD. Peak VCOM output current is 600mA. The negative input terminal of the VCOM operational amplifier is available for applications that require external push-pull transistors. The IC contains nonvolatile, multiple-time programmable memory that can store the gamma, VCOM, and the programmable reference codes. The interface and control of the IC are completely digital. Functions that are not real-time such as gamma and VCOM are set through the I2C interface. Real-time functions, such as the switching of the gamma and VCOM, are done through the dedicated logic input signal BKSEL. Programmable Reference The IC has an internal programmable reference, which when referred to the output, has a full-scale voltage of 20V (Q0.1%). The reference voltage is calculated using the following equation: where CODE is the numeric value stored in register address and N is the bits of resolution. For the IC, N = 10 and CODE ranges from 0 to 1023. Note that VPREF cannot be 20V because the maximum value of CODE is always one LSB less than the full-scale voltage. When the programmable reference code is 1023, then VPREF is: VPREF = (20V × 1023)/210 = 19.98V 10-Bit Digital-to-Analog Converters VPREF sets the full-scale output of the DACs. Determine the output voltages using the following equations: VGMA_ = (VPREF × CODE)/2N VVCOM = (VPREF × CODE)/2N where CODE is the numeric value of the DAC’s binary input code and N is the bits of resolution. For the IC, N = 10 and CODE ranges from 0 to 1023. Note that the DAC can never output VPREF because the maximum value of CODE is always one LSB less than the reference. For example, if VPREF = 16V and the DAC CODE is 1023, then the gamma output voltage is: VGMA_ = (16V × 1023)/210 = 15.98438V Gamma Buffers The gamma buffers can typically source or sink 4mA of DC current within 200mV of the supplies. The source drivers can kick back a great deal of current to the buffer outputs during a horizontal line change or a polarity switch. The DAC output buffers can source/sink 200mA of peak transient current to reduce the recovery time of the output voltages when critical levels and patterns are displayed. VCOM Amplifier The operational amplifier attached to the VCOM DAC holds the VCOM voltage stable while providing the ability to source and sink 600mA into the backplane of a TFTLCD panel. The operational amplifier can directly drive the capacitive load of the TFT-LCD backplane without the need for a series resistor in most cases. The VCOM amplifier has current limiting on its output to protect its bond wires. If the application requires more than 600mA, buffer the output of the VCOM amplifier with a MAX9650, a VCOM power amplifier. The MAX9650 can source or sink 1.3A of current. VPREF = (20V × CODE)/2N Maxim Integrated 11 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Switching Gamma and VCOM acknowledging commands after all registers have been loaded from MTP. The BKSEL signal determines which set of gamma and VCOM codes is driven out (Table 2). The IC features thermal-shutdown protection with temperature hysteresis. When the die temperature reaches +165NC, all of the gamma outputs and the VCOM output are disabled. When the die cools down by 15NC, the outputs are enabled again. The IC can keep two independent sets of gamma and VCOM codes in volatile memory (Table 1). Multiple-Time Programmable (MTP) Memory MTP memory, which is a form of nonvolatile memory, stores the DAC code values even when the chip is not powered. When the chip is powered up, the code values are automatically transferred from MTP memory to the I2C registers. See the Power-On Reset (POR)/Power-Up section for more details. The user can program DAC codes into MTP memory up to 100 times. Power-On Reset (POR)/Power-Up The POR circuit that monitors DVDD ensures that all I2C registers are reset to their MTP values upon power-up or POR. Once DVDD rises above 2.4V (typ), the POR circuit releases the I2C registers and the values stored in MTP are loaded. Should DVDD drop to less than 2.4V typical, then the contents of the registers can no longer be guaranteed and a reset is generated. When DVDD rises back above the POR voltage, the values stored in MTP are loaded back into the I2C registers. The transfer time of the MTP registers to I2C registers is 300Fs typical and is less than 400Fs in the worst case. During this time, AVDD should not be powered up, and the I2C does not acknowledge any commands. The I2C only starts Table 1. Registers in Each of the Two Independent Sets REGISTERS IN SET 1 GMA1BK1 GMA2BK1 GMA3BK1 GMA4BK1 GMA5BK1 GMA6BK1 GMA7BK1 GMA8BK1 GMA9BK1 GMA10BK1 GMA11BK1 GMA12BK1 VCOM1 VCOM1MIN VCOM1MAX 12 REGISTERS IN SET 2 GMA1BK2 GMA2BK2 GMA3BK2 GMA4BK2 GMA5BK2 GMA6BK2 GMA7BK2 GMA8BK2 GMA9BK2 GMA10BK2 GMA11BK2 GMA12BK2 VCOM2 VCOM2MIN VCOM2MAX Thermal Shutdown Register and Bit Descriptions The IC has both volatile memory and also nonvolatile MTP memory. The volatile memory structure has I2C registers and DAC registers (see the Functional Diagram). The I2C master must first write data into the I2C registers of the IC before the data can be moved into the DAC registers (or MTP memory). The advantage of having the I2C registers serve as a data buffer for the IC is that data can be transferred in a parallel operation from the I2C registers to the DAC registers, and so the entire gamma curve is essentially updated instantaneously rather than serially on a point-by-point basis. The volatile memory stores two independent sets of gamma curves and VCOM codes. The first set consists of gamma codes from bank 1, VCOM1 code, VCOM1MIN code, and VCOM1MAX code. The second set consists of gamma codes from bank 2, VCOM2 code, VCOM2MIN code, and VCOM2MAX code. In addition, volatile memory stores the programmable reference code. Table 2. BKSEL Logic Table OUTPUT GMA1 GMA2 GMA3 GMA4 GMA5 GMA6 GMA7 GMA8 GMA9 GMA10 GMA11 GMA12 VCOM BKSEL = LOW GMA1BK1 GMA2BK1 GMA3BK1 GMA4BK1 GMA5BK1 GMA6BK1 GMA7BK1 GMA8BK1 GMA9BK1 GMA10BK1 GMA11BK1 GMA12BK1 VCOM1 BKSEL = HIGH GMA1BK2 GMA2BK2 GMA3BK2 GMA4BK2 GMA5BK2 GMA6BK2 GMA7BK2 GMA8BK2 GMA9BK2 GMA10BK2 GMA11BK2 GMA12BK2 VCOM2 Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages The nonvolatile MTP memory stores all the data except for the second set of gamma curves and VCOM codes. During power-up, the codes in the MTP memory are transferred into the I2C and DAC registers. Each memory location whether in nonvolatile or volatile memory holds a 10-bit word. Two bytes must be read or written through the I2C interface for every register. Table 3 shows the register map. The same register address and register name exists in the MTP memory bank, I2C register bank, and the DAC register bank. The write control bits determine into which memory location the data is stored. Register Description Only the 10 least significant bits (LSBs) are written to the registers (Table 4). During a write operation, the write control bits (the two MSBs) are stripped from the incoming data stream and are used to determine whether the MTP or DAC registers are updated (Table 5). Note the I2C registers are only 10 bits. Table 3. Register Map REGISTER ADDRESS REGISTER NAME REGISTER DESCRIPTION POWER-ON RESET VALUE MTP FACTORY INITIALIZATION VALUE 0x00 GMA1BK1 Gamma 1 of Bank 1 0x200 0x200 0x01 GMA2BK1 Gamma 2 of Bank 1 0x200 0x200 0x02 GMA3BK1 Gamma 3 of Bank 1 0x200 0x200 0x03 GMA4BK1 Gamma 4 of Bank 1 0x200 0x200 0x04 GMA5BK1 Gamma 5 of Bank 1 0x200 0x200 0x05 GMA6BK1 Gamma 6 of Bank 1 0x200 0x200 0x06 GMA7BK1 Gamma 7 of Bank 1 0x200 0x200 0x07 GMA8BK1 Gamma 8 of Bank 1 0x200 0x200 0x08 GMA9BK1 Gamma 9 of Bank 1 0x200 0x200 0x09 GMA10BK1 Gamma 10 of Bank 1 0x200 0x200 0x0A GMA11BK1 Gamma 11 of Bank 1 0x200 0x200 0x0B GMA12BK1 Gamma 12 of Bank 1 0x200 0x200 0x0C Reserved — 0x000 — 0x0D Reserved — 0x000 — 0x0E Reserved — 0x000 — 0x0F Reserved — 0x000 — 0x10 Reserved — 0x000 — 0x11 Reserved — 0x000 — 0x12 VCOM1 Common voltage 1 0x200 0x200 0x13 Reserved — 0x000 — 0x14 Reserved — 0x000 — 0x15 Reserved — 0x000 — 0x16 Reserved — 0x000 — 0x17 Reserved — 0x000 — 0x18 VCOM1MIN Minimum VCOM1 value 0x000 0x000 0x19 VCOM1MAX Maximum VCOM1 value 0x3FF 0x3FF 0x1A Reserved — 0x000 — 0x1B Reserved — 0x000 — 0x1C Reserved — 0x000 — 0x1D Reserved — 0x000 — 0x1E Reserved — 0x000 — Maxim Integrated 13 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Table 3. Register Map (continued) REGISTER ADDRESS REGISTER NAME REGISTER DESCRIPTION POWER-ON RESET VALUE MTP FACTORY INITIALIZATION VALUE 0x1F VPREF Programmable reference voltage 0x200 0x200 0x20 GMA1BK2 Gamma 1 of Bank 2 0x200 0x21 GMA2BK2 Gamma 2 of Bank 2 0x200 0x22 GMA3BK2 Gamma 3 of Bank 2 0x200 0x23 GMA4BK2 Gamma 4 of Bank 2 0x200 0x24 GMA5BK2 Gamma 5 of Bank 2 0x200 0x25 GMA6BK2 Gamma 6 of Bank 2 0x200 0x26 GMA7BK2 Gamma 7 of Bank 2 0x200 0x27 GMA8BK2 Gamma 8 of Bank 2 0x200 0x28 GMA9BK2 Gamma 9 of Bank 2 0x200 0x29 GMA10BK2 Gamma 10 of Bank 2 0x200 0x2A GMA11BK2 Gamma 11 of Bank 2 0x200 0x2B GMA12BK2 Gamma 12 of Bank 2 0x200 0x2C VCOM2 Common voltage 2 0x200 0x2D VCOM2MIN Minimum VCOM2 value 0x000 0x2E VCOM2MAX Maximum VCOM2 value 0x3FF Table 4. Register Description REG REG ADDR B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 GMA1BK1 0x00 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA2BK1 0x01 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA3BK1 0x02 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA4BK1 0x03 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA5BK1 0x04 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA6BK1 0x05 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA7BK1 0x06 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA8BK1 0x07 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA9BK1 0x08 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA10BK1 0x09 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA11BK1 0x0A W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA12BK1 0x0B W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved 0x0C — — — — — — — — — — — — — — — — Reserved 0x0D — — — — — — — — — — — — — — — — Reserved 0x0E — — — — — — — — — — — — — — — — Reserved 0x0F — — — — — — — — — — — — — — — — Reserved 0x10 — — — — — — — — — — — — — — — — Reserved 0x11 — — — — — — — — — — — — — — — — VCOM1 0x12 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 14 Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Table 4. Register Description (continued) REG REG ADDR B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved 0x13 — — — — — — — — — — — — — — — — Reserved 0x14 — — — — — — — — — — — — — — — — Reserved 0x15 — — — — — — — — — — — — — — — — Reserved 0x16 — — — — — — — — — — — — — — — — Reserved 0x17 — — — — — — — — — — — — — — — — VCOM1MIN 0x18 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VCOM1MAX 0x19 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved 0x1A — — — — — — — — — — — — — — — — Reserved 0x1B — — — — — — — — — — — — — — — — Reserved 0x1C — — — — — — — — — — — — — — — — Reserved 0x1D — — — — — — — — — — — — — — — — Reserved 0x1E — — — — — — — — — — — — — — — — VPREF 0x1F W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA1BK2 0x20 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA2BK2 0x21 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA3BK2 0x22 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA4BK2 0x23 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA5BK2 0x24 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA6BK2 0x25 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA7BK2 0x26 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA8BK2 0x27 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA9BK2 0x28 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA10BK2 0x29 W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA11BK2 0x2A W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMA12BK2 0x2B W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VCOM2 0x2C W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VCOM2MIN 0x2D W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VCOM2MAX 0x2E W1 W0 X X X X b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Table 5. Write Control Bits W1 W0 0 0 No update. 0 1 MTP registers get updated when the current I2C register has finished updating. See the Nonvolatile Memory section for more details. 1 0 All DAC registers get updated when the current I2C register has finished updating (end of B0). 1 1 No update. Maxim Integrated ACTION 15 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages VCOM Programmable Range (VCOMMIN and VCOMMAX) two MSBs of the register address byte. Table 6 shows the memory write bits. Set both M1 and M0 to low or high when writing to or reading from the I2C registers through the I2C bus. The IC features a programmable range for VCOM1 and VCOM2. VCOM1MIN and VCOM1MAX registers provide low and high limits for the VCOM1 register. At the factory, VCOM1MIN is set to 0 and VCOM1MAX is set to 1023 (default values) to provide the full rail-to-rail programmable range for VCOM1. Later, the user can define their own limits by programming VCOM1MIN and VCOM1MAX registers and MTP. Volatile Memory The IC features a double-buffered register structure with the I2C registers as the first buffer and the DAC registers as the second buffer. The benefit is that the I2C registers can be updated without updating the DAC registers. After the I2C registers have been updated, the value or values in the I2C registers can be transferred all at the same time to the DAC registers. VCOM1 register values are limited to the defined range. If the VCOM1 register accidentally gets programmed with a value higher than VCOM1MAX, it automatically gets locked to the VCOM1MAX value. The I2C bus does acknowledge and receive the data sent on the bus; however, internally the part recognizes that the value is outside of the range and adjusts it accordingly. The same scenario is true if the value programming VCOM1 is below VCOM1MIN. Figure 1 shows how to program a single DAC register. The output voltage is updated after sending LSB (D0). It is possible to write to multiple I2C registers first, then update the output voltage of all channels simultaneously, as shown in Figure 2. In this mode, it is possible for the I2C master to write to all registers of the IC (gamma, VCOM, and programmable reference) in one communication. In that case, the value programmed on addresses 0x0C–0x11, 0x13–0x17, 0x1A–0x1E, and 0x20–0x2E are meaningless. However, the IC does send an acknowledge bit for each of the two bytes on any of these addresses. The control bits (W1, W0) shown in Figure 2 are set in a way that all DACs are programmed to their desired value with no changes to the output voltages until the LSB of the last DAC is received and then all the channels update simultaneously. VCOM2MIN and VCOM2MAX have a similar relationship with VCOM2. Memory The IC includes both volatile memory (I2C registers and DAC registers) and nonvolatile memory (MTP registers). It is possible to write to each single volatile memory register from a MTP register individually or to write to all at once through memory write bits (M1, M0), which are the Table 6. Memory Write Bits M1 M0 0 0 None. 0 1 Only the addressed I2C registers and DAC registers get set to the MTP values. 1 0 All I2C registers and DAC registers get set to the MTP values. 1 1 None. S 1 ACTION 1 1 0 1 0 B1 R/W =0 A SLAVE ID 1 0 X X X DATA X D9 D8 A 0 0 M1 M0 D7 D6 D5 D4 D3 D2 D1 D0 A D0 A DAC/VCOM ADDRESS D5 D4 D3 D2 D1 P DATA Figure 1. Single DAC Programming 16 Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages S 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 0 0 X X X X D9 D8 A 0 0 M1 M0 D7 D6 D5 0 X X D5 0 X X X D2 D1 D0 A D4 D3 D2 D1 D0 A D2 D1 D0 A D2 D1 D0 A DATA X D9 D8 A D7 D6 D5 DATA 1 D3 DAC/VCOM ADDRESS DATA 0 D4 D4 D3 DATA X X D9 D8 A D7 DATA D6 D5 D4 D3 P DATA Figure 2. Multiple (or All) DACs Programming Nonvolatile Memory The IC is able to write to nonvolatile memory (MTP) of any single DAC/VCOM register in a single or burst I2C transaction. This memory can be written to at least 100 times. Figure 3 shows a single write to a MTP address. The control bits are set in a way that the MTP register is updated at the end of LSB (D0). Figure 4 shows how to program multiple MTP registers in one communication transition. Similar to programming the volatile memory, the first 2 bytes of data correspond to the DAC/VCOM address specified by the master on the previous byte and the following 2 bytes of data correspond to the next address and so on. In this configuration, all the MTP registers are programmed at the same time following the LSB of the last set of data byte. The last set of data bytes is different than the previous bytes because bit 15 and bit 14 are 0b0 and 0b1, respectively. If, for some reason, the master issues a stop condition before sending the last two bytes of the data with appropriate values of bit 15 (0b0) and bit 14 (0b1), then none of the MTP registers are updated. Programming the MTP registers also updates the DAC registers and consequently the output voltages. Similar to multiple volatile memory programming, the update Maxim Integrated only occurs after the LSB of the last byte is received. All the outputs are programmed and updated simultaneously; however, depending on the number of MTP registers: it takes 31ms to 500ms to store the values into the nonvolatile memory. During this time, the IC is not available on the I2C bus and any communication from the master should be delayed until the MTP is programmed. Any attempt from the I2C master to talk to the IC is not acknowledged. General and Single Acquire Commands It is possible to update all the DAC outputs to the previously stored MTP values with one special command. Set the 2 MSB bits (M1 and M0) of the register address to 0b10 to set all the I2C registers, DAC registers and the output voltages to the values of MTP (Figure 5). The IC ignores the rest of the register address in this case. It is also possible to update the I2C register, DAC register and DAC output voltage of only one channel from the MTP. Set the 2 MSB bits (M1 and M0) of the DAC/VCOM address to 0b01 (Figure 6) to move a specific value from MTP into the I2C register and DAC register of a single channel. . 17 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages S 1 1 1 0 1 0 R/W =0 B1 A SLAVE ID 0 1 X X X X D9 D8 A 0 0 M1 M0 D7 D6 D5 D4 D3 D2 D1 D0 A A P DAC/VCOM ADDRESS D5 D4 DATA D3 D2 D1 D0 D1 D0 A DATA Figure 3. Single MTP Programming S 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 0 0 X X X X D9 D8 A 0 0 M1 M0 D5 D7 D6 D4 D5 D4 DATA 0 0 X X 1 X X X D2 D3 D2 D1 D0 A D2 D1 D0 A D2 D1 D0 A DATA X D9 D8 A D7 D6 D5 D4 DATA 0 D3 DAC/VCOM ADDRESS D3 DATA X X D9 D8 A D7 D6 D5 D4 DATA D3 P DATA Figure 4. Multiple MTP Programming S 1 1 1 0 1 0 B1 R/W =0 A SLAVE ID 1 0 M1 M0 0 0 0 0 0 0 A P D5 D4 D3 D2 D1 D0 A P Figure 5. General Acquire Command to Updated All Outputs with MTP S 1 1 1 0 SLAVE ID 1 0 B1 R/W =0 A 0 1 M1 M0 DAC/VCOM ADDRESS Figure 6. Single Acquire Command to Updated One Output with MTP 18 Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages SDA tBUF tSU,STA tSU,DAT tHD,STA tHD,DAT tLOW SCL tSP tSU,STO tHIGH tHD,STA tR tF REPEATED START CONDITION START CONDITION STOP CONDITION START CONDITION Figure 7. I2C Interface Timing Diagram I2C Serial Interface The IC features an I2C/SMBusK-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the devices and the master at clock rates up to 1MHz. Figure 7 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the devices by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9679 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the devices transmits the proper slave address followed by a series of nine SCL pulses. The devices transmit data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the devices from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals. See the START and STOP Conditions section. SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START (S) condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP (P) condition is a low-tohigh transition on SDA while SCL is high (Figure 8). A START condition from the master signals the beginning of a transmission to the IC. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START (Sr) condition is generated instead of a STOP condition. S Sr P SCL SDA Figure 8. START, STOP, and REPEATED START Conditions SMBus is a trademark of Intel Corp. Maxim Integrated 19 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Early STOP Conditions The IC recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the 7 most significant bits (MSBs) followed by the read/write (R/W) bit. Set the R/W bit to 1 to configure the IC to read mode. Set the R/W bit to 0 to configure the IC to write mode. The address is the first byte of information sent to the IC after the START condition. The IC’s slave address is configured with A0. Table 7 shows the possible addresses for the IC. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the IC uses to handshake receipt of each byte of data when in write mode (Figure 9). Table 7. Slave Address A0 READ ADDRESS AGND E9h (11101001) E8h (11101000) DVDD EBh (11101011) EAh (11101010) SCL The slave address with the R/W bit set to 0 indicates that the master intends to write data to the IC. The IC acknowledges receipt of the address byte during the master-generated 9th SCL pulse. CLOCK PULSE FOR ACKNOWLEDGMENT 1 2 8 Write Data Format A write to the IC consists of transmitting a START condition, the slave address with the R/W bit set to 0, one data byte of data to configure the internal register address pointer, one word (2 bytes) of data or more, and a STOP condition. Figure 10 illustrates the proper frame format for writing one word of data to the IC. Figure 11 illustrates the frame format for writing n-bytes of data to the IC. WRITE ADDRESS START CONDITION The IC pulls down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the IC is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the IC, followed by a STOP condition. The second byte transmitted from the master configures the IC’s internal register address pointer. The IC’s internal address pointer consists of the six least significant bits (LSB) of the second byte. The 2 MSBs of the second byte (M1 and M0) are set to 00b when writing to the internal registers. See the Memory section for more details. The pointer tells the IC where to write the next byte of data. An acknowledge pulse is sent by the IC upon receipt of the address pointer data when writing to the 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 9. Acknowledge ACKNOWLEDGE FROM THE IC ACKNOWLEDGE FROM THE IC ACKNOWLEDGE FROM THE IC W1 W0 X ACKNOWLEDGE FROM THE IC S 0 SLAVE ADDRESS A 0 0 REGISTER ADDRESS A X X X D9 D8 DATA BYTE 1 D7 D6 D5 D4 D3 D2 D1 D0 A DATA BYTE 2 A/A P ONE WORD R/W M1 M0 AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 10. Writing a Word of Data to the IC 20 Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages DAC registers. When writing to the MTP, a not acknowledge is sent from the IC after the master writes the final byte of data, followed by a STOP condition. autoincrements to 0xFF and stays at 0xFF until the master writes a new value into the register address pointer. The third and fourth bytes sent to the IC contain the data that is written to the chosen register and which type of register it writes to, volatile (DAC) or nonvolatile memory (MTP). See the Nonvolatile Memory section for more details. An acknowledge pulse from the IC signals receipt of each data byte. The address pointer autoincrements to the next register address after receiving every other data byte. This autoincrement feature allows a master to write to sequential register address locations within one continuous frame. The master signals the end of transmission by issuing a STOP condition. If data is written into register address 0x2E, the address pointer The master presets the address pointer by first sending the IC’s slave address with the R/W bit set to 0 followed by the register address with M1 and M0 set to 00 after a START condition. The IC acknowledges receipt of its slave address and the register address by pulling SDA low during the 9th SCL clock pulse. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The IC transmits the contents of the specified register. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after every other read Read Data Format ACKNOWLEDGE THE IC ACKNOWLEDGE FROM THE IC ACKNOWLEDGE FROM THE IC W1 W0 X ACKNOWLEDGE FROM THE IC S 0 SLAVE ADDRESS A 0 0 REGISTER ADDRESS A X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A DATA BYTE 1 A DATA BYTE 2 ONE WORD R/W M1 M0 AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER ACKNOWLEDGE FROM THE IC ACKNOWLEDGE FROM THE IC W1 W0 X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A DATA BYTE n-1 DATA BYTE n A/A P ONE WORD Figure 11. Writing n-Bytes of Data to the IC S SLAVE ADDRESS 0 ACKNOWLEDGE FROM THE IC ACKNOWLEDGE FROM THE IC ACKNOWLEDGE FROM THE IC A 0 0 REGISTER ADDRESS A Sr SLAVE ADDRESS REPEATED START R/W 1 A R/W M1 M0 ACKNOWLEDGE FROM MASTER X X X X X X DATA BYTE 1 NOT ACKNOWLEDGE FROM MASTER D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A DATA BYTE 2 A P ONE WORD AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 12. Reading One Indexed Word of Data from the IC Maxim Integrated 21 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages ACKNOWLEDGE FROM THE IC SLAVE ADDRESS S 0 ACKNOWLEDGE FROM THE IC A 0 X X X X DATA BYTE 1 SLAVE ADDRESS Sr 1 ACKNOWLEDGE FROM MASTER D9 D8 DATA BYTE 2 NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MASTER D7 D6 D5 D4 D3 D2 D1 D0 A A R/W M1 M0 ACKNOWLEDGE FROM MASTER X A REPEATED START R/W X REGISTER ADDRESS 0 ACKNOWLEDGE FROM THE IC X A X X X X X DATA BYTE n-1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A DATA BYTE n A P ONE WORD ONE WORD AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 13. Reading n Bytes of Indexed Data from the IC data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from the register address location set by the previous transaction and not 0x00, and subsequent reads autoincrement the address pointer until the next STOP condition. Attempting to read from register addresses higher than 0x2E results in repeated reads from a dummy register containing all one data. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 12 and Figure 13 illustrate the frame format for reading data from the IC. Applications Information Power Sequencing AVDD1, AVDD2, AVDD_AMP, and DVDD are independent of each other and can be powered up and powered down in any sequence. However, output voltages are only guaranteed to power up in a well-behaved manner when DVDD is powered up first and powered down last with 1ms allowed between DVDD and AVDD (Figure 14 and Figure 15). Connecting AVDD2 and AVDD_AMP to half AVDD supply reduces the temperature of the IC. If AVDD2 and AVDD_AMP are connected to the 12V supply to the LCD module because a half AVDD supply is not available, then Figure 16 shows the power-up and power-down sequence. The gamma and VCOM outputs 22 are close to ground until AVDD1 is greater than its power-on reset voltage because AVDD1 is used to power the internal voltage reference. DVDD must be powered up within 25ms from 1.5V to 2.3V to ensure proper MTP loading/read. See Figure 17. PCB Layout and Grounding If the IC is mounted using reflow soldering or waver soldering, the ground vias for the exposed pad should have a finished hole size of at least 14 mils to ensure adequate wicking of soldering onto the exposed pad. If the IC is mounted using solder mask technique, the vias requirement does not apply. In either case, the exposed pad on the TQFN package is electrically connected to both digital and analog grounds through a low thermal resistance path to ensure adequate heat dissipation. Do not route traces under these packages. The layout of the exposed pad should have multiple small vias over a single large via as shown in Figure 18. Thermal resistance between top and ground layers can be optimized with multiple small vias, and it is recommended to have a plated via with 15 mils diameter. The via should be flooded with solder for good thermal performance. Power-Supply Bypassing The IC operates from a single 9V to 20V analog supply (AVDD) and a 2.7V to 3.6V digital supply (DVDD). Bypass AVDD to AGND with 0.1FF and 10FF capacitors in parallel. Use an extensive ground plane to ensure optimum performance. Bypass DVDD to AGND with a 0.1FF capacitor. The 0.1FF bypass capacitors should be as close as possible to the device. Refer to the MAX9679 Evaluation Kit for a proven PCB layout. Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages VOLTAGE AVDD1 = AVDD2 = AVDD_AMP DVDD AVDD1 = AVDD2 = AVDD_AMP DVDD TIME >1ms Figure 14. Conventional Power-Up and Power-Down Sequence VOLTAGE AVDD1 AVDD2 = AVDD_AMP DVDD AVDD1 AVDD2 = AVDD_AMP DVDD TIME >1ms Figure 15. Power-Up and Power-Down Sequence with AVDD2 and AVDD_AMP Connected to Half AVDD VOLTAGE AVDD1 AVDD2 = AVDD_AMP DVDD AVDD1 AVDD2 = AVDD_AMP DVDD >1ms TIME Figure 16. Power-Up and Power-Down Sequence with AVDD2 and AVDD_AMP Connected to 12V Maxim Integrated 23 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages UVLO < DVDD < MTP_POR : NO EFFECT DVDD < UVLO : IC RESET DVDD 3.3V CASE 1 NORMAL STARTUP 2.3V MTP_POR 2.3V 1.5V UVLO 1.5V tSTART < 25ms : NORMAL STARTUP DVDD 3.3V MTP_POR 2.3V CASE 2 VERY SLOW STARTUP 2.3V UVLO 1.5V 1.5V tSTART > 25ms : MTP NOT READ GAMMA, VCOM = DEFAULT (5V) Figure 17. DVDD Power Up Requirement RECOMMENDED NOT RECOMMENDED Figure 18. Multiple Small Vias are Recommended over a Single Large Via in the PCB Layout 24 Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Package Information For the latest package outline information and land patterns (footrprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE PACKAGE CODE LAND PATTERN NO. 24 TQFN T2444M+1 21-0139 90-0068 Maxim Integrated 25 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Package Information (continued) For the latest package outline information and land patterns (footrprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 26 Maxim Integrated MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Package Information (continued) For the latest package outline information and land patterns (footrprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Maxim Integrated 27 MAX9679 12-Channel, 10-Bit Programmable Gamma and VCOM Reference Voltages Revision History REVISION NUMBER REVISION DATE 0 7/11 Initial release 1 1/13 Added ramp-up time parameter to Electrical Characteristics table, added new Figure 17 and updated Power Sequencing section and Figures 14–16 2 5/13 Added minimum value and removed the maximum value to the slowest DVDD rampup time parameter DESCRIPTION PAGES CHANGED — 4, 22–24 4 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 28 © 2013 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.