White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED*
256MB – 64Mx32 DDR2 SDRAM UNBUFFERED
FEATURES
DESCRIPTION
200-pin, Small-Outline DIMM (SO-DIMM)
Fast data transfer rates: PC2-5300*, PC2-4200 and
PC2-3200
Utilizes 667*, 533 and 400 Mb/s DDR2 SDRAM
components
The WV3HG64M32EEU is a 64Mx32 Double Data Rate
2 SDRAM memory module based on 512Mb DDR2
SDRAM components. The module consists of four 64Mx8,
in FBGA package mounted on a 200 pin SO-DIMM FR4
substrate.
VCC = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, and 5
Programmable burst: length (4, 8)
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
Row Addr: A0~A13, Column Addr: A0~A9,
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Bank Addr: BA0~BA1
Gold edge contacts
RoHS Compliant
JEDEC Package option
• 200 Pin (SO-DIMM)
• PCB – 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-5300*
PC2-4200
PC2-3200
Clock Speed
333MHz
266MHz
200MHz
CL-tRCD-tRP
5-5-5
4-4-4
3-3-3
Note:
• Consult factory for availability
May 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
PIN CONFIGURATION
PIN NAMES
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
51
DQS2
101
A1
151
NC
1
VREF
2
VSS
52
DM2
102
A0
152
NC
53
VSS
103
153
NC
3
VSS
VCC
4
DQ4
54
VSS
104
154
NC
VCC
5
DQ0
55
DQ18
105
A10/AP
155
VSS
6
DQ5
56
DQ22
106
BA1
156
VSS
7
DQ1
57
DQ19
107
BA0
157
NC
8
VSS
58
DQ23
108
RAS#
158
NC
9
VSS
59
VSS
109
WE#
159
NC
10
DM0
60
VSS
110
CS0#
160
NC
11
DQS0#
61
DQ24
111
161
VSS
VCC
12
VSS
62
DQ28
112
162
VSS
VCC
13
DQS0
63
DQ25
113
CAS#
163
NC
14
DQ6
64
DQ29
114
ODT0
164
NC
65
VSS
115
NC
165
VSS
15
VSS
16
DQ7
66
VSS
116
A13
166
NC
17
DQ2
67
DM3
117
167
NC
VCC
18
VSS
68
DQS3#
118
168
VSS
VCC
19
DQ3
69
NC
119
NC
169
NC
20
DQ12
70
DQS3
120
NC
170
NC
21
VSS
71
VSS
121
VSS
171
VSS
22
DQ13
72
VSS
122
VSS
172
VSS
23
DQ8
73
DQ26
123
NC
173
NC
74
DQ30
124
NC
174
NC
24
VSS
25
DQ9
75
DQ27
125
NC
175
NC
26
DM1
76
DQ31
126
NC
176
NC
27
VSS
77
VSS
127
VSS
177
VSS
28
VSS
78
VSS
128
VSS
178
VSS
29
DQS1#
79
CKE0
129
NC
179
NC
30
CK0
80
NC
130
NC
180
NC
31
DQS1
81
131
NC
181
NC
VCC
32
CK0#
82
132
VSS
182
NC
VCC
83
NC
133
VSS
183
VSS
33
VSS
34
VSS
84
NC
134
NC
184
VSS
35
DQ10
85
NC
135
NC
185
NC
36
DQ14
86
NC
136
NC
186
NC
137
NC
187
VSS
37
DQ11
87
VCC
38
DQ15
88
138
VSS
188
NC
VCC
39
VSS
89
A12
139
VSS
189
NC
40
VSS
90
A11
140
NC
190
VSS
41
VSS
91
A9
141
NC
191
NC
42
VSS
92
A7
142
NC
192
NC
43
DQ16
93
A8
143
NC
193
VSS
44
DQ20
94
A6
144
VSS
194
NC
45
DQ17
95
145
VSS
195
SDA
VCC
46
DQ21
96
146
NC
196
VSS
VCC
47
VSS
97
A5
147
NC
197
SCL
48
VSS
98
A4
148
NC
198
SA0
49
DQS2#
99
A3
149
VSS
199
VCCSPD
50
NC
100
A2
150
VSS
200
SA1
May 2006
Rev. 2
2
SYMBOL
A0-A13
ODT0
CK0, CK0#
CKE0
CS0#
RAS#, CAS#, WE#
BA0, BA1
DM0-DM3
A10/AP
DQ0-DQ31
DQS0-DQS3
DQS0#-DQS3#
SCL
SA0-SA1
SDA
VCC
VREF
VSS
VCCSPD
NC
DESCRIPTION
Address input
On-Die Termination
Differential Clock Inputs
Clock Enable input
Chip select
Command Inputs
Bank Address Inputs
Input Data Mask
Address input/Auto precharge
Data Input/Output
Data Strobe
Serial Clock for Presence Detect
Presence Detect Address Inputs
Serial Presence Detect Data
Power Supply: +1.8V ±0.1V
SSTL_18 reference voltage
Ground
Serial EEPROM Positive Power
Supply
No Connect
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
3
CS0#
DQS0#
DQS0
DM0
DM CS#DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS1#
DQS1
DM1
DM CS# DQS DQS#
DQS2#
DQS2
DM2
DM CS# DQS DQS#
DQS3#
DQS3
DM3
DM CS# DQS DQS#
3
BA0-BA1
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
NOTE: All resistor value, are 22 ohms ± 5% unless otherwise specified.
May 2006
Rev. 2
Serial PD
SCL
BA0-BA1: DDR2 SDRAMs
A0-A13: DDR2 SDRAMs
DDR2 SDRAMs
RAS#:
CAS#:
DDR2 SDRAMs
WE#:
DDR2 SDRAMs
CKE0:
DDR2 SDRAMs
ODT0:
DDR2 SDRAMs
WP A0
A1
SDA
A2
SA0 SA1
VCCSPD
100
Serial PD
VCC
DDR2 SDRAMs
VREF
DDR2 SDRAMs
VSS
DDR2 SDRAMs
3
CK0
CK0#
DDR2 SDRAMs
DDR2 SDRAMs
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
VCC
Voltage on VCC pin relative to VSS
-0.5
2.3
V
VIN, VOUT
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage Temperature
-55
100
˚C
-20
20
µA
CS#, CKE
-20
20
µA
CK, CK#
-20
20
µA
DM
-5
5
µA
-5
5
µA
-8
8
µA
TSTG
IL
IOZ
IVREF
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
Output leakage current; 0V<VIN<VCC; DQs and ODT are
disable
Command/Address,
RAS#, CAS#, WE#
DQ, DQS, DQS#
VREF leakage current; VREF = Valid VREF level
DC OPERATING CONDITIONS
All voltages referenced to VSS
Rating
Parameter
Symbol
Min.
Type
Max.
Units
Notes
Supply Voltage
VCC
1.7
1.8
1.9
V
3
I/O Reference Voltage
VREF
0.49 x VCC
0.50 x VCC
0.51 x VCC
V
1
I/O Termination Voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
2
Notes:
1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. VCCQ of all IC's are tied to VCC.
May 2006
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Parameter
Symbol
Min
Max
Units
Input Capacitance (A0~A13, BA0~BA1, RAS#, CAS#, WE#)
CIN1
8
12
pF
Input Capacitance CKE0, ODT
CIN2
8
12
pF
Input Capacitance CS0#
CIN3
8
12
pF
Input Capacitance (CK0, CK0#)
CIN4
8
12
pF
CIN5 (665)
6.5
7.5
pF
Input Capacitance (DM0 ~ DM3), (DQS0 ~ DQS3)
Input Capacitance (DQ0 ~ DQ31)
CIN5 (534)
6.5
8
pF
COUT1 (665)
6.5
7.5
pF
COUT1 (534)
6.5
8
pF
Notes:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature (Commercial)
TOPER
0° to 85°
°C
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Units
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VCC + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Symbol
Min
Max
Units
Input High (Logic 1) Voltage DDR2-400 & DDR2-533
VIH(AC)
VREF + 0.250
-
V
Input Low (Logic 1) Voltage DDR2-667
VIH(AC)
VREF + 0.200
-
V
Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
VIL(AC)
-
VREF - 0.250
V
Input Low (Logic 0) Voltage DDR2-667
VIL(AC)
-
VREF - 0.200
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
May 2006
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
ICC SPECIFICATION
VCC = +1.8V ± 0.1V
Symbol
ICC0*
ICC1*
ICC2P**
ICC2Q**
ICC2N**
ICC3P**
ICC3N**
ICC4W*
ICC4R*
ICC5**
ICC6**
ICC7*
Proposed Conditions
665
534
403
Units
Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
340
320
320
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as ICC4W
400
380
380
mA
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
32
32
32
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
140
120
120
mA
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
160
140
140
mA
Fast PDN Exit MRS(12) = 0
120
120
120
mA
Slow PDN Exit MRS(12) = 1
48
48
48
mA
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
220
200
200
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
560
480
440
mA
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
580
500
440
mA
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
600
560
560
mA
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
32
32
32
mA
880
880
880
mA
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
May 2006
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
665
PARAMETER
Data
403
SYMBOL
tCK (5)
tCK (4)
tCK (3)
MIN
3,000
3,750
5,000
MAX
8,000
8,000
8,000
MIN
MAX
MIN
MAX
3,750
5,000
8,000
8,000
5,000
5,000
8,000
8,000
UNIT
ps
ps
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.55
0.45
MIN (tCH,
tCL)
-125
-600
0.55
tCK
tHP
0.45
MIN (tCH,
tCL)
-125
-500
0.55
Half clock period
0.45
MIN (tCH,
tCL)
-125
-450
CL = 5
CL = 4
CL = 3
Data Strobe
534
Clock jitter
DQ output access time from CK/CK#
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go nonvalid, per
access
Data valid output window (DVW)
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold time
DQS…DQ skew, DQS to last DQ valid, per group,
per access
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
tJIT
tAC
tHZ
tLZ
tDS
tDH
tDIPW
tQHS
tWPRES
tWPRE
tWPST
Write command to first DQS latching transition
tDQSS
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
Address and control input hold time
tIPW
tIS
tIH
tCCD
tAC MIN
100
225
0.35
125
+450
tAC MAX
tAC MAX
tAC MIN
100
225
0.35
340
125
+500
tAC MAX
tAC MAX
tAC MIN
150
275
0.35
400
ps
125
+600
tAC MAX
tAC MAX
450
ps
ps
ps
ps
ps
ps
tCK
ps
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tQH - tDQSQ
0.35
0.35
-400
0.2
0.2
tQH - tDQSQ
0.35
0.35
-450
0.2
0.2
tQH - tDQSQ
0.35
0.35
-500
0.2
0.2
ns
tCK
tCK
ps
tCK
tCK
tDQSQ
tRPRE
tRPST
+400
240
0.9
0.4
0
0.35
0.4
WL
- 0.25
1.1
0.6
0.6
WL +
0.25
0.6
200
275
2
+450
300
0.9
0.4
0
0.35
0.4
WL
- 0.25
0.6
250
375
2
1.1
0.6
0.6
WL +
0.25
0.9
0.4
0
0.35
0.4
WL
- 0.25
0.6
350
475
2
+500
350
ps
1.1
0.6
tCK
tCK
ps
tCK
tCK
0.6
WL +
0.25
tCK
tCK
ps
ps
tCK
Note:
AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
May 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
AC TIMING PARAMETERS (cont'd)
Power-Down
ODT
Self Refresh
Command and Address
AC CHARACTERISTICS
665
PARAMETER
SYMBOL
MIN
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tRC
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
tDAL
tWTR
tRP
tRPA
tMRD
55
7.5
15
37.5
45
7.5
15
tWR + tRP
7.5
15
tRP+tCK
2
tIS + tCK
+ tIH
tDELAY
REFRESH to Active of Refresh to Refresh command
interfal
tRFC
Average periodic refresh interval
tREFI
105
534
MAX
37.5
70,000
MIN
60
7.5
15
37.5
45
7.5
15
tWR + tRP
7.5
15
tRP+tCK
2
tIS + tCK
+ tIH
70,000
105
7.8
403
MAX
37.5
70,000
70,000
MIN
65
7.5
15
37.5
45
7.5
15
tWR + tRP
10
15
tRP+tCK
2
tIS + tCK
+ tIH
105
7.8
tIS
tIS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
70,000
ns
7.8
µs
Exit self refresh to READ command
tXSRD
Exit self refresh timing reference
tISXR
tIS
ODT turn-on delay
tAOND
2
2
2
2
2
2
tCK
ODT turn-on
tAON
tAC (MIN)
tAC (MAX)
+ 1000
tAC (MIN)
tAC (MAX)
+ 1000
tAC (MIN)
tAC (MAX)
+ 1000
ps
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC (MIN)
tAC (MIN)
tAC (MIN)
+ 2000
ODT turn-off (power-down mode)
tAOFPD
tAC (MIN)
+ 2000
tAC (MAX)
+ 600
2 x tCK +
tAC (MAX)
+ 1000
2.5 x
tCK + tAC
(MAX) +
1000
ps
tAONPD
tAC (MAX)
+ 600
2 x tCK +
tAC (MAX)
+ 1000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
ODT turn-on (power-down mode)
tAC (MAX)
+ 600
2 x tCK +
tAC (MAX)
+ 1000
2.5 x
tCK + tAC
(MAX) +
1000
tXSNR
tRFC (MIN)
+ 10
200
37.5
70,000
UNIT
tRFC (MIN)
+ 10
200
Exit self refresh to non-READ command
tRFC (MIN)
+ 10
200
MAX
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
ns
tCK
ps
ps
ps
ODT to power-down entry latency
tANPD
3
3
3
tCK
ODT power-down exit latency
tAXPD
8
8
8
tCK
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
A Exit precharge power-down to any non-READ
command.
CKE minimum high/low time
tXARD
2
2
2
tCK
tXARDS
7 - AL
6 - AL
6 - AL
tCK
tXP
2
2
2
tCK
tCKE
3
3
3
tCK
Note:
AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
May 2006
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
ORDERING INFORMATION FOR D4
Part Number
Clock/Data Rate
Frequency
CAS Latency
tRCD
tRP
Height**
WV3HG64M32EEU665D4xxG*
333MHz/667Mb/s
5
5
5
30.00mm (1.181") TYP
WV3HG64M32EEU534D4xxG
266MHz/533Mb/s
4
4
4
30.00mm (1.181") TYP
WV3HG64M32EEU403D4xxG
200MHz/400Mb/s
3
3
3
30.00mm (1.181") TYP
* Consult Factory for availability
NOTES:
• RoHS product. ("G" = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D4
FRONT VIEW
3.80 (0.150)
MAX
67.75 (2.667)
67.45 (2.656)
4.10(0.161) (2X)
3.90(0.154)
30.15 (1.187)
29.85 (1.175)
1.80 (0.071)
(2X)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
2.15 (0.085)
1.10 (0.043)
0.90 (0.035)
1.00 (0.039)
TYP
PIN 1
0.45 (0.018)
TYP
0.60 (0.024)
TYP
PIN 199
63.60 (2.504)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
47.40 (1.866)
TYP
PIN 2
11.40 (0.449)
TYP
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2006
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 64M 32 E E U xxx D4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 200 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
May 2006
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M32EEU-D4
ADVANCED
Document Title
256MB – 64Mx32 DDR2 SDRAM UNBUFFERED
DRAM DIE OPTIONS:
• SAMSUNG: C-Die, will move to E-Die Q2'06
• MICRON: U37Y: B-Die
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
3-06
Advanced
Rev 1
1.1 Added row, column, and bank address
3-23-06
Advanced
Rev 2
2.1 Correction on component used, (512Mb)
5-06
Advanced
2.2 Added VCCQ update
2.3 Added "x" to part number to indicate industrial temp option
2.4 Added "x" to part numbering guide to indicate industrial
temp option
2.5 Added die rev info
May 2006
Rev. 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com