White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED* 2GB – 2x128Mx72 DDR2 SDRAM UNBUFFERED DIMM FEATURES DESCRIPTION Unbuffered 240-pin, dual in-line memory module Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4300 and PC2-3200 VCC = VCCQ = 1.8V The WV3HG2128M72EEU is a 2x128Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of eighteen 128Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 240-pin DIMM FR4 substrate. VCCSPD = +1.7V to +3.6V Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, 5* and 6* Adjustable data-output drive strength On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM Auto & self refresh (64ms/8,192 cycle refresh) Gold edge contacts Dual Rank RoHS compliant Package option * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • Vendor source control options • Industrial temperature option • Parity function • 240 Pin DIMM • 30.00mm (1.181") TYP OPERATING FREQUENCIES PC2-6400* PC2-5300* PC2-4300 PC2-3200 Clock Speed 400MHz 333MHz 266MHz 200MHz CL-tRCD-tRP 6-6-6 5-5-5 4-4-4 3-3-3 * Consult factory for availability August 2006 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS VCC CKE0 VCC BA2 NC VCC A11 A7 VCC A5 August 2006 Rev. 1 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol A4 VCC A2 VCC VSS VSS VCC NC VCC A10/AP BA0 VCC WE# CAS# VCC CS1# ODT1 VCC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS VCC CKE1 VCC NC NC VCC A12 A9 VCC A8 A6 PIN NAMES Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VCC A3 A1 VCC CK0 CK0# VCC A0 VCC BA1 VCC RAS# CS0# VCC ODT0 A13 VCC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2# VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VCCSPD SA0 SA1 Pin Name A0-A13 BA0,BA2 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# DM0-DM8 ODT0, ODT1 CK0,CK0#-CK2,CK2# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# SA0-SA2 SDA SCL VCC VSS VREF VCCSPD NC 2 Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement Data masks On-die termination controls Clock Inputs Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable SPD address SPD Data Input/Output SPD Clock Input Power Supply Ground Power Supply Reference SPD Power Spare pins, No connect White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DM/ RDQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQS# DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM/ RDQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1# DM1 CS# DQS DQS# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS CS# DQS DQS# CS# DQS DQS# CS# DQS DQS# CS# DQS DQS# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5# DM5 DM/ RDQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS# DQS DQS# DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM/ RDQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DQS2# DM2 CS# DQS DQS# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6# DM6 DM/ RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS# DQS DQS# DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM/ RDQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS3 DQS3# DM3 CS# DQS DQS# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7# DM7 DM/ RDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS8 DQS8# DM8 DM/ RDQS CS# DQS DQS# VCCSPD DM/ RDQS CS# DQS DQS# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Serical PD SCL Serial PD SDA VCC\VCCQ WP DDR2 SDRAMs VREF DDR2 SDRAMs VSS DDR2 SDRAMs A0 A1 A2 SA0 SA1 SA2 *Clock Wiring CS0# CS0#: DDR 2 SDRAMs CS1# CS1#: DDR 2 SDRAMs BA0-BA2 A0-A13 BA0-BA2: DDR 2 SDRAMs A0-A13: DDR 2 SDRAMs RAS# RAS#: DDR 2 SDRAMs CAS# CAS#: DDR 2 SDRAMs WE# WE#: DDR 2 SDRAMs CKE0 CKE0: DDR 2 SDRAMs CKE1 CKE1: DDR 2 SDRAMs ODT0 ODT0: DDR 2 SDRAMs ODT1 ODT1: DDR 2 SDRAMs Clock Input *CK0/CK0# *CK1/CK1# *CK2/CK2# DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs *Wire per Clock Loading Table/Wiring Diagrams Notes: 1. DQ, DM, DQS/DQS# resistors: 5.1 Ohms +/-5% 2. BAx, Ax RAS#, CAS#, WE# resistors: 5.1 Ohms +/- 5% NOTE: All resistor values are 22 ohms unless otherwise specified. August 2006 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Symbol Min Typical Max Unit Notes Supply Voltage VCC 1.7 1.8 1.9 V 3 I/O Reference Voltage VREF 0.49 x VCC 0.50 x VCC 0.51 x VCC V 1 I/O Termination Voltage VTT VREF-0.04 VREF VREF+0.04 V 2 VCCSPD 1.7 - 3.6 V SPD Supply Voltage Notes: 1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units VCC Voltage on VCC pin relative to VSS -0.5 2.3 V VIN, VOUT Voltage on any pin relative to VSS -0.5 2.3 V Storage Temperature -55 100 °C Command/Address, RAS#, CAS#, WE#, -90 90 µA CS#, CKE -45 45 µA CK, CK# -30 30 µA DM -10 10 µA DQ, DQS, DQS# -10 10 µA -36 36 µA TSTG IL IOZ IVREF Input leakage current; Any input 0V<VIN<VCC; VREF input 0V,VIN,0.95V; Other pins not under test = 0V Output leakage current; 0V<VIN<VCC; DQs and ODT are disable VREF leakage current; VREF = Valid VREF level INPUT/OUTPUT CAPACITANCE TA = 25°C, f = 100MHz Parameter Input Capacitance (A0-A13, BA0~BA2, RAS#, CAS#, WE#) Input Capacitance (CKE0, CKE1), (ODT0, ODT1) Input Capacitance (CS0#, CS1#)) Input Capacitance (CK0, CK0#-CK2, CK2#) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (665) Input Capacitance (DQS0~DQS8), (DM0-DM8) CIN5 (534, 403) COUT (665) COUT (534, 403) Input Capacitance (DQ0~DQ63), (CB0~CB7) August 2006 Rev. 1 4 Min 22 13 13 10 9 9 9 9 Max 40 22 22 16 11 12 11 12 Unit pF pF pF pF pF pF pF pF White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED OPERATING TEMPERATURE CONDITION Parameter Symbol Rating Units Notes Operating Temperature (Commercial) TOPER 0ºC to 85ºC ºC 1, 2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2. 2. At 0 - 85ºC, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Units Input High (Logic 1) Voltage VIH(DC) VREF + 0.125 VCC + 0.300 V Input Low (Logic 0) Voltage VIL(DC) -0.300 VREF - 0.125 V Symbol Min Max Units AC Input Low (Logic 1) Voltage DDR2-400 & DDR2-533 VIL(AC) VREF+ 0.250 V AC Input High (Logic 1) Voltage DDR2-667 VIH(AC) VREF+ 0.200 V AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 VIL(AC) VREF - 0.250 V AC Input Low (Logic 0) Voltage DDR2-667 VIL(AC) VREF - 0.200 V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter August 2006 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED DDR2 ICC SPECIFICATIONS AND CONDITIONS DDR2 SDRAM components only Symbol ICC0* ICC1* ICC2P* ICC2Q** ICC2N** ICC3P** ICC3N** ICC4W* ICC4R* ICC5B** ICC6** ICC7* Proposed Conditions 806 665 553 403 Units Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 918 873 828 mA Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W TBD 1,008 963 918 mA Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 216 216 216 mA Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 720 630 630 mA Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 810 720 720 mA Fast PDN Exit MRS(12) = 0 TBD 540 450 450 mA Slow PDN Exit MRS(12) = 1 TBD 216 216 216 mA Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 900 810 810 mA Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 1,503 1,278 1,143 mA Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W TBD 1,503 1,278 1,143 mA Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 3,960 3,870 3,780 mA Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING TBD 180 180 180 mA TBD 2,808 2,628 2,448 mA Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Normal Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING. Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different. *: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition. August 2006 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED AC TIMING PARAMETERS & SPECIFICATIONS AC CHARACTERISTICS 806 PARAMETER SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) MIN MAX TBD TBD TBD TBD TBD TBD TBD CK high-level width tCH CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ…DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising … setup time DQS falling edge from CK rising … hold time DQS…DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Clock Data 534 403 MIN MAX MIN MAX MIN MAX TBD 3,000 3,750 5,000 8,000 8,000 8,000 3,750 5,000 8,000 8,000 5,000 5,000 8,000 8,000 UNIT ps ps ps ps TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCL tHP tJIT tAC TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 TBD TBD MIN(tCH,tCL) TBD TBD TBD TBD -125 -450 125 +600 tCK ps ps ps tHZ TBD TBD tAC(MAX) ps tLZ TBD TBD tAC(MIN) tAC(MAX) ps tDS TBD TBD 100 100 150 tDH TBD TBD 225 225 275 tDIPW TBD TBD 0.35 0.35 0.35 tQHS TBD TBD tQH TBD TBD tHP - tQHS tHP - tQHS tHP - tQHS ps tDVW tDQSH tDQSL tDQSCK tDSS TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD tQH - tDQSQ 0.35 0.35 -400 0.2 tQH - tDQSQ 0.35 0.35 -450 0.2 tQH - tDQSQ 0.35 0.35 -500 0.2 ns tCK tCK ps tCK tDSH TBD TBD TBD TBD tRPRE tRPST TBD TBD TBD TBD tWPRES tWPRE tWPST TBD TBD TBD TBD TBD TBD tDQSS TBD TBD tIPW TBD TBD Address and control input setup time tIS TBD TBD Address and control input hold time tIH TBD TBD Address and control input hold time tCCD TBD TBD Clock cycle time Data Strobe 665 CL = 6 CL = 5 CL = 4 CL = 3 Address and control input pulse width for each input tDQSQ MIN(tCH,tCL) 125 +450 -125 -500 tAC(MAX) tAC(MAX) 0.2 tAC(MIN) tAC(MAX) +450 0.2 1.1 0.6 0.6 WL+ 0.25 200 275 2 -125 -600 tAC(MIN) 400 240 0.9 0.4 0 0.35 0.4 WL0.25 0.6 125 +500 tAC(MAX) 340 +400 MIN(tCH,tCL) 450 250 375 2 +500 0.2 300 0.9 0.4 0 0.35 0.4 WL0.25 0.6 tCK 1.1 0.6 0.6 WL+ 0.25 0.9 0.4 0 0.35 0.4 WL0.25 0.6 250 475 2 ps tCK 350 ps 1.1 0.6 tCK tCK ps tCK tCK 0.6 WL+ 0.25 tCK tCK ps ps tCK * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page August 2006 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED AC TIMING PARAMETERS (cont'd) AC CHARACTERISTICS Self Refresh Command and Address PARAMETER ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty ODT 665 SYMBOL MIN MAX MIN tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL TBD TBD TBD TBD TBD TBD TBD TBD 55 7.5 15 37.5 40 7.5 15 tWR+tRP TBD TBD TBD TBD TBD TBD TBD TBD tWTR tRP tRPA tMRD TBD TBD TBD TBD TBD TBD TBD TBD tDELAY TBD TBD TBD TBD REFRESH to Active of Refresh to Refresh command interfal tRFC Average periodic refresh interval tREFI TBD TBD Exit self refresh to non-READ command tXSNR TBD TBD 534 MAX MIN 37.5 70,000 55 7.5 15 37.5 40 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK tIH 127.5 403 MAX MIN 37.5 70,000 55 7.5 15 37.5 40 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK tIH 70,000 127.5 7.8 MAX UNIT 37.5 70,000 ns ns ns ns ns ns ns ns 7.5 15 tRP+tCK 2 tIS+tCK tIH 70,000 127.5 7.8 tRFC(MIN) +10 200 tRFC(MIN) +10 200 tIS tIS ns ns ns tCK ns 70,000 ns 7.8 µs Exit self refresh to READ command tXSRD TBD TBD tRFC(MIN) +10 200 Exit self refresh timing reference tISXR TBD TBD tIS ODT turn-on delay tAOND TBD TBD 2 2 2 2 2 2 tCK ODT turn-on tAON TBD TBD tAC(MIN) tAC(MAX) +1000 tAC(MIN) tAC(MAX) +1000 tAC(MIN) tAC(MAX) +1000 ps ODT turn-off delay tAOFD TBD TBD 2.5 2.5 2.5 2.5 2.5 2.5 tCK tAOF TBD TBD tAC(MIN) tAC(MIN) tAC(MIN) +2000 TBD TBD tAC(MAX) +600 2 x tCK+ tAC(MAX) +1000 2.5 x tCK+ tAC(MAX) +1000 ps TBD tAC(MAX) +600 2 x tCK+ tAC(MAX) +1000 2.5 x tCK+ tAC(MAX) +1000 tAC(MIN) TBD tAC(MAX) +600 2 x tCK+ tAC(MAX) +1000 2.5 x tCK+ tAC(MAX) +1000 ODT turn-off Power-Down 806 ODT turn-on (power-down mode) tAONPD ODT turn-off (power-down mode) tAOFPD tAC(MIN) +2000 tAC(MIN) +2000 tAC(MIN) +2000 tAC(MIN) +2000 tAC(MIN) +2000 ns tCK ps ps ps ODT to power-down entry latency tANPD TBD TBD 3 3 3 tCK ODT power-down exit latency tAXPD TBD TBD 8 8 8 tCK Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any nonREAD command. CKE minimum high/low time tXARD TBD TBD 2 2 2 tCK tXARDS TBD TBD 7-AL 6-AL 6-AL tCK tXP TBD TBD 2 2 2 tCK tCKE TBD TBD 3 3 3 tCK * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. August 2006 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED ORDERING INFORMATION FOR D6 Part Number Speed/Data Rate Frequency CAS Latency tRCD tRP Height** WV3HG2128M72EEU806D6xxG* WV3HG2128M72EEU665D6xxG* WV3HG2128M72EEU534D6xxG 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 6 5 4 6 5 4 6 5 4 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP WV3HG2128M72EEU403D6xxG 200MHz/400Mb/s 3 3 3 30.00mm (1.181") TYP * Contact factory for availability NOTES: • RoHS compliant product. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D6 FRONT VIEW 4.00 (0.158) MAX 133.50 (5.256) 133.20 (5.244) 3.00 (0.118) (4X) 4.00 (0.158) (4X) 30.50 (1.201) 29.85 (1.175) 17.80 (0.700) TYP. 5.175 (0.204) PIN 1 (2X) 1.0 (0.039) TYP. 0.80 (0.032) TYP. 10.00 (0.394) TYP. 1.50 (0.059) 1.37 (0.054) 1.17 (0.046) PIN 120 123.0 (4.843) TYP. BACK VIEW PIN 240 PIN 121 5.0 (0.197) TYP. 63.0 (2.480) TYP. 55.0 (2.165) TYP. ** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) August 2006 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED PART NUMBERING GUIDE WV 3 H G 2 128M 72 E E U xxx D6 x x G WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH (x8) 1.8V UNBUFFERED SPEED (Mb/s) PACKAGE 240 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT August 2006 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG2128M72EEU-D6 ADVANCED Document Title 2GB – 2x128Mx72 DDR2 SDRAM UNBUFFERED DRAM Die Options: • SAMSUNG: B-Die • MICRON: U28A: A-Die, move to U38Z: D-Die Q4'06 and U48B: E-Die Q2'07 Revision History Rev # History Release Date Status Rev 0 Created June 2006 Concept Rev 1 1.0 Moved to Advanced August 2006 Advanced August 2006 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com