ISSUED DATE :2005/02/18 REVISED DATE : G P 3 4 11 9 LOW POWER AUDIO AMPLIFIER Description The GP34119 is a low power audio amplifier integrated circuit intended (primarily) for telephone applications, such as in speakerphones. It provides differential speaker outputs to maximize output swing at low supply voltages (2.0V minimum). Coupling capacitors to the speaker are not required. Open loop gain is 80 dB, and the closed loop gain is set with two external resistors. A Chip Disable pin permits powering down and/or muting the input signal. Features Wide Operating Supply Voltage Range (2.0V to 16V), Allows Telephone Line Powered Applications Low Quiescent Supply Current (2.7mA Typ) for Battery Powered Applications Chip Disable Input to Power Down the IC Low Power-Down Quiescent Current (65uA Typ) Drives a Wide Range of Speaker Loads (8.0 Output Power Exceeds 250 mW with 32 and Up) Speaker Low Total Harmonic Distortion (0.5% Typ) Gain Adjustable from <0 dB to >46 dB for Voice Band Requires Few External Components Package Dimensions D E GAUGE PLANE c A REF. SEATING PLANE b Z L Z SECTION Z - Z b e DIP-8 A A1 A2 b b1 b2 b3 c Millimeter Min. Max. 0.381 2.921 0.356 0.356 1.143 0.762 0.203 0.5334 4.953 0.559 0.508 1.778 1.143 0.356 REF. Millimeter Min. Max. c1 D E E1 e HE L 0.203 0.279 9.017 10.16 6.096 7.112 7.620 8.255 2.540 BSC 10.92 2.921 3.810 Block Diagram and Simplified Application & Pin Configuration 1/8 ISSUED DATE :2005/02/18 REVISED DATE : Maximum Ratings Rating Value -1.0 to +18 ±250 -1.0, VCC+1.0 -1.0, VCC+1.0 -55, +140 Supply Voltage Maximum Output Current at VO1, VO2 Maximum Voltage @ Vin, FC1, FC2, CD Applied Output Voltage to VO1, VO2 when disabled Junction Temperature Unit Vdc mA Vdc Note: ESD data available upon request. Recommended Operating Conditions Characteristics Supply Voltage Voltage @ CD (Pin 1) Load Impedance Peak Load Current Differential Gain (5.0kHz Bandwidth) Ambient Temperature Electrical Characteristics (TA=25 Characteristics Symbol Amplifiers (AC Characteristics) AC Input Resistance ri Open Loop Gain AVOL1 Close Loop Gain AV2 Gain Bandwidth Product GBW POut3 Output Power POut6 POut12 Total Harmonic Distortion (f=1kHz) Power Supply Rejection (VCC=6V, VCC=3V) THD Min +2.0 0 8.0 0 -20 Max +16 VCC ±200 46 +70 Unit Vdc mA dB unless otherwise noted.) Test Conditions Min Typ. Max. Unit 80 -0.35 55 250 400 >30 0 1.5 - +0.35 - M dB dB MHz 50 - 0.5 0.5 0.6 12 52 >70 1.0 - 1.0 - 1.15 2.65 5.65 VCC-1 0.16 1.25 - VCC =6V, Rf=75k , RL=32 -30 0 +30 mV Vin(VCC=6V) 100 18 -100 -200 220 40 nA @ Vin Amplifier #1, f<100Hz Amplifier #2, VCC=6V, f=1kHz, RL=32 VCC= 3V, RL= 16 , THD VCC= 6V, RL= 32 , THD VCC=12V, RL=100 , THD 10% 10% 10% VCC= 6V, RL=32 , Pout=125mW VCC 3V, RL= 8 , Pout= 20mW VCC 12V, RL=32 , Pout=200mW C1= , C2=0.01uF PSRR C1=0.1uF, C2=0, f=1kHz C1=1.0uF, C2=5.0uF, f=1kHz Differential Muting GMT Amplifiers (DC Characteristics) VO(3) Output DC Level VO(6) VO(12) VOH Output Level VOL Output DC Offset Voltage VO (VO1-VO2) Input Bias Current IIB Equivalent Resistance Symbol VCC VCD RL IL AVD TA VCC=6V, 1kHz f 20kHz, CD=2V VO1, VO2, VCC=3V, RL=16 , (Rf=75k) VCC= 6V VCC=12V High Iout=-75mA, 2V VCC Low Iout= 75mA, 2V VCC RFC1 RFC2 FC1(VCC =6V) FC2(VCC =6V) VIL VIH RCD Low High 16V 16V 150 25 mW % dB dB Vdc Vdc k Chip Disable(Pin1) Input Voltage Input Resistance Power Supply Power Supply Current VCC= VCD=16V ICC3 VCC= 3V, RL= , CD=0.8V ICC16 VCC=16V, RL= , CD=0.8V ICCD VCC= 3V, RL= , CD=2.0V 2.0 50 90 0.8 175 - 2.7 3.3 65 4.0 5.0 100 - Vdc k mA mA uA Note: Currents into a pin are positive, currents out of a pin are negative. 2/8 ISSUED DATE :2005/02/18 REVISED DATE : Pin Function Description Symbol Pin Description CD 1 Chip Disable-Digital input. A Logic “0” (<0.8V) sets normal operation. A Logic “1” ( power down mode. Input impedance is nominally 90k . FC2 2 A capacitor at this pin increases power supply rejection, and affects turn-on time. This pin can be left open if the capacitor at FC1 is sufficient. FC1 3 Analog ground for the amplifiers. A 1.0uF capacitor at this pin (with a 5.0uF capacitor at Pin 2) provides (typically) 52dB of power supply rejection. Turn-on time of the circuit is affected by the capacitor on this pin. This pin can be used as an alternate input. Vin 4 Amplifier input. This input capacitor and resistor set low frequency rolloff and input impedance. The feedback resistor is connected to this pin and V O1. VO1 VCC GND 5 6 7 Amplifier Output #1. The dc level is VO2 8 Amplifier Output #2. This signal is equal in amplitude, but 180° out-of-phase with that at VO1. The dc level is (VCC – 0.7)/2. 2V) sets the (VCC – 0.7)/2. DC supply voltage (+2V to +16V) is applied to this pin. Ground pin for the entire circuit. Typical Temperature Performance (-20 < TA < +70 ) Function Typical Change ±40 Input Bias Current (@ Vin) Total Harmonic Distortion(VCC=6V, RL=32 Pout=125mW, f=1kHz) Power Supply Current (VCC=3V, RL= , CD=0V) (VCC=3V, RL= , CD=2V) Units pA/ +0.003 %/ -0.25 -0.03 uA/ Design Guidelines General The GPC34119 is a low power audio amplifier capable of low voltage operation (VCC = 2.0 V minimum) such as that encountered in line-powered speakerphones. The circuit provides a differential output (VO1-VO2) to the speaker to maximize the available voltage swing at low voltages. The differential gain is set by two external resistors. Pins FC1 and FC2 allow controlling the amount of power supply and noise rejection, as well as providing alternate inputs to the amplifiers. The CD pin permits powering down the IC for muting purposes and to conserve power. Amplifiers Referring to the block diagram, the internal configuration consists of two identical operational amplifiers. Amplifier # 1 has an open loop gain of 80 dB (at f 100 Hz), and the closed loop gain is set by external resistor Rf and Ri. The amplifier is unity gain stable, and has a unity gain frequency of approximately 1.5 MHz. In order to adequately cover the telephone voice band (300 Hz to 3400 Hz), a maximum closed loop gain of 46 is recommended. Amplifier #2 is internally set to a gain of-1.0(0dB). The outputs of both amplifiers are capable of sourcing and sinking a peak current of 200 mA. The outputs can typically swing to within 0.4 V above ground, and to with 1.3 V below VCC, at the maximum current. See Figures 17 and 18 for V OH and V OL curves. The output dc offset voltage (VO1-VO2) is primarily a function of the feedback resistor (Rf), and secondarily due to the amplifiers' input offset voltages. The input offset voltage of the two amplifiers swill generally be similar for a particular IC, and therefore nearly cancel each other at the outputs. Amplifier #1's bias current, however, flows out of Vin (Pin 4) and through Rf, forcing V01 to shift negative by an amount equal to [Rf x IIB]. V O2 is shifted positive an equal amount. The output offset voltage, specified in the Electrical Characteristics, is measured with the feedback resistor shown in the Typical Application Circuit, and therefore takes into account the bias current as well as internal offset voltages of the amplifiers. The bias current is constant with respect to VCC. FC1 and FC2 Power supply rejection is provided by the capacitors (C1 and C2 in the Typical Application Circuit) at FC1 and FC2. C2 is somewhat dominant at low frequencies, while C1 is dominant at high frequencies, as shown in the graphs of Figures 4 to 7. The required values of C1 and C2 depend on the conditions of each application. A line powered speakerphone, for example, will require more filtering than a circuit powered by a well regulated power supply. The amount of rejection is a function of the capacitors, and the equivalent impedance looking into FC1 and FC2 (listed in the Electrical Characteristics as R FC1 and R FC2). In addition to providing filtering, C1 and C2 also affect the turn-on time of the circuit at power-up, since the two capacitors must charge up through the internal 50 k and 125 k resistors. The graph of Figure 1 indicates the turn-on time upon application of VCC of + 6.0 V. The turn-on time is 60% longer for VCC = 3.0 V, and 20% less for VCC = 9.0V. Turn-off time is < 10 us upon removal of VCC. 3/8 ISSUED DATE :2005/02/18 REVISED DATE : Chip Disable The Chip Disable (Pin 1) can be used to power down the IC to conserve power, or for muting, or both. When at a Logic "0" (0 V to 0.8 V), the GP34119 is enabled for normal operation. When Pin 1 is at a Logic "1" (2.0 V to VCC V), the IC is disabled. If Pin 1 is open, that is equivalent to a Logic "0", although good design practice dictates that an input should never be left open. Input impedance at Pin 1 is a nominal 90 k . The power supply current (when disabled) is shown in Figure 19. Muting, defined as the change in differential gain from normal operation to muted operation, is in excess of 70 dB. The turn-off time of the audio output, from the application of the CD signal, is <2.0 us, and turn on-time is 12 ms-15 ms. Both times are independent of C1,C2, and VCC. When the GP34119 is disabled, the voltages at FC1 and FC2 do not change as they are powered from VCC. The outputs, VO1 and VO2, change to a high impedance condition, removing the signal from the speaker. If signals from other sources are to be applied to the outputs (while disabled), they must be within the range of V CC and Ground. Power Dissipation Figures 8 to 10 indicate the device dissipation (within the IC) for various combinations of VCC, RL, and load power. The maximum power which can safely be dissipated within the GP34119 is found from the following equation: PD = (140 temperature; and JA is the package thermal resistance (100 -TA)/ JA where TA is the ambient /W for the standard DIP package.) The power dissipated within the GP34119, in a given application, is found from the following equation: 2 PD = (VCC x ICC) + (IRMS x VCC) – (RL x IRMS ) where ICC is obtained from Figure 19; and IRMS is the RMS current at the load; and RL is the load resistance. Figures 8 to 10, along with Figures 11 to 13 (distortion curves), and a peak working load current of 200 mA, define the operating range for the GP34119. The operating range is further defined in terms of allowable load power in Figure 14 for loads of 8.0 , 16 and 32 . The left (ascending) portion of each of the three curves is defined by the power level at which 10% distortion occurs. The center flat portion of each curve is defined by the maximum output current capability of the GP34119. The right (descending) portion of each curve is defined by the maximum internal power dissipation of the IC at 25 . At higher ambient temperatures, the maximum load power must be reduced according to the above equations. Operating the device beyond the current and junction temperature limits will degrade long term reliability. Layout Considerations Normally a snubber is not needed at the output of the GP34119, unlike many other audio amplifiers. However, the PC board layout, stray capacitances, and the manner in which the speaker wires are configured, may dictate otherwise. Generally, the speaker wires should be twisted tightly, and not more than a few inches in length. Characteristics Curve Fig 1. Turn-On Time versus C1, C2 at Power-On Fig 2. Amplifier #1 Open Loop Gain and Phase 4/8 ISSUED DATE :2005/02/18 REVISED DATE : (C2 = 10 F) Fig 3. Differential Gain versus Frequency (C2 = 5.0 F) Fig 5. Power Supply Rejection versus Frequency Fig 4. Power Supply Rejection versus Frequency (C2 = 1.0 F) Fig 6. Power Supply Rejection versus Frequency (C2 = 0) Fig 7. Power Supply Rejection versus Frequency Fig 8. Device Dissipation, 8.0 Load 5/8 ISSUED DATE :2005/02/18 REVISED DATE : Fig 9. Device Dissipation, 16 Load (f = 1.0kHz, AVD = 34 dB) Fig 11. Distortion versus Power Fig 10. Device Dissipation, 32 Load (f = 3.0kHz, AVD = 34 dB) Fig 12. Distortion versus Power (f = 1, 3.0kHz, AVD = 34 dB) Fig 13. Distortion versus Power Fig 14. Maximum Allowable Load Power 6/8 ISSUED DATE :2005/02/18 REVISED DATE : Fig 15. Small Signal Response Fig 17. VCC-VOH @ VO1, VO2 versus Load Current Fig 19. Power Supply Current Fig 16. Large Signal Response Fig 18. VOL @ VO1, VO2 versus Load Current Fig 20. Input Characteristics @ CD (Pin 1) 7/8 ISSUED DATE :2005/02/18 REVISED DATE : Note: If VCC and VEE are not symmetrical about ground then FC1 mist be connected through a capacitor to ground as shown on the front page. Fig 21. Audio Amplifier with High Input Impedance Fig 22. Split Supply Operation Fig 23. Audio Amplifier with Bass Suppression Fig 24. Frequency Response of Fig 23 Fig 25. Audio Amplifier with Bandpass Fig 26. Frequency Response of Fig 25 portant Notice: All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM. GTM reserves the right to make changes to its products without notice. GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems. GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. Head Office And Factory: Taiwan: No. 17-1 Tatung Rd. Fu Kou Hsin-Chu Industrial Park, Hsin-Chu, Taiwan, R. O. C. TEL : 886-3-597-7061 FAX : 886-3-597-9220, 597-0785 China: (201203) No.255, Jang-Jiang Tsai-Lueng RD. , Pu-Dung-Hsin District, Shang-Hai City, China TEL : 86-21-5895-7671 ~ 4 FAX : 86-21-38950165 8/8