19-2557; Rev 0; 7/02 14-Bit, 260Msps High-Dynamic Performance DAC ♦ 260Msps Output Update Rate ♦ Excellent SFDR Performance To Nyquist (-12dBFS) At 19.4MHz Output = 77dBc At 51.6MHz Output = 76dBc ♦ Industry-Leading IMD Performance For 4 Tones (-15dBFS) At 18MHz Output = 86dBc At 31MHz Output = 84dBc ♦ Low Noise Performance SNR = 160dB/Hz at fOUT = 19.4MHz ♦ On-Chip 1.2V Bandgap Reference ♦ 20mA Full-Scale Current ♦ Single 5V Supply ♦ Differential LVPECL-Compatible Digital Inputs ♦ 48-Lead QFN-EP Package Ordering Information PART MAX5195EGM PIN-PACKAGE 48 QFN-EP* *EP = Exposed paddle. Base Stations: Single-/Multi-Carrier UMTS, GSM D13P D13N REFIN 37 38 39 40 41 42 43 D10P D10N D11P D11N D12P D12N 44 45 46 D9N DVCC DGND 36 2 35 3 34 D7N D7P CLKP 4 33 5 32 AMPOUT AVCC AVCC 31 OUTP CLKN D6N D6P 7 30 8 29 OUTN AVCC 9 28 D5N D5P 10 27 11 26 D4N 12 25 6 RSET AVCC AGND AGND REFOUT AVCC 24 23 22 21 20 18 17 16 DVCC DGND D2N D2P 15 MAX5195 14 Instrumentation 1 13 Automated Test Equipment D9P D8N D8P D4P Broadband Cable Systems 47 Digital-Signal Synthesis 48 TOP VIEW Direct IF Synthesis D3N D3P LMDS, MMDS, Point-to-Point Microwave Pin Configuration D1N D1P D0N D0P T.P. Applications TEMP RANGE -40°C to +85°C 19 The MAX5195 is available in a 48-lead QFN package with exposed paddle and is specified for the extended industrial temperature range (-40°C to +85°C). Features QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5195 General Description The MAX5195 is an advanced, 14-bit, 260Msps digitalto-analog converter (DAC) designed to meet the demanding performance requirements of signal synthesis applications found in wireless base stations and other communication systems. Operating from a single 5V supply, this DAC offers exceptional dynamic performance such as 77dBc spurious-free dynamic range (SFDR) at fOUT = 19.4MHz, while supporting update rates beyond 260Msps. The MAX5195 current-source array architecture supports a full-scale current range of 10mA to 20mA, which allows a differential output voltage swing between 0.5VP-P and 1VP-P. The MAX5195 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy and low-noise performance. Additionally, a separate reference input pin allows the user to apply an external reference source for optimum flexibility. The digital and clock inputs of the MAX5195 are designed for differential LVPECL-compatible voltage levels. MAX5195 14-Bit, 260Msps High-Dynamic Performance DAC ABSOLUTE MAXIMUM RATINGS AVCC, DVCC to AGND..............................................-0.3V to +6V AVCC, DVCC to DGND..............................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V D0N–D013, D0P–D13P, T.P. to DGND .................-0.3V to +3.6V OUTP, OUTN, AMPOUT, REFOUT, CLKP, CLKN, RSET to AGND..........................................-0.3V to +6V REFIN Voltage Range...............................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C) 48-Pin QFN-EP (thermal resistance θJA = +37°C/W)....2162W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVCC = DVCC = 5V, AGND = DGND = 0, external reference VREFIN = 1.196V, RT = 27.4Ω referenced to AVCC, VOUT = 1VP-P, RSET = 3.83kΩ, fCLK = 156MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 14 Integral Nonlinearity INL Best-straight-line fit Differential Nonlinearity DNL TA = +25°C Offset Error VOS Full-Scale Gain Error (Note 2) GE LSB ±2 LSB ±1.5 +3.0 LSB (Note 1) 0.05 0.1 %FS Internal reference 2.5 6 External reference 1.6 4 -3.3 %FS DYNAMIC PERFORMANCE Maximum Throughput Rate Signal-to-Noise Ratio Spurious-Free Dynamic Range to Nyquist, -12dBFS fCLK SNR 260 Full-scale output, within Nyquist window, fCLK = 260MHz, fOUT = 19.4MHz fCLK = 156MHz SFDR fCLK = 260MHz Spurious-Free Dynamic Range ±10MHz Window, -12dBFS 2nd-Order Harmonic Distortion, -12dBFS fCLK = 156MHz SFDR fCLK = 260MHz HD2 fCLK = 156MHz fCLK = 260MHz 2 MHz 160 fOUT = 1MHz, -2dBFS 89 fOUT = 19.42MHz 77 fOUT = 51.67MHz 76 fOUT = 19.4MHz 74 fOUT = 51.61MHz 72 fOUT = 19.42MHz 82 fOUT = 51.67MHz 75 fOUT = 19.42MHz 82 fOUT = 51.61MHz 76 fOUT = 1.27MHz -88 fOUT = 9.53MHz -86 fOUT = 19.42MHz -82 fOUT = 28.82MHz -79 fOUT = 38.42MHz -77 fOUT = 51.67MHz -79 fOUT = 70.05MHz -72 _______________________________________________________________________________________ dB/Hz dBc dBc dBc 14-Bit, 260Msps High-Dynamic Performance DAC (AVCC = DVCC = 5V, AGND = DGND = 0, external reference VREFIN = 1.196V, RT = 27.4Ω referenced to AVCC, VOUT = 1VP-P, RSET = 3.83kΩ, fCLK = 156MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER 3rd-Order Harmonic Distortion, -12dBFS SYMBOL HD3 CONDITIONS fCLK = 156MHz fCLK = 260MHz fCLK = 156MHz 2-Tone IMD, -9dBFS, 200kHz Frequency Spacing IM3 fCLK = 260MHz fCLK = 156MHz 2-Tone IMD, -12dBFS, 200kHz Frequency Spacing IM3 fCLK = 260MHz 4-Tone Power Ratio, -15dBFS, 200kHz Frequency Spacing 4-Tone Power Ratio, -18dBFS, 200kHz Frequency Spacing 8-Tone Power Ratio, -21dBFS, 200kHz Frequency Spacing 8-Tone Power Ratio, -24dBFS, 200kHz Frequency Spacing fCLK = 156MHz MTPR fCLK = 260MHz fCLK = 156MHz MTPR fCLK = 260MHz fCLK = 156MHz MTPR fCLK = 260MHz fCLK = 156MHz MTPR fCLK = 260MHz MIN TYP fOUT = 1.27MHz -90 fOUT = 9.53MHz -85 fOUT = 19.42MHz -81 fOUT = 28.82MHz -78 fOUT = 38.42MHz -78 fOUT = 51.64MHz -79 fOUT = 70.05MHz -80 fOUT = 18MHz 92 fOUT = 31MHz 90 fOUT = 18MHz 91 fOUT = 31MHz 89 fOUT = 18MHz 89 fOUT = 31MHz 87 fOUT = 18MHz 88 fOUT = 31MHz 87 fOUT = 18MHz 86 fOUT = 31MHz 84 fOUT = 18MHz 86 fOUT = 31MHz 84 fOUT = 18MHz 81 fOUT = 31MHz 79 fOUT = 18MHz 81 fOUT = 31MHz 78 fOUT = 18MHz 80 fOUT = 31MHz 77 fOUT = 18MHz 79 fOUT = 31MHz 76 fOUT = 18MHz 75 fOUT = 31MHz 73 fOUT = 18MHz 76 fOUT = 31MHz 74 MAX UNITS dBc dBc dBc dBc dBc dBc dBc REFERENCE AND CONTROL AMPLIFIER Internal Reference Voltage Range VREFOUT 1.136 1.196 1.255 V 1.196 ±8% V µV/°C Reference Input Voltage Range VREFIN Internal Reference Voltage Drift TCOREF 30 ISINK 200 µA ISOURCE 1.5 mA RIN 1 MΩ Internal Reference Sink/Source Current Amplifier Input Impedance _______________________________________________________________________________________ 3 MAX5195 ELECTRICAL CHARACTERISTICS (continued) MAX5195 14-Bit, 260Msps High-Dynamic Performance DAC ELECTRICAL CHARACTERISTICS (continued) (AVCC = DVCC = 5V, AGND = DGND = 0, external reference VREFIN = 1.196V, RT = 27.4Ω referenced to AVCC, VOUT = 1VP-P, RSET = 3.83kΩ, fCLK = 156MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG OUTPUT TIMING Output Fall Time tFALL 90% to 10% 0.8 Output Rise Time tRISE 10% to 90% 0.8 ns 0.5 pV-s Glitch Energy ns TIMING CHARACTERISTICS Data-to-Clock Setup Time (D0N–D13N, D0P–D13P) tSETUP Referenced to the rising edge, Figure 4 0.5 1 ns Data-to-Clock Hold Time (D0N–D13N, D0P–D13P) tHOLD Referenced to the rising edge, Figure 4 0.5 1.1 ns Propagation Delay Time tPD (Note 3) Minimum Clock Pulse Width High tCH CLKP, CLKN 1.6 0.5 ns ns Minimum Clock Pulse Width Low tCL CLKP, CLKN 1.6 ns 2.4 V LOGIC INPUTS (D0N–D13N, D0P–D13P, CLKP, CLKN) Input Logic High VIH Input Logic Low VIL 1.6 V Input Logic Current, Logic High IIH VIH = 2.4V -300 50 +300 µA Input Logic Current, Logic Low IIL VIL = 1.6V -300 10 +300 µA Digital Input Capacitance CIN 2 pF POWER SUPPLIES Analog Supply Voltage Range AVCC 4.75 4.75 5 5.25 V Digital Supply Voltage Range DVCC 5 5.25 V Analog Supply Current IAVCC AVCC = DVCC = 5V 48 58 mA Digital Supply Current IDVCC AVCC = DVCC = 5V 190 230 mA Power Dissipation PDISS AVCC = DVCC = 5V 1190 1440 Power-Supply Rejection Ratio PSRR AVCC = DVCC = 5V ±5% (Note 4) 0.2 mW %FS/V Note 1: Offset error is the deviation of the output voltage from its ideal value at midscale. Note 2: Full-scale gain error is the deviation of the output voltage from the ideal full-scale value. The actual full-scale voltage is determined by VOUTP - VOUTN, when D0P–D13P are set high and D0N–D13N are set low. Note 3: Propagation delay is the time difference between the active edge of the clock and the active edge of the output. Note 4: Power-supply rejection ratio is the full-scale output change as the supply voltage varies over its specified range. 4 _______________________________________________________________________________________ 14-Bit, 260Msps High-Dynamic Performance DAC REFERENCE VOLTAGE vs. TEMPERATURE DIFFERENTIAL NONLINEARITY 1.5 1.20 MAX5195 toc02 3 MAX5195 toc01 2.0 2 1.19 0.5 0 -0.5 VREFOUT (V) 1 DNL (LSB) 0 -1 -1.0 1.17 -2 -1.5 -2.0 -3 2048 4096 6144 8192 10240 12288 14336 16384 1.16 0 2048 4096 6144 8192 10240122881433616384 DIGITAL INPUT CODE -40 REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE 1.1888 1.70 GAIN ERROR (%FS) 1.1892 -0.04 -0.06 -0.08 5.125 5.250 1.65 1.60 1.55 -0.10 5.000 85 60 1.75 MAX5195 toc05 -0.02 OFFSET ERROR (%FS) 1.1896 35 GAIN ERROR vs. TEMPERATURE 0 MAX5195 toc04 1.1900 4.875 10 TEMPERATURE (°C) OFFSET ERROR vs. TEMPERATURE 1.1904 1.1884 4.750 -15 DIGITAL INPUT CODE MAX5195 toc06 0 1.50 -40 -15 10 35 60 85 -40 -15 10 35 85 60 ANALOG SUPPLY VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SUPPLY VOLTAGE SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 156.072MHz) 250 MAX5195 toc07 250 200 100 MAX5195 toc08 VREFOUT (V) 1.18 200 MAX5195 toc09 INL (LSB) 1.0 MAX5195 toc03 INTEGRAL NONLINEARITY -6dBFS 90 100 ANALOG SUPPLY CURRENT 80 150 100 SFDR (dBc) IAVCC, IDVCC (mA) IAVCC, IDVCC (mA) -12dBFS DIGITAL SUPPLY CURRENT 150 DIGITAL SUPPLY CURRENT ANALOG SUPPLY CURRENT 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 4.750 -18dBFS 60 50 50 70 50 40 4.875 5.000 5.125 ANALOG SUPPLY VOLTAGE (V) 5.250 0 10 20 30 40 50 60 70 80 fOUT (MHz) _______________________________________________________________________________________ 5 MAX5195 Typical Operating Characteristics (AVCC = DVCC = 5V, external reference VREFIN = 1.196V, fCLK = 156.072MHz, RT = 27.4Ω referenced to AVCC, CL = 15pF, VOUT = 1VP-P, RSET = 3.83kΩ, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVCC = DVCC = 5V, external reference VREFIN = 1.196V, fCLK = 156.072MHz, RT = 27.4Ω referenced to AVCC, CL = 15pF, VOUT = 1VP-P, RSET = 3.83kΩ, TA = +25°C, unless otherwise noted.) SFDR (dBc) -18dBFS 60 70 60 50 60 -18dBFS 40 60 80 100 120 40 0 20 40 60 80 100 120 140 20 0 40 60 80 100 120 140 160 fOUT (MHz) fOUT (MHz) fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (fOUT = 16MHz AT -12dBFS) SPECTRAL PLOT, SINGLE-TONE SFDR FOR A ±10MHz WINDOW SPECTRAL PLOT, SINGLE-TONE SFDR FOR A ±10MHz WINDOW -20 81 80 79 -30 -40 fCENTER -50 0 -60 -70 -20 -30 -40 77 -60 -70 -80 -90 -90 -100 -100 -110 -110 -40 -15 10 35 85 60 10 12 14 16 18 20 22 24 26 28 10 12 14 16 18 20 22 24 26 28 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) TEMPERATURE (°C) SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY (fOUT = 19MHz) -6dBFS -12dBFS 73 69 -70 32MHz/-18dBFS -75 4-TONE MTPR (dBc) 81 SFDR (dBc) MULTITONE (4 TONES) POWER RATIO vs. CLOCK FREQUENCY MAX5195 toc16 85 77 fCENTER -50 -80 78 fCLK = 260.12MHz fCENTER = 19.3975MHz OUTPUT AMPLITUDE: -12dBFS -10 -80 18MHz/-18dBFS 32MHz/-15dBFS -85 18MHz/-15dBFS -90 -18dBFS 65 MAX5195 toc17 AMPLITUDE (dBm) 82 fCLK = 156.072MHz fCENTER = 19.416 MHz OUTPUT AMPLITUDE: -12dBFS -10 AMPLITUDE (dBm) fCLK = 160MHz MAX5195 toc14 0 MAX5195 toc13 83 -95 150 180 210 240 fCLK (MHz) 6 -18dBFS 50 40 20 0 -12dBFS 70 50 40 -6dBFS 90 80 -12dBFS MAX5195 toc12 -6dBFS 80 70 100 SFDR (dBc) -12dBFS 80 SFDR (dBc) 90 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 312.144MHz) MAX5195 toc11 -6dBFS 90 100 MAX5195 toc10 100 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 260.12MHz) 270 300 330 150 180 210 240 270 300 330 fCLK (MHz) _______________________________________________________________________________________ MAX5195 toc15 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 208.096MHz) SFDR (dBc) MAX5195 14-Bit, 260Msps High-Dynamic Performance DAC 14-Bit, 260Msps High-Dynamic Performance DAC MULTITONE (8 TONES) POWER RATIO vs. CLOCK FREQUENCY -73.0 90% MAX5195 toc19 32MHz/-24dBFS 8-TONE MTPR (dBc) OUTPUT RISE/FALL TIMES MAX5195 toc18 -70.0 18MHz/-24dBFS -76.0 200mV/div 32MHz/-21dBFS -79.0 10% 18MHz/-21dBFS -82.0 -85.0 150 180 210 240 270 300 330 1ns/div fCLK (MHz) Pin Description PIN NAME FUNCTION 1 D9P 2 D8N Data Bit 9 Complementary Data Bit 8 3 D8P Data Bit 8 4 D7N Complementary Data Bit 7 5 D7P Data Bit 7 6 CLKP Converter Clock Input. Positive input terminal for LVPECL-compatible differential converter clock. 7 CLKN Complementary Converter Clock Input. Negative input terminal for LVPECL-compatible differential converter clock. 8 D6N Complementary Data Bit 6 9 D6P Data Bit 6 10 D5N Complementary Data Bit 5 11 D5P Data Bit 5 12 D4N Complementary Data Bit 4 13 D4P Data Bit 4 14 D3N Complementary Data Bit 3 15 D3P Data Bit 3 16, 47 DVCC Digital Supply Voltage. Accepts a 4.75V to 5.25V supply voltage range. Bypass to DGND with a capacitor combination of 10µF in parallel with 0.1µF and 47pF. 17, 46 18 19 20 21 22 DGND D2N D2P D1N D1P D0N Digital Ground Complementary Data Bit 2 Data Bit 2 Complementary Data Bit 1 Data Bit 1 Complementary Data Bit 0 (LSB) _______________________________________________________________________________________ 7 MAX5195 Typical Operating Characteristics (continued) (AVCC = DVCC = 5V, external reference VREFIN = 1.196V, fCLK = 156.072MHz, RT = 27.4Ω referenced to AVCC, CL = 15pF, VOUT = 1VP-P, RSET = 3.83kΩ, TA = +25°C, unless otherwise noted.) MAX5195 14-Bit, 260Msps High-Dynamic Performance DAC Pin Description (continued) PIN NAME 23 D0P Data Bit 0 (LSB) FUNCTION Test Point. Must be connected to LVPECL high level (2.4V) for optimum dynamic performance. 24 T.P. 25, 29, 32, 33, 35 AVCC Analog Supply Voltage. Accepts a 4.75V to 5.25V supply voltage range. Bypass to AGND with a capacitor combination of 10µF in parallel with 0.1µF and 47pF. 26 REFOUT Reference Output. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF capacitor to AGND, if an external reference source is used. 27, 28 AGND 30 OUTN Complementary DAC Output. Negative terminal for differential voltage output. 31 OUTP DAC Output. Positive terminal for differential voltage output. 34 AMPOUT Control Amplifier Output. For stable operation, bypass to AGND with a combination of a 3kΩ resistor in parallel with a 1.5µF tantalum capacitor. 36 RSET Output Current Set Resistor. External resistor (3.83kΩ to 7.66kΩ) sets the full-scale current of the DAC. 37 REFIN Reference Input. Accepts an input voltage range of 1.196V ±8%. Bypass to AGND with a 0.1µF capacitor, when used with the internal bandgap reference. 38 D13N Complementary Data Bit 13 (MSB) 39 D13P Data Bit 13 (MSB) 40 D12N Complementary Data Bit 12 41 D12P Data Bit 12 42 D11N Complementary Data Bit 11 43 D11P Data Bit 11 44 D10N Complementary Data Bit 10 45 D10P Data Bit 10 48 D9N Complementary Data Bit 9 8 Analog Ground _______________________________________________________________________________________ 14-Bit, 260Msps High-Dynamic Performance DAC The MAX5195 supports operation with the on-chip 1.2V bandgap reference or an external reference voltage source. REFIN serves as the input for an external reference source, and REFOUT provides a 1.2V output voltage, if the internal reference is used. For internal reference operation, REFIN and REFOUT must be connected together and decoupled to AGND with a 1µF capacitor in parallel with a 0.1µF capacitor for stable operation. Architecture The MAX5195 is a high-performance, 14-bit, segmented current-source array DAC (Figure 1) capable of operating with clock speeds up to 260MHz. The converter consists of separate input and DAC registers, followed by a current-source array. This current-source array is capable of generating differential full-scale currents in the range of 10mA to 20mA. An internal R2R resistor network, in combination with external 27.4Ω termination resistors, convert these differential output currents into a differential output voltage with a peak-to-peak output voltage range of 0.5V to 1V. An integrated 1.2V bandgap reference, control amplifier, and user-selectable, external resistor determine the data converter’s full-scale output range. The MAX5195 reference circuit also employs a control amplifier, designed to regulate the full-scale current IFS for the differential current outputs of the MAX5195. For stable operation, the output AMPOUT of this amplifier must be bypassed with a 3kΩ resistor in parallel with a 1.5µF tantalum capacitor to AGND. Configured as a voltage-to-current amplifier, the output current can be calculated as follows: IFS = 64 ✕ IREF - 1LSB DVCC 1.2V REFERENCE DGND AGND AVCC R2R NETWORK BIAS REFOUT REFIN OUTP CURRENT-SOURCE ARRAY RSET OUTN CLKN INPUT REGISTER CLKP DECODER INPUT LATCH MAX5195 14 D0N/D0P–D13N/D13P Figure 1. Simplified MAX5195 Block Diagram _______________________________________________________________________________________ 9 MAX5195 Internal Reference and Control Amplifier Detailed Description MAX5195 14-Bit, 260Msps High-Dynamic Performance DAC Table 1. IFS and RSET Selection Matrix Based on a Typical 1.2V Reference Voltage RSET (kΩ) FULL-SCALE CURRENT IFS (mA) REFERENCE CURRENT IREF (µA) CALCULATED 1% EIA STD OUTPUT VOLTAGE VOUTP/N* (mVP-P) 10 156.26 7.68 7.50 500 12 187.50 6.40 6.34 600 14 218.80 5.49 5.49 700 16 250.00 4.80 4.75 800 18 281.30 4.27 4.22 900 20 312.50 3.84 3.83 1000 *Terminated into a 27.4Ω load (see Analog Outputs section for details) referenced to AVCC. 1.5µF AVCC IFS = 64 ✕ IREF - (IFS / 214) where I REF is the reference output current (I REF = VREFOUT/RSET) and IFS is the full-scale current. RSET is the reference resistor that determines the amplifier’s output current (Figure 2) on the MAX5195. See Table 1 for a matrix of different IFS and RSET selections. CURRENT-SOURCE ARRAY Figure 3 illustrates a low-impedance reference source applied to the data converter for external reference operation. REFIN allows an input voltage range of 1.196V ±8%. Use a fixed output voltage reference source such as the 1.2V, 25ppm/°C (typ) MAX6520 bandgap reference for improved accuracy and drift performance. Bypass the unused REFOUT pin of the MAX5195 with a 1µF capacitor to AGND. 3kΩ MAX5195 1.2V REFERENCE External Reference Operation REFOUT 0.1µF 1µF OUTP REFIN OUTN RSET IREF = VREFOUT/RSET IREF NOTE: CONNECT REFIN AND REFOUT TOGETHER FOR INTERNAL REFERENCE OPERATION. Figure 2. Internal Reference Configuration 1.5µF 3kΩ AVCC MAX5195 AMPOUT 1.2V REFERENCE REFOUT 1µF REFIN MAX6520 OUTP RSET CURRENT-SOURCE ARRAY OUTN IREF = VREFOUT/RSET IREF Figure 3. External Reference Configuration Using the MAX6520 10 ______________________________________________________________________________________ 14-Bit, 260Msps High-Dynamic Performance DAC MINIMUM LVPECL SPECIFICATION MAXIMUM LVPECL SPECIFICATION Input Voltage High PARAMETER VCC** - 1.16V VCC** - 0.88V Input Voltage Low VCC** - 1.81V VCC** - 1.48V Common-Mode Level VCC** - 1.3V **VCC is the supply voltage associated with the LVPECL source. A typical VCC level associated with LVPECL is 3.3V, which sets the common-mode level to 2V, allowing a typical peak-to-peak signal swing of 0.8V. LVPECL-Compatible Digital Inputs (D0P–D13P, D0N–D13N) The MAX5195 digital interface consists of 14 differential, LVPECL-compatible digital input pins. These inputs follow standard positive binary coding where D0P and D0N represent the differential inputs to the least significant bit (LSB), and D13P and D13N represent the differential pair associated with the most significant bit (MSB). D0P/N through D13P/N accept LVPECL input levels of 0.8VP-P (Table 2). Each of the digital input terminals can be terminated with a separate 50Ω resistor; however, to achieve the lowest noise performance, it is recommended to terminate each differential pair with a 100Ω resistor located between the positive and negative input terminals. Clock Inputs (CLKP, CLKN) and Data Timing Relationship The MAX5195 features differential, LVPECL-compatible clock inputs. Internal edge-triggered flip-flops latch the input word on the rising edge of the clock-input pair CLKP/CLKN. The DAC is updated with the data word on the next rising edge of the clock input. This results in a conversion latency of one clock cycle. The MAX5195 tCH provides for minimum setup and hold times (<2ns), allowing for noncritical external interface timing (Figure 4). For best AC performance, a differential, DC-coupled clock signal with LVPECL-compatible voltage levels (Table 2) should be used. The MAX5195 operates properly with a clock duty cycle set within the limits listed in the Electrical Characteristics table. However, a 50% duty cycle should be utilized for optimum dynamic performance. To maintain the DAC’s excellent dynamic performance, clock and data signals should originate from separate signal sources. Analog Outputs (OUTP, OUTN) The MAX5195’s current array is designed to drive fullscale currents of 10mA to 20mA into an internal R2R resistor network (RR2R). To achieve the desired differential output voltage range of 0.5VP-P to 1VP-P, both OUTP and OUTN should be externally terminated into 27.4Ω (RT), resulting in a combined load of RLOAD = 25Ω (Figure 5): RLOAD = RR2R || RT RLOAD = (285Ω ✕ 27.4Ω) / (285Ω + 27.4Ω) RLOAD = 25Ω tCL CLKP CLKN tSETUP tHOLD D13–D0 OUTP 90% POINT tPD MAX5195 OUTN 10% POINT tRISE, tFALL Figure 4. Input/Output Timing Information ______________________________________________________________________________________ 11 MAX5195 Table 2. LVPECL Voltage Levels MAX5195 14-Bit, 260Msps High-Dynamic Performance DAC AVCC AVCC RR2R 285Ω RT 27.4Ω RR2R 285Ω RLOAD = 25Ω OUTN OUTP RT 27.4Ω The proportional, differential output voltages can then be used to drive a wideband RF transformer or a fast, low-noise, low-distortion operational amplifier to convert the differential voltage into a single-ended output. The MAX5195 analog outputs can also be configured in single-ended mode. For more details on different output configurations, see the Applications Information section. RLOAD = 25Ω Applications Information Differential Coupling Using a Wideband RF Transformer AVCC AMPOUT AGND MAX5195 RLOAD IS THE COMBINED LOAD OF THE INTERNAL R2R RESISTOR NETWORK IN PARALLEL WITH THE EXTERNAL TERMINATION RESISTOR. Figure 5. Simplified Output Architecture With a full-scale current of 10mA (20mA), both outputs OUTP and OUTN achieve a 0.25V (0.5V) voltage swing each, resulting in a 0.5VP-P (1VP-P) differential output signal. For applications that require an even smaller output voltage swing, the termination resistor value RT can be as low as 0Ω. A wideband RF transformer such as the TTWB1010 (1:1 turns ratio) from Coilcraft can be used to convert the MAX5195 differential output signal to a single-ended signal (Figure 6). As long as the generated output spectrum is within the passband of the transformer, a differentially coupled transformer provides the best distortion performance. Additionally, the transformer helps to reject noise and even-order harmonics, provides electrical isolation, and is capable of delivering more power to the load. Single-Ended Unbuffered Output Configuration Figure 7a shows an unbuffered single-ended output, which is suitable for applications requiring a unipolar voltage output. The nominal termination resistor load of 27.4Ω (referred to AVCC) results in a differential output AVCC, DVCC AVCC RT 27.4Ω VOUT, SINGLE ENDED OUTP AGND 1:1 D0–D13 14 OUTN TTWB1010 RT 27.4Ω MAX5195 AGND, DGND AVCC AGND WIDEBAND RF TRANSFORMER PERFORMS DIFFERENTIAL-TOSINGLE-ENDED CONVERSION. Figure 6. Differential Coupling Using a Wideband RF Transformer 12 ______________________________________________________________________________________ 14-Bit, 260Msps High-Dynamic Performance DAC MAX5195 AVCC, DVCC AVCC RT 27.4Ω OUTP VOUTP AGND D0–D13 VOUT_ = IFS × RLOAD 14 VOUTN OUTN RT 27.4Ω MAX5195 AVCC AGND, DGND AGND RLOAD: RESISTOR COMBINATION OF INTERNAL R2R NETWORK AND EXTERNAL TERMINATION RESISTOR Figure 7a. Single-Ended Unbuffered Output Configuration AVCC, DVCC RLOOP OUTP CLOOP D0–D13 VOUT 14 AGND OUTN MAX5195 AGND, DGND AVCC Figure 7b. Single-Ended Buffered Output Configuration swing of 1VP-P (0.5VP-P single ended) when applying a full-scale current of 20mA. Alternatively, an external unity-gain amplifier can be used to buffer the outputs. This circuit works as an I-V amplifier (Figure 7b), in which OUTP is held at AVCC by the inverting terminal of the buffer amplifier. OUTN should then be connected to AVCC to provide a DCcurrent path for the current switched to OUTP. The amplifier’s maximum output swing and the MAX5195 full-scale current determine the value of RLOOP. An optional roll-off capacitor (CLOOP) in the feedback loop helps to ease dV/dt requirements at the input of the operational amplifier. It is recommended that the amplifier’s power-supply rails be higher than the resistor’s output reference voltage AVCC due to its positive and negative output swing around AVCC. ______________________________________________________________________________________ 13 MAX5195 14-Bit, 260Msps High-Dynamic Performance DAC Grounding, Bypassing, and Power-Supply Considerations point connecting the two planes. Digital signals should run above the digital ground plane and analog signals above the analog ground plane. Digital signals should be kept as far away from sensitive analog inputs, reference input lines, and clock inputs. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The MAX5195 has two separate power-supply inputs for analog (AVCC) and digital (DVCC). Each AVCC input should be decoupled with parallel ceramic chip capacitors of 10µF in parallel with 0.1µF and 47pF with these capacitors as close to the supply pins as possible and their opposite ends with the shortest possible connection to the ground plane (Figure 8). The DV CC pins should also have separate 10µF in parallel with 0.1µF and 47pF capacitors adjacent to their respective pins. Try to minimize the analog and digital load capacitances for proper operation. Grounding and power-supply decoupling can strongly influence the performance of the MAX5195. Unwanted digital crosstalk can couple through the input, reference, power supply, and ground connections, thus affecting dynamic performance. Proper grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. This reduces EMI and internal crosstalk, which can also affect the dynamic performance of the MAX5195. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. High-speed signals should be run on lines directly above the ground plane. Since the MAX5195 has separate analog and digital ground buses (AGND and DGND, respectively), the PC board should have separate analog and digital ground sections with only one 5V 10µF 1.5µF 0.1µF 47pF 3kΩ DGND AMPOUT DVCC 5V AVCC 1.2V REFERENCE R2R NETWORK BIAS 47pF 0.1µF 10µF AGND REFOUT 27.4Ω AGND REFIN RSET OUTP CURRENT-SOURCE ARRAY 1µF VOUT 27.4Ω AGND OUTN 3.83kΩ AGND 0.1µF INPUT REGISTER CLKP 2.4V 1.6V DECODER 2V 260MHz, LVPECL MAX5195 CLKN INPUT LATCH 14 D0N/D0P–D13N/D13P Figure 8. Decoupling and Bypassing Techniques for MAX5195—Typical Operating Circuit 14 ______________________________________________________________________________________ 14-Bit, 260Msps High-Dynamic Performance DAC Enhanced Thermal Dissipation QFN-EP Package The MAX5195 is packaged in a thermally enhanced 48pin QFN-EP package, providing greater design flexibility, increased thermal efficiency, and a low thermal junction-case (θjc) resistance of ≈2°C/W. In this package, the data converter die is attached to an EP lead frame. The back of the lead frame is exposed at the package bottom surface (the PC board side of the package, Figure 9. This allows the package to be attached to the PC board with standard infrared (IR) flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (5.5mm ✕ 5.5mm), guarantees proper attachment of the chip, and can also be used for heat-sinking purposes. Designing thermal vias* into the land area and implementing large ground planes in the PC board design further enhance the thermal conductivity between board and package. To remove heat from a 48-pin QFN-EP package effectively, an array of 3 ✕ 3 (or greater) vias (≤0.3mm diameter per via hole and 1.2mm pitch between via holes) is recommended. A smaller via array can be used as well, but results in an increased θja. Note that efficient thermal management for the MAX5195 is strongly dependent on PC board and circuit design, component placement, and installation; therefore, exact performance figures cannot be provided. For more information on proper design techniques and recommendations to enhance the thermal performance of parts such as the MAX5195, refer to Amkor Technology’s website at www.amkor.com. Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured every individual step. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. *Connect the land pattern to internal or external copper planes. DIE 48-LEAD QFN PACKAGE WITH EXPOSED PAD BONDING WIRE EPOXY EXPOSED PAD COPPER TRACE, 1oz COPPER TRACE, 1oz PC BOARD TOP LAYER GROUND PLANE AGND, DGND POWER PLANE GROUND PLANE (AGND) 3 x 3 ARRAY OF THERMAL VIAS THERMAL LAND COPPER PLANE, 1oz MAX5195 Figure 9. MAX5195 Exposed Paddle/PC Board Cross Section ______________________________________________________________________________________ 15 MAX5195 The power-supply voltages should also be decoupled at the point where they enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a π network can also improve performance. The analog and digital power-supply inputs AVCC and DVCC of the MAX5195 allow a 4.75V to 5.25V supply voltage range. MAX5195 14-Bit, 260Msps High-Dynamic Performance DAC Offset Error The offset error is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is at midscale. This error affects all codes by the same amount. Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Glitch Energy Glitch impulses are caused by asymmetrical switching times in the DAC architecture, which generates undesired output transients. The amount of energy that appears at DAC’s output is measured over time and is usually specified in the pV-s range. Dynamic Performance Parameter Definitions Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum can be derived from the DAC’s resolution (N bits): SNRdB = 6.02dB ✕ N + 1.76dB However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading. SNR is therefore computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. 16 Spurious-Free Dynamic Range SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of the next largest distortion component. SFDR is measured in dBc, with respect to the carrier frequency amplitude. Multitone Power Ratio (MTPR) A series of equally spaced ones is applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most common test conditions for CDMA- and GSM/EDGE-type applications. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc of either input tone to the worst 3rd-order (or higher) IMD products. Note that 2nd-order IMD products usually fall at frequencies, which can be easily removed by digital filtering. Therefore, they are not as critical as 3rd-order IMDs. The two-tone IMD performance of the MAX5195 was tested with the two individual input tone levels set to -9dBFS and -12dBFS. Chip Information TRANSISTOR COUNT: 15,000 PROCESS: SiGe ______________________________________________________________________________________ 14-Bit, 260Msps High-Dynamic Performance DAC QFN 28, 32,44, 48L.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5195 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)