19-3486; Rev 0; 11/04 10Gbps Clock and Data Recovery with Limiting Amplifier The MAX3991 is a 10Gbps clock and data recovery (CDR) with limiting amplifier IC for XFP optical receivers. The MAX3991 and the MAX3992 (CDR with equalizer) form a signal conditioner chipset for use in XFP transceiver modules. The chipset is XFI compliant and offers multirate operation for data rates from 9.95Gbps to 11.1Gbps. The MAX3991 has 7mVP-P input sensitivity (BER ≤ 10-12), which allows direct connection to a transimpedance amplifier without the use of a stand-alone limiting amplifier. The phase-locked loop (PLL) is optimized for jitter tolerance and provides 0.6UI of high-frequency tolerance in SONET, Ethernet, and Fibre-Channel applications. The MAX3991 output provides 27% margin to the XFP eye mask specification. An AC-based power detector toggles the loss-of-signal (LOS) output when the input signal swing is below the user-programmed assert threshold. An external reference clock, with frequency equal to 1/64 or 1/16 of the serial data rate is used to aid in frequency acquisition. A loss-of-lock (LOL) indicator is provided to indicate the lock status of the receiver PLL. The MAX3991 is available in a 4mm x 4mm, 24-pin QFN package. It consumes 350mW from a single +3.3V supply and operates over the 0°C to +85°C temperature range. Features ♦ Multirate Operation from 9.95Gbps to 11.1Gbps ♦ 7mVP-P Input Sensitivity (BER ≤ 10-12) ♦ 0.6UIP-P Total High-Frequency Jitter Tolerance ♦ Low-Output Jitter Generation: 7mUIRMS ♦ Low-Output Deterministic Jitter: 4.6psP-P ♦ XFI-Compliant Output Interface ♦ LOS Indicator with Programmable Threshold ♦ LOL Indicator ♦ Power Dissipation: 350mW Ordering Information PART 0°C to +85°C 24 QFN T2444-4 MAX3991UTG+* 0°C to +85°C 24 QFN T2444-4 *Future product—contact factory for availability. +Denotes lead-free package. Pin Configuration FCTL1 REFCLK- REFCLK+ LOS LOL 24 23 22 21 20 19 VCC 1 18 VCC GND 2 17 GND SDI+ 3 16 SDO+ MAX3991 SDI- 4 GND 5 14 GND VCC 6 13 VCC 8 9 10 11 12 FCTL2 POL VCC CFIL 15 SDO- SCLKO- 7 SCLKO+ Typical Application Circuit appears at end of data sheet. TOP VIEW VTH 10.3Gbps/11.1Gbps Ethernet XFP Transceivers 10.5Gbps Fibre-Channel XFP Transceivers 10Gbps DWDM Transceivers PKG CODE MAX3991UTG Applications 9.95Gbps to 11.1Gbps Optical XFP Modules SONET OC-192/SDH STM-64 XFP Transceivers PINPACKAGE TEMP RANGE 4mm x 4mm QFN* *THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT-BOARD GROUND FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3991 General Description MAX3991 10Gbps Clock and Data Recovery with Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +4.0V Input Voltage Levels (SDI+, SDI-, REFCLK+, REFCLK-) ....................................(VCC - 1.0V) to (VCC + 0.5V) CML Output Voltage (SDO+, SDO-, SCLKO+, SLCKO-) ......................................(VCC - 1.0V) to (VCC + 0.5V) Voltage at (CFIL, LOL, VTH, POL, LOS, FCTL1, FCTL2) ..............................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 24-Pin QFN (derate 20.8mW/°C above +85°C) .........1355mW Junction Temperature Range ............................-40°C to +150°C Storage Temperature Range.............…………..-55°C to +150°C Lead Temperature (soldering, 10s) ..……………………..+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Supply Current CONDITIONS MIN ICC TYP MAX UNITS 106 140 mA DATA INPUT SPECIFICATION (SDI±) Single-Ended Input Resistance RSE 42 50 58 Ω Differential Input Resistance RD 84 100 116 Ω ±5 % Single-Ended Input Resistance Matching Differential Input Return Loss SDD11 0.1GHz to 5.5GHz (Note 1) 12.5 5.5GHz to 12GHz (Note 1) 6 DC Cancellation Loop LowFrequency Cutoff dB 30 kHz REFERENCE CLOCK SPECIFICATION (REFCLK±) Single-Ended Input Resisitance 84 100 116 Ω Differential Input Resistance 168 200 232 Ω 575 650 725 mVP-P CML OUTPUT SPECIFICATION (SDO±) SDO± Differential Output Swing (Note 2) SDO± Output Common-Mode Voltage RL = 50Ω to VCC VCC 0.16 SCLKO± Differential Output 380 Single-Ended Output Resistance Differential Output Resistance RO Differential Output Return Loss SDD22 Common-Mode Output Return 50 58 Ω 84 100 116 Ω ±5 % SCC22 0.1GHz to 5.5GHz (Note 1) 13 5.5GHz to 12GHz (Note 1) 8 0.1GHz to 15GHz (Note 1) Rise/Fall Time (20% to 80%) (Note 2) Output AC Common Mode Power-Down Assert Time mVP-P 42 Single-Ended Output Resistance Matching 2 V dB 5 18 23 dB 30 ps (Note 2) 10 mVRMS (Note 3) 50 µs _______________________________________________________________________________________ 10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991 ELECTRICAL CHARACTERISTICS (continued) (See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.05 0.25 UNITS JITTER SPECIFICATION Jitter Peaking JP Jitter Transfer Bandwidth JBW Sinusoidal Jitter Tolerance f ≤ 120kHz (Notes 2, 4) DJ 0.03 (Notes 2, 4) (Notes 2, 4, 6) Jitter Generation Serial Data Output Deterministic Jitter 120kHz < f ≤ 8MHz (Notes 2, 4) 5.6 8.0 f = 400kHz 3.0 >3 (Note 5) f = 4MHz 0.55 >0.6 (Note 5) f = 80MHz 0.45 >0.5 (Note 5) dB MHz UIP-P (Notes 2, 4, 7) 4.5 11.0 mUIRMS PRBS 27 - 1 (Note 2) 4.6 13 psP-P PLL ACQUISITION/LOCK SPECIFICATION Acquisition Time Figures 1, 2 (Note 2) 200 µs LOL Assert Time Figure 1 (Note 2) 90 µs Maximum Frequency Pullin Time (Note 8) 2 ms Frequency Difference at which LOL is Asserted ∆f/fREFCLK ∆f = |fVCO / N - fREFCLK|, N = 16 or 64 651 ppm Frequency Difference at which LOL is DeAsserted ∆f/fREFCLK ∆f = |fVCO / N - fREFCLK|, N = 16 or 64 500 ppm LOSS-OF-SIGNAL (LOS) SPECIFICATION VTH Control Voltage Range VTH 150 500 mV LOS Gain Factor VTH/ VLOS_ASSERT 10 V/V Minimum LOS Assert Voltage VLOS_ASSERT 15 mV Maximum LOS Assert Voltage VLOS_ASSERT 50 mV LOS Gain-Factor Accuracy (Notes 2, 9) -1.5 LOS Hysteresis (Notes 2, 10) 3.5 LOS Gain-Factor Stability (Note 2) Overtemperature and supply -10 +10 % LOS Assert Time Figure 2 (Note 2) 3 90 µs LOS Deassert Time Figure 2 (Note 2) 90 µs +5 µA 0.8 V V +30 µA VTH Input Current -5 3.7 +1.5 dB 3.9 dB LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LOS, FCTL1, FCTL2) Input High Voltage VIH Input Low Voltage VIL 2.0 Input Current -30 Output High Voltage VOH Sourcing 30µA Output Low Voltage VOL Sinking 1mA VCC 0.5 V 0.4 V _______________________________________________________________________________________ 3 MAX3991 10Gbps Clock and Data Recovery with Limiting Amplifier ELECTRICAL CHARACTERISTICS (continued) (See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) Note 1: Measured with 100mVP-P differential amplitude. Note 2: Guaranteed by design and characterization. Note 3: Measured from the time that the FCTL1 input goes high with FCTL2 = 0 to the time when the supply current drops to less than 40% of the nominal value. Note 4: Measured with PRBS = 231 - 1. Note 5: Measurement limited by test equipment. Note 6: Jitter tolerance is for BER ≤ 10-12, measured with additional 0.1UI deterministic jitter and 40mVP-P differential input. Note 7: Measured with 50kHz to 80MHz SONET filter. Note 8: Applies on power-up, after standby. Note 9: Over process, temperature, and supply. Note 10: Hysteresis is defined as 20Log(VLOS-DEASSERT / VLOS-ASSERT). Table 1. Operating Conditions (Unless otherwise noted, FCTL1 = FCTL2 = 0.) PARAMETER Supply Voltage SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 3.0 3.6 V Ambient Temperature TA 0 +85 °C Input Data Rate Rb SDI± Differential Input Voltage Swing VD Load Resistance RL (See Table 2 ) 15 RL is AC-coupled 1000 300 REFCLK Duty Cycle 30 1600 mVP-P 70 % Rb / 16 fREFCLK GHz Rb / 64 -100 mVP-P Ω 50 REFCLK± Differential Input Voltage Swing REFCLK Frequency Gbps REFCLK Accuracy Relative to Rb / 16 or Rb / 64 REFCLK Rise/Fall Times (20% to 80%) fREFCLK= Rb / 64 +100 1200 fREFCLK= Rb / 16 300 REFCLK Random Jitter Noise bandwidth < 100MHz 10 ppm ps psRMS Table 2. Serial Data Rate and Reference Clock Frequency DATA RATE (Rb) (Gbps) /16 REFERENCE CLOCK FREQUENCY (MHz) /64 REFERENCE CLOCK FREQUENCY (MHz) OC-192 SONET – SDH64 9.95328 622.08 155.52 OC-192 SONET Over FEC 10.664 666.5 166.625 ITU G.709 10.709 669.3125 167.328125 10Gbps Ethernet, IEEE 802.3ae 10.3125 644.53125 161.1328125 10 Gigabit Ethernet Over ITU G.709 11.09573 693.483125 173.3707813 10Gbps Fibre Channel 10.51875 657.421875 164.355469 APPLICATION Note: The part should be in standby mode when data rates are being switched. 4 _______________________________________________________________________________________ 10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991 ∆f/fREFCLK 651ppm 500ppm LOL ASSERT TIME ACQUISITION TIME LOL *ASSERT AND ACQUISITION TIME ARE DEFINED WITH A VALID REFERENCE CLOCK APPLIED. Figure 1. RX LOL Assert and PLL Acquisition Time DATA INPUT POWER LOS ASSERT TIME LOS DEASSERT TIME LOS ACQUISITION TIME LOL Figure 2. LOS Assert/Deassert Time _______________________________________________________________________________________ 5 Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) MAX3991 OUTPUT (INPUT = 9.95328Gbps, 231-1 PATTERN) MAX3991 toc01 JITTER GENERATION vs. POWER-SUPPLY WHITE NOISE AMPLITUDE (BW < 100kHz) MAX3991 toc02 16 MAX3991 toc03 MAX3991 OUPTUT AFTER XFP CONNECTOR (INPUT = 9.95328Gbps, 231-1 PATTERN, 10mVP-P) JITTER GENERATION (mUIRMS) 14 12 10 8 6 4 2 0 20ps/div 20ps/div 0 10 20 30 40 50 NOISE AMPLITUDE (mVRMS) 0.05 0.04 0.03 0.02 10 SONET MASK 1 0.01 0.1 10k 0 10k 100k 1M 10M 100k MAX3991 toc06 0.35 0.30 0.25 0.20 0.15 PATTERN = 231 -1 PRBS WITH 0.2UIP-P ADDITIONAL DETERMINISTIC JITTER, 10.095Gbps 0.10 0.05 0 1M 10M 0 100M BIT ERROR RATIO vs. INPUT AMPLITUDE 1.0E-08 1.0E-09 1.0E-10 1.0E-11 1.0E-12 30 40 140 MAX3991 toc08 0 50 130 -3 120 -6 ICC (mA) JITTER TRANSFER (dB) 1.0E-04 1.0E-05 1.0E-06 1.0E-07 20 SUPPLY CURRENT vs. TEMPERATURE JITTER TRANSFER 3 MAX3991 toc07 1.0E-00 1.0E-01 1.0E-02 1.0E-03 10 DIFFERENTIAL INPUT AMPLITUDE (mVP-P) FREQUENCY (Hz) FREQUENCY (Hz) -9 -12 110 100 -15 90 -18 80 -21 4.5 5.0 5.5 6.0 6.5 DIFFERENTIAL INPUT AMPLITUDE (mVP-P) 6 0.40 MAX3991 toc09 1k INPUT = 30mVP-P, PRBS 231-1, 10.095Gbps, 0.2UIP-P 0.45 80MHz JITTER TOLERANCE (U|P-P) JITTER TOLERANCE (U|P-P) 0.06 TOLERANCE EXCEEDS MODULATION CAPABILITIES OF TEST EQUIPMENT MAX3991 toc05 100 MAX3991 toc04 ADDITIONAL OUTPUT JITTER (psP-P/mVP-P) 0.07 SINUSOIDAL JITTER TOLERANCE vs. INPUT AMPLITUDE JITTER TOLERANCE vs. FREQUENCY SUPPLY-INDUCED OUTPUT JITTER BIT ERROR RATIO MAX3991 10Gbps Clock and Data Recovery with Limiting Amplifier 7.0 1k 10k 100k 1M FREQUENCY (MHz) 10M 100M -5 10 25 40 55 AMBIENT TEMPERATURE (°C) _______________________________________________________________________________________ 70 85 10Gbps Clock and Data Recovery with Limiting Amplifier XFI XFI -10 SCC22 (dB) -5 -10 -15 -20 -25 -15 20 -25 -30 -30 -35 -40 100M 1G 10G 100G -35 100M FREQUENCY (mHz) 140 MAX3991 toc12 -5 160 DIFFERENTIAL INPUT AMPLITUDE (mVP-P) 0 MAX3991 toc11 5 SDD22 (dB) 0 MAX3991 toc10 10 LOS ASSERT/DEASSERT LEVELS vs. VTH VOLTAGE SCC22 vs. FREQUENCY SDD22 vs. FREQUENCY DEASSERT THRESHOLD 120 100 80 60 ASSERT THRESHOLD 40 20 0 1G 10G 100G FREQUENCY (Hz) 0 200 400 600 800 1000 1200 1400 1600 VTH VOLTAGE (mV) Pin Description PIN NAME FUNCTION 1, 6, 11, 13, 18 VCC 2, 5, 14, 17 GND +3.3V Power Supply Supply Ground 3 SDI+ Positive Serial Input, CML 4 SDI- Negative Serial Input, CML 7 SCLKO+ Positive Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use in device testing). 8 SCLKO- Negative Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use in device testing). 9 FCTL2 10 POL Data Polarity Control Input, TTL. Connect to VCC or leave open to maintain the same polarity as the input. Connect to GND to invert the polarity of the data. 12 CFIL Loop-Filter Capacitor Connection. Connect a 0.047µF capacitor between CFIL and VCC. 15 SDO- Negative Serial Data Output, CML 16 SDO+ 19 LOL Lock Status Indicator, TTL. This output goes high to indicate the receiver is out of lock. 20 LOS Receiver Loss-of-Signal Indicator, TTL . This output goes high when the input signal drops below the programmed threshold. Function Control Input 2, TTL. See Table 3 for more information. Positive Serial Data Output, CML _______________________________________________________________________________________ 7 MAX3991 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) 10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991 Pin Description (continued) PIN NAME FUNCTION 21 REFCLK+ Positive Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the reference clock source. REFCLK± have a 200Ω differential impedance. See the Detailed Description section for more information. See Table 2. 22 REFCLK- Negative Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the reference clock source. REFCLK± have a 200Ω differential impedance. See the Detailed Description section for more information. See Table 2. 23 FCTL1 24 VTH EP Exposed Pad Function Control Input 1, TTL. See Table 3 for more information. LOS Threshold Input, Analog. A voltage applied to this input sets the LOS assert threshold. The LOS power detector can be disabled if VTH is connected to VCC, which forces LOS low. Supply Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal and electrical performance. The MAX3991 uses exposed-pad variation T2444-4 in the package outline drawing. See the exposed-pad package. Functional Diagram VTH LOS MAX3991 SDI+ SDI- CML DFF LIMITING AMPLIFIER D SDO+ CML Q SDOPLL PHASE/ FREQUENCY DETECTOR REFCLK+ REFCLK- 200Ω SCLKO- LOL DETECTOR FUNCTIONAL CONTROL FCTL1 LOL SCLKO+ CML VCO CFIL FCTL2 POL Figure 3. Functional Diagram Detailed Description The MAX3991 clock and data recovery with limiting amplifier restores data to XFI specifications. It consists of a limiting amplifier with LOS power detector, and a PLL data retimer with LOL indicator. An optional recovered clock may also be enabled for performance testing. 8 Limiting Amplifier The SDI inputs of the MAX3991 accept serial NRZ data from the optical receiver assembly. The limiting amplifier accepts signals as small as 7mVP-P and amplifies them to allow recovery by the CDR. The limiting amplifier uses an offset cancellation circuit to compensate for device mismatch within the gain stages. The low-frequency cutoff of the offset cancellation loop is typically 30kHz. _______________________________________________________________________________________ 10Gbps Clock and Data Recovery with Limiting Amplifier Reference Clock Input The REFCLK inputs are internally terminated and selfbiased to allow AC-coupling. The input impedance is 100Ω single-ended (200Ω differential). The REFCLK inputs of the MAX3991 and MAX3992 should be connected close together in parallel. The impedance looking into the parallel combination is 100Ω differential. This allows both the MAX3991 and MAX3992 to easily interface with one reference clock without using additional components. See Figure 5. Loss-of-Lock Monitor Design Procedure The LOL output indicates that the frequency difference between the recovered clock and the reference clock is excessive. LOL may assert due to excessive jitter at the data input, incorrect frequency, or loss of input data. The LOL detector monitors the frequency difference between the recovered clock and the reference clock. The LOL output is asserted high when the frequency difference exceeds 650ppm. Loss-of-Signal Monitor The LOS output indicates low, receive-signal power. The LOS output is asserted high when the input signal is below the threshold set by VTH. VTH = 10 x VLOS_ASSERT(mVP-P) (typ) The hysteresis value of the LOS detector is internally fixed at 1.5. Hysteresis values above 1.5 can be achieved using external resistors as shown in Figure 4. The new hysteresis value is: Hysteresis = 1.5 × 3 × R1 + VREF × R2 0.2 × R1 + VREF × R2 Resistor R2 is selected to prevent loading of the LOS pin. A value of >40kΩ is recommended. Refer to applications note HFDN 34-0. LOS R2 MAX3992 R1 VTH VREF Modes of Operation The MAX3991 has a standby mode, jitter test mode, and squelch mode in addition to its normal operating mode. Standby is used to conserve power. In the standby mode, the power consumption of the MAX3991 falls below 40% of the normal-operation power consumption. The jitter test mode enables the SCLK outputs to clock a BERT when testing jitter generation, jitter transfer, and jitter tolerance. In the squelch mode, the SDO± outputs are held static at VCC. The FCTL1 and FCTL2 TTL inputs are used to select the mode of operation as shown in Table 3. Serial Data Rate and Reference Clock Frequency Input Configuration The SDI± inputs of the MAX3991 are current-mode logic (CML) compatible. The inputs have internal 50Ω terminations for minimum external components. See Figure 6 for the input structure. AC-coupling is recommended. The common-mode levels of DC-coupled parts must be matched. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML. Output Configuration The MAX3991 uses CML for its high-speed digital outputs (SDO± and SCLKO±). The configuration of the output circuit includes internal 50Ω back terminations to VCC. See Figure 7 for the output structure. CML outputs may be terminated by 50Ω to VCC, or by 100Ω differential impedance. The relation of the output polarity to input can be reversed using the POL pin (see Figure 8). For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML. Figure 4. Added Hysteresis Circuit _______________________________________________________________________________________ 9 MAX3991 PLL Retimer The integrated PLL recovers a synchronous clock, which is used to retime the input data. Connect a 0.047µF capacitor between CFIL and VCC to provide PLL dampening. The external reference connected to REFCLK aids in frequency acquisition. Because the reference clock is only used for frequency acquisition, a low-quality reference clock can be used with no penalty in performance. The reference clock should be within ±100ppm of the bit rate divided by 16 or 64. MAX3991 10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991 50Ω REFERENCE CLOCK 200Ω MAX3991 50Ω REFERENCE CLOCK 200Ω 200Ω 50Ω 50Ω RECEIVER-ONLY TERMINATION MAX3992 200Ω TRANSCEIVER TERMINATION Figure 5. Reference Clock Termination Table 3. Functional Control FCTL1 FCTL2 0 0 Normal operation, serial clock output disabled. 1 0 Standby power-down mode. 0 1 Serial data output disabled. 1 1 Serial clock output enabled for jitter testing. VCC DESCRIPTION 50Ω 50Ω SDI+ SDI- Applications Information Exposed Pad (EP) Package The exposed pad, 24-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3991 and must be soldered to the circuit board for proper thermal and electrical performance. Figure 6. CML Input Model Layout Considerations For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3991 high-speed inputs and outputs. Power-supply decoupling should be placed as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals. 10 ______________________________________________________________________________________ 10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991 VCC 50Ω 50Ω SDO+ SDO- GND Figure 7. CML Output Model (SDI+) - (SDI-) (SDO+) - (SDO-) POL = VCC (SDO+) - (SDO-) POL = GND Figure 8. Polarity (POL) Function ______________________________________________________________________________________ 11 MAX3991 10Gbps Clock and Data Recovery with Limiting Amplifier Typical Application Circuit VCC 0.047µF TOSA VCC CFIL GND SDI+ SDO+ SDI- MAX3975 DRIVER MAX3992 SDO- REFCLK+ REFCLK- FCTL VTH POL LOL LOS N.C. 2 30-PIN CONNECTOR DS1862* CONTROLLER 2 2-WIRE INTERFACE N.C. FCTL VTH POL LOL LOS REFCLK+ SDI+ REFCLK- RO5A MAX3991 SDI- SDO+ SDO- CFIL VCC GND XFI REFERENCE 0.047µF VCC Chip Information TRANSISTOR COUNT: 10,300 50Ω TRANSMISSION LINE *FUTURE PRODUCT Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maximic.com/packages.) (QFN 4mm x 4mm x 0.8mm, package code: T2444-4) PROCESS: SiGe bipolar SUBSTRATE: SOI Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.