ABRIDGED DATA SHEET EVALUATION KIT AVAILABLE DS28E25 1-Wire SHA-256 Secure Authenticator with 4Kb User EEPROM General Description The DS28E25 combines crypto-strong, bidirectional, secure challenge-and-response authentication functionality with an implementation based on the FIPS 180-3-specified Secure Hash Algorithm (SHA-256). A 4Kb user-programmable EEPROM array provides nonvolatile storage of application data and additional protected memory holds a read-protected secret for SHA256 operations and settings for user memory control. Each device has its own guaranteed unique 64-bit ROM identification number (ROM ID) that is factory programmed into the chip. This unique ROM ID is used as a fundamental input parameter for cryptographic operations and also serves as an electronic serial number within the application. A bidirectional security model enables two-way authentication between a host system and slave-embedded DS28E25. Slave-to-host authentication is used by a host system to securely validate that an attached or embedded DS28E25 is authentic. Hostto-slave authentication is used to protect DS28E25 user memory from being modified by a nonauthentic host. The SHA-256 message authentication code (MAC), which the DS28E25 generates, is computed from data in the user memory, an on-chip secret, a host random challenge, and the 64-bit ROM ID. The DS28E25 communicates over the single-contact 1-WireM bus at overdrive speed. The communication follows the 1-Wire protocol with the ROM ID acting as node address in the case of a multipledevice 1-Wire network. Applications Features SSymmetric Key-Based Bidirectional Secure Authentication Model Based on SHA-256 SDedicated Hardware-Accelerated SHA Engine for Generating SHA-256 MACs SStrong Authentication with a High Bit Count, UserProgrammable Secret, and Input Challenge S4096 Bits of User EEPROM Partitioned Into 16 Pages of 256 Bits SUser-Programmable and Irreversible EEPROM Protection Modes Including Authentication, Write and Read Protect, and OTP/EPROM Emulation SUnique, Factory-Programmed 64-Bit Identification Number SSingle-Contact 1-Wire Interface Communicates with Host at Up to 76.9kbps SOperating Range: 3.3V ±10%, -40NC to +85NC SLow-Power 5µA (typ) Standby S±8kV Human Body Model ESD Protection (typ) S2-Pin SFN, 2-Pin TO-92, 6-Pin TDFN, and 6-Pin TSOC Packages Typical Application Circuit 3V RP (I2C PORT) Authentication of Network-Attached Appliances Printer Cartridge ID/Authentication Reference Design License Management SDA SCL RP = 1.1kΩ MAXIMUM I2C BUS CAPACITANCE 320pF VCC DS2465 µC SLPZ IO 1-Wire LINE System Intellectual Property Protection Sensor/Accessory Authentication and Calibration DS28E25 Secure Feature Setting for Configurable Systems Key Generation and Exchange for Cryptographic Systems Ordering Information appears at end of data sheet. 1-Wire is a registered trademark of Maxim Integrated Products, Inc. For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/DS28E25.related For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 219-0019; Rev 1; 8/12 ABRIDGED DATA SHEET DS28E25 1-Wire SHA-256 Secure Authenticator with 4Kb User EEPROM ABSOLUTE MAXIMUM RATINGS IO Voltage Range to GND....................................... -0.5V to 4.0V IO Sink Current....................................................................20mA Operating Temperature Range .......................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -55NC to +125NC Lead Temperature (soldering, 10s) TO-92, TSOC, TDFN....................................................+300NC Soldering Temperature (reflow) TO-92...........................................................................+250NC TSOC, TDFN................................................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = -40NC to +85NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 2) 2.97 3.63 V 1-Wire Pullup Resistance RPUP VPUP = 3.3V Q 10% (Note 3) 300 1500 I Input Capacitance CIO Input Load Current IL (Notes 4, 5) 1500 IO pin at VPUP High-to-Low Switching Threshold VTL (Notes 6, 7) Input Low Voltage VIL (Notes 2, 8) 5 pF 19.5 0.65 x VPUP FA V 0.3 V Low-to-High Switching Threshold VTH (Notes 6, 9) 0.75 x VPUP Switching Hysteresis VHY (Notes 6, 10) 0.3 Output Low Voltage VOL IOL = 4mA (Note 11) Recovery Time tREC RPUP = 1500I (Notes 2, 12) 5 Fs Time-Slot Duration tSLOT (Notes 2, 13) 13 Fs V V 0.4 V IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Reset Low Time tRSTL (Note 2) 48 80 Reset High Time tRSTH (Note 14) 48 Presence-Detect Sample Time tMSP (Notes 2, 15) 8 10 Fs Write-Zero Low Time tW0L (Notes 2, 16) 8 16 Fs Write-One Low Time tW1L (Notes 2, 16) 1 2 Fs tRL (Notes 2, 17) 1 2-d Fs tMSR (Notes 2, 17) tRL + d 2 Fs Fs Fs IO PIN: 1-Wire WRITE IO PIN: 1-Wire READ Read Low Time Read Sample Time EEPROM Programming Current IPROG VPUP = 3.63V (Notes 5, 18) 1 mA Programming Time for a 32-Bit Segment tPROG (Note 19) 10 ms Write/Erase Cycling Endurance NCY TA = +85NC (Notes 20, 21) Data Retention tDR TA = +125NC (storage) (Notes 22, 23, 24) Maxim Integrated 100k — 10 Years 2 ABRIDGED DATA SHEET DS28E25 1-Wire SHA-256 Secure Authenticator with 4Kb User EEPROM ELECTRICAL CHARACTERISTICS (continued) (TA = -40NC to +85NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SHA-256 ENGINE Computation Current ICSHA Computation Time tCSHA Refer to the full data sheet. mA ms Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. Note 4: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication. Note 5: Guaranteed by design and/or characterization only; not production tested. Note 6:VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on IO, a logic-zero is detected. Note 8: The voltage on IO must be less than or equal to VILMAX at all times when the master is driving IO to a logic-zero level. Note 9: Voltage above which, during a rising edge on IO, a logic-one is detected. Note 10:After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero. Note 11:The I-V characteristic is linear for voltages less than 1V. Note 12:Applies to a single device attached to a 1-Wire line. Note 13:Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN). Note 14:An additional reset or communication sequence cannot begin until the reset high time has expired. Note 15:Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E25 present. The power-up presence detect pulse could be outside this interval, but will be complete within 2ms after power-up. Note 16:ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 17:δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Note 18:Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during the programming and computation interval should be such that the voltage at IO is greater than or equal to VPUPMIN. A low-impedence bypass of RPUP activated during programming and computation is the recommended way to meet this requirement. Note 19:Refer to the full data sheet. 20:Write-cycle endurance is tested in compliance with JESD47G. 21:Not 100% production tested; guaranteed by reliability monitor sampling. 22:Data retention is tested in compliance with JESD47G. 23:Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 24:EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-term storage at elevated temperatures is not recommended. Note 25:Refer to the full data sheet. Note Note Note Note Maxim Integrated 3 ABRIDGED DATA SHEET DS28E25 1-Wire SHA-256 Secure Authenticator with 4Kb User EEPROM Pin Configurations BOTTOM VIEW TOP VIEW 1 2 + DS28E25 GND IO GND N.C. DS28E25 6 N.C. 1 2 DS28E25 5 4 3 N.C. IO 2 N.C. GND 3 TSOC SFN (6mm x 6mm x 0.9mm) + N.C. 1 6 N.C. 28E25 ymrrF IO TOP VIEW EP 5 N.C. 4 N.C. TDFN (3mm × 3mm) NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE. SIDE VIEW FRONT VIEW IO 1 N.C. 2 GND 3 1 2 3 TO-92 Pin Descriptions PIN NAME SFN TO-92 TSOC TDFN-EP 2 3 1 3 GND 1 1 2 2 IO — 2 3, 4, 5, 6 1, 4, 5, 6 N.C. — — — — EP Maxim Integrated FUNCTION Ground Reference 1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor. Not Connected Exposed Pad (TDFN only). Solder evenly to the board’s ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. 4 ABRIDGED DATA SHEET DS28E25 1-Wire SHA-256 Secure Authenticator with 4Kb User EEPROM Note to readers: This document is an abridged version of the full data sheet. Additional device information is available only in the full version of the data sheet. To request the full data sheet, go to www.maxim-ic.com/ DS28E25 and click on Request Full Data Sheet. Ordering Information PART TEMP RANGE PIN-PACKAGE 2 SFN (2.5k pcs) DS28E25G+T -40°C to +85°C DS28E25+ -40°C to +85°C 2 TO-92 DS28E25P+ -40°C to +85°C 6 TSOC DS28E25P+T -40°C to +85°C 6 TSOC (4k pcs) DS28E25Q+T -40°C to +85°C 6 TDFN-EP* (2.5k pcs) +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. Maxim Integrated Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 2 SFN G266N+1 21-0390 — 2 TO-92 Q2+1 21-0249 — 6 TSOC D6+1 21-0382 90-0321 6 TDFN-EP T633+2 21-0137 90-0058 43 ABRIDGED DATA SHEET DS28E25 1-Wire SHA-256 Secure Authenticator with 4Kb User EEPROM Revision History REVISION NUMBER REVISION DATE 0 7/12 Initial release 1 8/12 Replaced the Typical Application Circuit; added the TO-92 package to the Features, Absolute Maximum Ratings, Pin Configurations, Pin Descriptions, Ordering Information, and Package Information sections DESCRIPTION PAGES CHANGED — 1, 2, 4, 43 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated 44 The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc. DS28E25 - 概述 Page 1 of 2 Login 产品 方案 设计 销售联络 支持中心 公司简介 Register 简体中文 (cn) 我的Maxim Maxim > 产品 > 1-Wire®器件 > DS28E25 Maxim > 产品 > 存储器 > DS28E25 Maxim > 产品 > 安全与认证 > DS28E25 DS28E25 1-Wire SHA-256 Authenticator with 4Kb User EEPROM Provides World Class Authentication Security to Protect Your Development Investment 概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况 数据资料 状况：生产中。 数据资料缩写本 英文 下载 Rev. 1 (PDF, 840.9kB) 概述 申请数据资料全文 The DS28E25 combines secure challenge-and-response authentication functionality based on the FIPS 180-3-specified 定制产品 Secure Hash Algorithm (SHA-256) with 4Kb of user-programmable EEPROM. Additional secure memory holds a secret/key for SHA-256 operations. Each device has its own guaranteed unique 64-bit ROM identification number (ROM ID) that is factory programmed into the chip. The SHA-256 message authentication code (MAC), which the DS28E25 generates, is computed from data in the user memory, the SHA-256 secret, a host controller random challenge, and the 64-bit ROM ID. A secure and low-cost factory-programming service is available to pre-program device data including the SHA-256 secret. The DS28E25 communicates over Maxim's single-contact 1-Wire® bus. 关键特性 应用/使用 Symmetric-Key-Based Bidirectional Secure Authentication Model Based on SHA-256 Sophisticated Die-Level Methods and Circuits for Tamper Protection of Sensitive Data and Signals Dedicated Hardware-Accelerated SHA Engine for Generating SHA-256 MACs Strong Authentication with a High Bit Count, UserProgrammable Secret, and Input Challenge 4096 Bits of User EEPROM Partitioned Into 16 Pages of 256 Bits User-Programmable and Irreversible EEPROM Protection Modes Including Authentication, Write and Read Protect, and OTP/EPROM Emulation Unique, Factory-Programmed 64-Bit Identification Number Single-Contact 1-Wire Interface Communicates with Host at Up to 76.9kbps Operating Range: 3.3V ±10%, -40°C to +55°C ±8kV HBM ESD Protection (typ) 2-Pin SFN, 2-Pin TO-92, 6-Pin TDFN, and 6-Pin TSOC Packages 消费品鉴别与认证 授权管理的参考设计 传感器/配件识别和校准 系统知识产权保护 关键特性: Memory (EPROM, EEPROM, ROM, NV SRAM) Part Number Memory Type Memory Size Bus Type Real Time Clock DIP w/Int. Batt. Pwr. Cap Pckg. Battery Monitor GPIO DS28E25 NEW! EEPROM 4K x 1 1-Wire No No No No No VSUPPLY (V) VSUPPLY (V) min max 2.97 3.63 查看所有Memory (EPROM, EEPROM, ROM, NV SRAM) (61) Pricing Notes: This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor. 图表 http://china.maximintegrated.com/datasheet/index.mvp/id/7535 2012-09-12 DS28E25 - 概述 Page 2 of 2 Typical Application Circuit 没有找到你需要的产品吗？ 应用工程师帮助选型，下个工作日回复 参数搜索 应用帮助 信息索引 概述 技术文档 定购信息 相关产品 概述 关键特性 应用/使用 关键指标 图表 注释、注解 数据资料 技术文档 评估板 可靠性报告 软件/模型 价格与供货 样品 在线订购 封装信息 无铅信息 类似功能器件 类似应用器件 评估板 类似型号器件 配合该器件使用的产品 参考文献： 219-0019 Rev. 1; 2012-09-11 本页最后一次更新: 2012-09-11 © 2012 Maxim Integrated版权所有 联络我们' | 隐私权政策 | http://china.maximintegrated.com/datasheet/index.mvp/id/7535 法律声明 | 代理商网站入口 | 关注我们 2012-09-12