MICRONAS MAS3507D

PRELIMINARY DATA SHEET
MICRONAS
Edition March 16, 2000
6251-459-3PD
MAS 3507D
MPEG 1/2 Layer 2/3
Audio Decoder
MAS 3507D
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
5
5
6
6
6
1.
1.1.
1.2.
1.2.1.
1.2.2.
Introduction
Features
Application Overview
Multimedia Mode
Broadcast Mode
7
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2.
2.1.
2.2.
2.3.
2.4.
2.4.1.
2.4.2.
2.4.3.
2.5.
2.6.
2.6.1.
2.6.2.
2.6.3.
2.6.4.
2.7.
2.7.1.
2.7.2.
2.7.3.
2.7.3.1.
2.7.3.2.
2.7.3.3.
2.7.3.4.
2.7.4.
2.7.4.1.
2.7.4.2.
2.7.4.3.
2.8.
2.8.1.
2.9.
Functional Description of the MAS 3507D
DSP Core
Firmware (Internal Program ROM)
Program Download Feature
Baseband Processing
Volume Control / Channel Mixer
Mute / Bypass Tone Control
Bass / Treble Control
Clock Management
Power Supply Concept
Internal Voltage Monitor
DC/DC Converter
Stand-by Functions
Start-up Sequence
Interfaces
MPEG Bit Stream Interface (SDI)
SDI* Selection
Parallel Input Output Interface (PIO)
PIO-DMA Input Mode
Writing MPEG Data to the PIO-DMA
DMA Handshake Protocol
End of DMA Transfer
Audio Output Interface (SDO)
Mode 1: 16 Bits/Sample(I2S Compatible Data Format)
Mode 2:32 Bit/Sample (Inverted SOI)
Other Output Modes
Start-up Configuration
Parallel Input Output Interface (PIO)
Status Pins in SDI Input Mode
2
Micronas
PRELIMINARY DATA SHEET
MAS 3507D
Contents, continued
Page
Section
Title
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3.
3.1.
3.1.1.
3.2.
3.2.1.
3.2.2.
3.3.
3.3.1.
3.3.2.
3.3.3.
3.3.4.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.3.9.
3.4.
3.4.1.
3.4.2.
3.4.3.
3.4.4.
3.4.5.
3.4.6.
3.4.7.
3.4.8.
3.4.9.
3.4.10.
3.5.
3.6.
3.6.1.
3.6.2.
3.6.3.
3.7.
3.7.1.
3.7.1.1.
3.7.1.2.
3.7.1.3.
3.7.1.4.
3.7.1.5.
3.7.1.6.
3.7.2.
3.7.2.1.
3.7.2.2.
3.7.3.
Control Interfaces
I2C Bus Interface
Device and Subaddresses
Command Structure
The Internal Fixed Point Number Format
Conventions for the Command Description
Detailed MAS 3507D Command Syntax
Run
Read Control Interface Data
Write Register
Write D0 Memory
Write D1 Memory
Read Register
Read D0 Memory
Read D1 Memory
Default Read
Protocol Description
Run Command
Read Control Interface Data
Write to MAS 3507D Register
Write to MAS 3507D D0 Memory
Write to MAS 3507D D1 Memory
Read Register
Read D0 memory
Read D1 memory
Default Read
Write Data to the Control Register
Version Number
Register Table
DC/DC Converter
Muting / Bypass Tone Control
Bass and Treble Control
Memory Area
Status Memory
MPEG Frame Counter
MPEG Status 1
MPEG Status 2
CRC Error Counter
Number Of Ancillary Bits
Ancillary Data
Configuration Memory
PLL Offset for 44/48 kHz Sampling Frequency
Output Configuration
Baseband Volume Matrix
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
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4.
4.1.
4.2.
4.2.1.
4.2.1.1.
4.2.1.2.
4.2.1.3.
4.2.1.4.
4.2.1.4.1.
4.2.1.4.2.
4.2.1.5.
4.2.1.6.
4.2.1.7.
4.2.1.8.
4.2.2.
4.2.3.
4.2.4.
4.2.4.1.
4.2.4.2.
4.2.4.3.
4.2.4.3.1.
4.2.4.3.2.
4.2.4.3.3.
4.2.4.4.
4.2.4.4.1.
4.2.4.5.
4.2.4.6.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Power Supply Pins
DC/DC Converter Pins
Control Lines
Parallel Interface Lines
PIO Handshake Lines
PIO Data Lines
Voltage Supervision And Other Functions
Serial Input Interface
Serial Output Interface
Miscellaneous
Pin Configurations
Internal Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
I2C Characteristics
I2S Bus Characteristics – SDI
I2S Characteristics – SDO
Firmware Characteristics
Input Timing Parameters of the MultimediaMode
DC/DC Converter Characteristics
Typical Performance Characteristics
60
5.
Data Sheet History
4
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
MPEG 1/2 Layer 2/3 Audio Decoder
1.1. Features
Release Note: Revision bars indicate significant
changes to the previous edition.
This data sheet applies to MAS 3507D version G10
and following versions.
– Serial asynchronous MPEG bit stream input (SDI)
– Parallel (PIO-DMA) Input
– Broadcast and multimedia operation mode
– Automatic locking to given data rate in broadcast
mode
1. Introduction
The MAS 3507D is a single-chip MPEG layer 2/3 audio
decoder for use in audio broadcast or memory-based
playback applications. Due to embedded memories,
the embedded DC/DC up-converter, and the very low
power consumption, the MAS 3507D is ideally suited
for portable electronics.
In MPEG 1 (ISO 11172-3), three hierarchical layers of
compression have been standardized. The most
sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo
signals while still maintaining CD audio quality. Layer 2
(widely used in DVB, ADR, and DAB) achieves a compression of 8:1 providing CD quality.
In order to achieve better audio quality at low bit rates
(<64 kbit/s per audio channel), three additional sampling frequencies are provided by MPEG 2
(ISO 13818-3). The MAS 3507D decodes both layer 2
and layer 3 bit streams as defined in MPEG 1 and 2.
The multichannel/multilingual capabilities defined by
MPEG 2 are not supported by the MAS 3507D. An
extension to the MPEG 2 layer 3 standard developed
by FhG Erlangen, Germany sometimes referenced as
MPEG 2.5, for extremely low bit rates at sampling frequencies of 12, 11.025, or 8 kHz is also supported by
the MAS 3507D.
CLKI
CLKO
decoded output
/3/
– Output audio data delivered (in various formats) via
an I2S bus (SDO)
– Digital volume / stereo channel mixer / Bass / Treble
– Output sampling clocks are generated and controlled internally.
– Ancillary data provided via I2C interface
– Status information accessible via PIO pins or I2C
– “CRC Error” and “MPEG Frame Synchronization”
Indicators at Pins in serial input mode
– Power management for reduced power consumption
at lower sampling frequencies
– Low power dissipation (30 mW @ fs ≤ 12 kHz,
46 mW @ fs ≤ 24 kHz, 86 mW @ fs > 24 kHz @
2.7 V)
– Supply voltage range: 1.0 V to 3.6 V due to built-in
DC/DC converter (1-cell/2-cell battery operation)
– Adjustable power supply supervision
– Power-off function
– Additional functionality achievable via download
software (CELP voice Decoder, ADPCM encoder /
decoder)
MAS 3507D
DC/DC
Converter
Clock
Synthesizer
Serial Out
I2S
RISC DSP Core
MPEG 1/2
audio bit stream
/2/
– Data request triggered by ’demand signal’ in multimedia mode
PIO
/3/
/8+5/
serial control
I2C
Serial In
MPEG frame sync
/2/
CRC error
Fig. 1–1: MAS 3507D block diagram
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
1.2. Application Overview
A delayed response of the host to the demand signal
(by several milliseconds) or an interrupted response of
the host will be tolerated by the MAS 3507D as long as
the input buffer does not run empty. A PC might use its
DMA capabilities to transfer the data in the background
to the MAS 3507D without interfering with its foreground processes.
The MAS 3507D can be applied in two major environments: in multimedia mode or in broadcast mode. For
both modes, the DAC 3550A fits perfectly to the
requirements of the MAS 3507D. It is a high-quality
multi sample rate DAC (8 kHz ... 50 kHz) with internal
crystal oscillator, which is only needed for generating
the decoder clock, and integrated stereo headphone
amplifier plus 2 stereo inputs.
The source of the bit stream may be a memory (e.g.
ROM, Flash) or PC peripherals, such as CD-ROM
drive, an ISDN card, a hard disk or a floppy disk drive.
1.2.1. Multimedia Mode
1.2.2. Broadcast Mode
In a memory-based multimedia environment, the easiest way to incorporate a MAS 3507D decoder is to use
its data-demand pin. This pin can be used directly to
request input bit stream data from the host or memory
system.
In environments where the bit stream is delivered from
an independent transmitter to one or more receivers,
the MAS 3507D cannot act as master for the bit
stream clock. In this mode, it synchronizes itself to the
incoming bit stream data rate by a digital PLL and generates a synchronized digital audio sample clock for
the required output sample rates.
While the demand pin is active, the data stream shall
be transmitted to the MAS 3507D. The bit stream clock
should be higher than the actual data rate of the
MPEG bit stream (1 MHz bit stream clock works with
all MPEG bit rates). The demand signal will be active
until the input buffer of the MAS 3507D is filled.
I2C
Host
(PC, Controller)
14.725 MHz
demand signal
demand clock
I2S
MAS 3507D
line out
DAC
3550A
MPEG bit stream
CLKI
CLKOUT
ROM, CD-ROM,
RAM, Flash Mem. ..
Fig. 1–2: Block diagram of a MAS 3507D, decoding a stored bit stream in multimedia mode
control I2C
Receiver
L3 bit stream
(fixed rate)
Front-end
14.725 MHz
2
I S
MAS 3507D
DAC
3550A
line out
clock
CLKI
CLKOUT
Fig. 1–3: Block diagram of a MAS 3507D in a broadcast environment
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Micronas
MAS 3507D
PRELIMINARY DATA SHEET
2. Functional Description of the MAS 3507D
2.2. Firmware (Internal Program ROM)
2.1. DSP Core
A valid MPEG 1/2/2.5 layer 2/3 data signal is taken as
input. The signal lines are a clock line SIC and the data
line SID. The MPEG decoder performs the audio
decoding. The steps for decoding are
The hardware of the MAS 3507D consists of a high
performance RISC Digital Signal Processor (DSP) and
appropriate interfaces (see Fig. 2–1). The internal processor works with a memory word length of 20 bits
and an extended range of 32 bits in its accumulators.
The instruction set of the DSP is highly optimized for
audio data compression and decompression. Thus,
only very small areas of internal RAM and ROM are
required. All data input and output actions are based
on a ‘non cycle stealing’ background DMA that does
not cause any computational overhead.
MPEG Bit Stream
Digital Audio Output
Volume
Tone
Control
– synchronization,
– side information extraction,
– audio data decoding,
– ancillary data extraction, and
– volume and tone control.
For the supported bit rates and sample rates, see
Table 3–12 on page 32. Frame synchronization and
CRC-error signals are provided at the output pins of
the MAS 3507D in serial input mode.
Sync
Ancillary
Data
MPEG
Decoder
Decoder
Status
to µC
Config. Reg.
PIO
Status
Start-up Config.
Fig. 2–1: Block diagram of the MPEG Decoder in serial input mode
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
2.3. Program Download Feature
2.4. Baseband Processing
This is an additional feature that is not required for the
MPEG decoding function.
2.4.1. Volume Control / Channel Mixer
The overall function of the MAS 3507D can be altered
by downloading up to 1 kWord program code into the
internal RAM and executing this code instead of the
ROM code. During this time, MPEG decoding is not
possible.
The code must be downloaded by the ‘write to memory’ command (see Section 3.3.) into an area of RAM
that is switchable from data memory to program memory. A ‘run’ command (see Section 3.3.1.) starts the
operation.
Micronas provides modules for voice-decoding using
the CELP algorithm (performing good speech quality
at very low bit rates) and for encoding and decoding
audio data with ADPCM.
Detailed information about downloading is provided in
combination with the MAS 3507D software development package from Micronas.
For commercial issues and detailed information please
contact our sales department.
A digital volume control matrix is applied to the digital
stereo audio data. This performs additional balance
control and a simple kind of stereo basewidth
enhancement. The 4 factors LL, LR, RL, and RR are
adjustable via the controller with 20-bit resolution. See
Fig. 3–2 and Section 3.7.3. for details.
2.4.2. Mute / Bypass Tone Control
A special bit enables a fast and simple mute functionality without changing the current volume setting.
Another bit allows to bypass the complete bass / treble
/ volume control. See for details Section 3.6.2.
2.4.3. Bass / Treble Control
Tone control is implemented in the MAS 3507D. It
allows the control of bass and treble in a range up to
±15 dB, as Table 3–9 shows. To prevent overflow or
clipping effects, the prescaler is built-in. The prescaler
decreases the overall gain of the tone filter, so the full
range up to +15 dB is usable without clipping.
Due to the different frequency ranges in MPEG 1,
MPEG 2, or MPEG 2.5, the bass cutoff frequencies differ.
Table 2–1: Cutoff Frequencies
Cutoff
Bass
Treble
MPEG 1
100 Hz
10 kHz
MPEG 2
200 Hz
10 kHz
MPEG 2.5
400 Hz
10 kHz
For details see Section 3.6.3..
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Micronas
MAS 3507D
PRELIMINARY DATA SHEET
2.5. Clock Management
2.6.2. DC/DC Converter
The MAS 3507D should be driven by a single clock at
a frequency of 14.725 MHz. It is possible to drive the
MAS 3507D with other reference clocks (see Section
3.7.2.1. on page 36).
The DC/DC converter of the MAS 3507D is used to
generate a fixed power supply voltage even if the chip
set is powered by battery cells in portable applications.
The DC/DC converter is designed for the application of
1 or 2 batteries or NiCd cells as shown in Fig. 2–3
which shows the standard application circuit. The DC/
DC converter is switched on by activating the DCEN
pin. Its output power is sufficient for other ICs as well.
The CLKI signal acts as a reference for the embedded
clock synthesizer that generates the internal system
clock. Based on the reference input clock CLKI, a synchronized output clock CLKO that depends on the
audio sample frequency of the decompressed bit
stream is generated and provided as ‘master clock’ to
external D/A converters. Some of them need master
clocks that have a fixed relation to the sampling frequencies. A scaler can be switched on during start-up,
optionally, by setting the PI8 pin to 0. Then, the clock-out
will automatically be divided by 1, 2, or 4 as defined in
Table 2–2.
Table 2–2: CLKO Frequencies
fs/kHz
CLKO/MHz
scaler on
CLKO/MHz
scaler off
48, 32
24.576
24.576
44.1
22.5792
22.5792
24, 16
12.288
24.576
22.05
11.2896
22.5792
12, 8
6.144
24.576
11.025
5.6448
22.5792
2.6. Power Supply Concept
The MAS 3507D offers an embedded controlled DC/
DC converter for battery based power supply concepts. It works as an up-converter.
Note: Connecting DCEN directly to VDD leads to
unexpected states of the DCCF register.
The PUP signal should be read out by the system controller.
A 22 µH inductor is required for the application. The
important specification item is the inductor saturation
current rating, which should be greater than 2.5 times
the DC load current. The DC resistance of the inductor
is important for efficiency. The primary criterion for
selecting the output filter capacitor is low equivalent
series resistance (ESR), as the product of the inductor
current variation and the ESR determines the high-frequency amplitude seen on the output voltage. The
Schottky diode should have a low voltage drop VD for a
high overall efficiency of the DC/DC converter. The
current rating of the diode should also be greater than
2.5 times the DC output current. The VSENS pin has
to be always connected to the output voltage.
2.6.3. Stand-by Functions
The digital part of the MAS 3507D and the DC/DC
converter are turned on by setting WSEN. If only the
DC/DC converter should work, it can remain active by
setting DCEN alone to supply other parts of the application even if the audio decoding part of the
MAS 3507D is not being used. The WSEN power-up
pin of the digital part may be handled by the controller.
Please pay attention to the fact, that I2C protocol is
working only if the processor and its interfaces works
(WSEN = 1)
2.6.1. Internal Voltage Monitor
An internal voltage monitor compares the input voltage
at the VSENS pin with an internal reference value that
is adjustable via I2C bus. The PUP output pin becomes
inactive when the voltage at the VSENS pin drops
below the programmed value of the reference voltage.
It is important that the WSEN must not be activated
before the PUP is generated. The PUP signal thresholds are listed in Table 3–8. The internal voltage monitor will be activated with a high level at Pin DCEN.
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
2.6.4. Start-up Sequence
µController
The DC/DC converter starts from a minimum input
voltage of 0.9 V. There should be no output load during
startup. In case WSEN is active, the MAS 3507D is in
the DSP operation mode. The start-up script should be
as follows:
DSP
operation
=1
1. Enable the DC/DC-converter with a high signal
(VDD, AVDD) at pin DCEN.
WSEN > 2 V
2. Wait until PUP goes “high”.
3. Wait one more millisecond to guarantee that the output voltage has settled (recommended).
DC/DC
On
> 0.9 V
DCEN
button
4. Enable the MAS 3507D with a “high” signal at pin
“WSEN”.
Fig. 2–2: DC/DC operation
Please also refer to Figure 2–2.
CLKI
VDD
optional
filter
AVDD
22 µH
DCSO
Start-up
oscillator
DCSG
Frequency
divider
64...94
DCEN
x2
32...47
voltage monitor
WSEN
DCCF
$8e
Power-On
Push Button
Cout
330 µF
Low ESR
Cin
330 µF
PUP
+32
0...15
9
+
−
DC/DC
converter
+
−
Vin
≥0.9 V
10 kΩ
VSENSE
10
16
VSS
AVSS
10 nF
47 kΩ 47 kΩ
µController
Fig. 2–3: DC/DC converter connections
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Micronas
MAS 3507D
PRELIMINARY DATA SHEET
2.7. Interfaces
The MAS 3507D uses an I2C control interface,
2 selectable serial input interfaces for MPEG bit
stream (SDI, SDI*) , a parallel I/O interface (PIO) for
MPEG- or ADPCM-data and a digital audio output
interface (SDO) for the decoded audio data (I2S or
similar). Additionally, the parallel I/O interface (PIO)
may be used for monitoring and mode selection tasks.
The PIO lines are defined by the internal firmware.
The MPEG input signal format is shown in Fig. 2–4.
The data values are latched with the falling edge of the
SIC signal.
The MPEG bit stream generated by an encoder is
unformatted. It will be formatted (e.g. 8 bit or 16 bit) by
storing on a media (Flash-RAM, Harddisk). The serial
data required from the MPEG bit stream interface must
be in the same bit order as produced by the encoder.
2.7.2. SDI* Selection
2.7.1. MPEG Bit Stream Interface (SDI)
The MPEG bit stream input interface uses the three
pins: SIC, SII, and SID. For MPEG decoding operation,
the SII pin must always be connected to VSS.
The serial interface has to be initialized before the
first use. Otherwise no output signal is produced.
After Power-up or a rising slope on Pin PORQ, write
the following I2C-command, while SIC is hold low:
W $3A 68 93 B0 00 02
(write $0020 into register $3B)
An alternative serial input (SDI*) is available. The alternative serial input can be selected by setting register
SI1M0 at address $4f (see Table 2–3).
Table 2–3: SDI* Selection via Register SI1M0,
$4f (write)
Value
Function
0
use SDI lines
2
use PI14...PI16 pins for
serial input (named SDI*)
W $3A 68 00 01
(execute “RUN 1” command)
Vh
SIC
Vl
Vh
data valid
latch data at falling edge of clock
SII
Vl
Vh
SID
Vl
Fig. 2–4: Schematic timing of the SDI (MPEG) input
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
2.7.3. Parallel Input Output Interface (PIO)
The parallel interface of the MAS 3507D uses the lines
PI0...PI4, PI8, PI12...PI19, and several control lines.
2.7.3.1. PIO-DMA Input Mode
.
Table 2–4: Switching from SDI- to PIO-DMA-Input
Address 1)
Value
$e6, Bit 4
1
1)
Startup Configuration Register
By setting the PIO pin PI4 to “1”, the PIO-DMA input
mode of the MAS 3507D is activated after reset.
Normally, the input mode should not be altered in a
customer’s application. Should this nonetheless be
desired, the necessary changes are described in
Table 2–4 and Table 2–5.
2.7.3.2. Writing MPEG Data to the PIO-DMA
The PIO-DMA mode enables the writing of 8-bit parallel MPEG data to the MAS 3507D. In this mode, PIO
lines PI19...PI12 are switched to the MAS 3507D data
input which hence will be an 8-bit parallel input port
with MSB first (at position PI19) for the MPEG bit
stream data. In order to write data to this parallel port
successfully, a special handshake protocol has to be
used by the controller (see Fig. 2–5).
Table 2–5: Switching from PIO-DMA- to SDI-Input
Step
Address 1)
Value
1
$e6, Bit 4
0
2
$4b
$82
1)
PIO Configuration Register
Note: These 2 steps must be done in above
order!
Note: Either SII has to be set to “1”, or SIC clock input
has to be stopped (“0”) in this mode.
.
tst
tr
trtrq
trpr
teod
teodq
tpd
high
EOD
low
high
tpr
PR
low
high
low
RTR
tset
PI[19:12]
Byte 1
th
high
low
Byte 15
MAS 3507D latches the PIO DATA
Fig. 2–5: Handshake protocol for writing MPEG data to the PIO-DMA
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Micronas
MAS 3507D
PRELIMINARY DATA SHEET
Table 2–6: PIO DMA Timing
2.7.3.3. DMA Handshake Protocol
The data transfer can be started after the EOD pin of
the MAS 3507D is set to “high”. After verifying this, the
controller signalizes the sending of data by activating
the PR line. The MAS 3507D responds by setting the
RTR line to the “low” level. The MAS 3507D reads the
data PI[19:12] tpd ns after rising edge of the PR. The
next data word write operation will again be initialized
by setting the PR line via the controller. Please refer to
Figure 2–5 and Table 2–6 for the exact timing
Symbol
PIO Pin
tst
PR, EOD
0.010
2000
µs
tr
PR, RTR
40
160
ns
tpd
PR,
PI[19:12]
120
480
ns
tset
PI[19:12]
160
no limit
ns
2.7.3.4. End of DMA Transfer
th
PI[19:12]
160
no limit
ns
The above procedure will be repeated until the
MAS 3507D sets the EOD signal to “0”, which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to
“0”, wait until EOD rises again, and then repeat the
procedure (see Section 2.7.3.3. ) to send the next
block of data. The DMA buffer is 15 bytes long.
trtrq
RTR
200
30000
ns
tpr
PR
120
no limit
ns
trpr
PR, RTR
40
no limit
ns
teod
PR, EOD
40
160
ns
teodq
EOD
0
500
µs
The recommended PIO-DMA conditions and the characteristics of the PIO timing are given in Table 2–6
Min.
Max.
Unit
2.7.4.1. Mode 1: 16 Bits/Sample
(I2S Compatible Data Format)
2.7.4. Audio Output Interface (SDO)
The audio output interface of the MAS 3507D is a
standard I2S interface. It is possible to choose between
two standard interfaces (16 bit with delay or 32 bit without delay and inverted SOI) via start-up configuration.
These setup modes meet the performance of the most
common DACs. It is also possible to select other interface modes via I2C commands (see Section 2.7.4.3.).
A schematic timing diagram of the SDO interface in
16 bit/sample mode is shown in Fig. 2–6.
.
Vh
SOC
Vl
Vh
SOD
SOI
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Vl
Vh
Vl
left 16-bit audio sample
right 16-bit audio sample
Fig. 2–6: Schematic timing of the SDO interface in 16 bit/sample mode
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2.7.4.2. Mode 2:32 Bit/Sample (Inverted SOI)
2.7.4.3. Other Output Modes
If the serial output generates 32 bits per audio sample,
only the first 20 bits will carry valid audio data. The 12
trailing bits are set to zero by default (see Fig. 2–7)
The interface is also configurable by software to work
in different modes. It is possible to choose:
The 12 trailing bits for left and right channel of the SDO
interface can be accessed by writing to registers as
shown in Table 2–7.
– inverted or noninverted word strobe (SOI),
– 16 or 32 bit/sample modes,
– no delay or delay of data related to word strobe
– inverted or noninverted I2S-Clock (SOC).
Table 2–7: Access for Trailing Bits
Register
Bit 0 ... 11
$c5
Left Channel
$c6
Right Channel
Vh
SOC
For further details see Section 3.7.2.2.
...
...
Vl
Vh
SOD
31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0
Vl
Vh
SOI
Vl
left 32-bit audio sample
right 32-bit audio sample
Fig. 2–7: Schematic timing of the SDO interface in 32 bit/sample mode
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2.8. Start-up Configuration
Basic operation of the MAS 3507D is possible without
controller interaction. Configuration and the most
important status information are available by the PIO
interface. The start-up configuration is selected
according to the levels of several PIO pins. The levels
should be set via high impedance resistors (for example 10 kΩ) to VSS or VDD and will be copied into the
StartupConfig register directly after power up / reset.
After start-up, the PIO will be reconfigured as output.
To enable greater flexibility, it is possible to configure
the MAS 3507D without using the PIO pins or to reconfigure the IC after start-up. The procedure for this is to
send two I2C commands to the MAS 3507D:
– Writing the StartupConfig register (see Section 3.6.
on page 26)
– Execute a ‘run $0fcd’ command (see
Section 3.3.1.).
The configuration will be active up to a reset. Then, the
new configuration will be loaded again via PIO.
Table 2–8: Start-up configuration1)
PIO
Pin
“0”
“1”
PI8
divide CLKO by 1,
2, or 4 (according
to MPEG 1, 2, or
2.5)
CLKO fixed at
24.576 or
22.5792 MHz
PI4
SDI input mode
PIO-DMA input
mode
PI3
Enable layer 3
Disable layer 3
PI2
Enable layer 2
Disable layer 2
PI1
SDO output: 32 bit
SDO output: 16 bit
PI0
input: Multimedia
mode (PLL off)
input: Broadcast
mode (PLL on)
1) Start-up setting can be changed by I2C commands
after reset.
2.8.1. Parallel Input Output Interface (PIO)
During start-up, the PIO will read the start-up configuration. This is to define the environment for the
MAS 3507D. The following pins must be connected via
resistors to VSS or VDD:
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2.9. Status Pins in SDI Input Mode
Table 2–9: PIO output signals during MPEG decoding
in SDI mode
After having read the start-up configuration, the PIO
will be switched to ‘µP-mode’. In µP-mode, the additional PIO control lines (PR, PCS) are evaluated. If the
MPEG decoder firmware detects PR = ‘1’ and the
PCS = ‘0’. Then, all PIO interface lines are configured
as output and display some status information of the
MPEG decoder. The PIO lines can be read by an
external controller or directly used by dedicated hardware blocks (e.g. for sample rate indication or display
units). The internal MPEG decoder firmware attaches
specific functions to the following pins.
PIO
Pin
Name
PI19
Demand PIN
%0
%1
The MPEG-FRAME-SYNC signal is set to ‘1’ after the
internal decoding for the MPEG header has been finished for one frame. The rising edge of this signal
could be used as an interrupt input for the controller
that triggers the read out of the control information and
ancillary data. As soon as the MAS 3507D has recognized the corresponding read command (‘read control
interface data’ (see Section 3.3.2. on page 21), the
MPEG-FRAME-SYNC is reset. This behavior reduces
the possibility of missing the MPEG-FRAME-SYNC
active state.
PI18,
PI17
MPEG INDEX
PI13,
PI12
MPEG Layer ID
PI8
MPEG CRC-ERROR
%00
%01
%10
%11
%00
%01
%10
%11
%0
%1
tframe=24 ... 72 ms
tread
PI4
Vh
Comment
no input data exp.
input data request
MPEG 2.5
reserved
MPEG 2
MPEG 1
reserved
Layer 3
Layer 2
Layer 11)
no error
CRC-error,
MPEG decoding
not successful
MPEG-FRAMESYNC
see following text
PI3,
PI2
Sampling frequency
in kHz2)
%00
%01
%10
%11
44.1 / 22.1 / 11.0
48 / 24 / 12
32 / 16 / 8
reserved
PI1,
PI0
Deemphasis
l
MPEG-FRAME-SYNC
Fig. 2–8: Schematic timing of MPEG-FRAME-Sync
The time tread depends on the response time of the
controller. This time must not exceed 1/2 of the MPEGframe length tframe. The MPEG frame lengths are given
in Table 2–10
1)
2)
%00
%01
%10
%11
none
50/15 µs
reserved
CCITT J.17
Layer 1 bit streams will not be decoded
Sampling frequency also defined by MPEG index
(see Table 3–12 for additional information)
.
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Table 2–10: Frame length in MPEG layer 2 / 3
fs in
kHz
Frame Length
Layer 2
Frame Length
Layer 3
48
24 ms
24 ms
44.1
26.12 ms
26.12 ms
32
36 ms
36 ms
24
24 ms
24 ms
22.05
26.12 ms
26.12 ms
16
32 ms
32 ms
12
not available
48 ms
11.025
not available
52.24 ms
8
not available
72 ms
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By means of the RESET bit in the CONTROL register,
the MAS 3507D can be reset by the controller.
3. Control Interfaces
3.1. I2C Bus Interface
Due to the internal architecture of the MAS 3507D, the
IC cannot react immediately to an I2C request. The
typical response time is about 0.5 ms. If the
MAS 3507D cannot accept another complete byte of
data until it has performed some other function (for
example, decoding MP3 data), it will hold the clock line
I2C_CL LOW to force the transmitter into a wait state.
The positions within a transmission where this may
happen are indicated by ’Wait’ in section 3.4. The maximum wait period of the MAS 3507D during normal
operation mode is less than 4 ms.
3.1.1. Device and Subaddresses
The MAS 3507D is controlled via the I2C bus slave
interface.
The IC is selected by transmitting the MAS 3507D
device addresses. (see Table 3–1).
Writing is done by sending the device write address,
($3a) followed by the subaddress byte ($68), two or
more bytes of data. Reading is done by sending the
write device address ($3a), followed by the subaddress byte ($69). Without sending a stop condition,
reading of the addressed data is completed by sending
the device read address ($3b) and reading n-bytes of
data.
Table 3–1: I2C Bus Device Addresses
MAS 3507D Device
Address
Write
Read
MAS_I2C_ADR
$3a
$3b
Table 3–2: I2C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL_MAS
0000 0000
$6a
Write
control subaddress (see Table 3–3)
WR_MAS
0110 1000
$68
Write
write subaddress
RD_MAS
0110 1001
$69
Write
read subaddress
Table 3–3: Control Register (Subaddress: $6a)
Name
Subaddress
Bit : 8
Bit : 0-7, 9-15
CONTROL
$6a
1 : Reset
0 : normal
0
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Note: S =
P=
ACK =
NAK =
Wait =
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
Acknowledge-Bit: LOW on I2C_DA from slave or master
Not Acknowledge-Bit: HIGH on I2C_DA from master to indicate ‘End of Read’
I2C-Clock line is held low, while the MAS 3507D is processing the I2C command.
1
0
I2C_DA
S
P
I2C_CL
Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.2. Command Structure
3.2.1. The Internal Fixed Point Number Format
The I2C control of the MAS 3507D is done completely
via the I2C data register by using a special command
syntax. The commands are executed by the
MAS 3507D during its normal operation without any
loss or interruption of the incoming data or outgoing
audio data stream. These I2C commands allow the
controller to access internal states, RAM contents,
internal hardware control registers, and even a download of an alternative software module. The command
structure allows sophisticated control of the
MAS 3507D. The registers of the MAS 3507D are
either general purpose, e.g. for program flow control,
or specialized registers that directly affect hardware
blocks. The unrestricted access to these registers
allows the system controller to overrule the firmware
configuration of the serial interfaces or the default input
line selection.
Internal register or memory values can easily be
accessed via the I2C interface. In this document, two
number representations are used: the fixed point notation ‘v’ and the 2’s complement number notation ‘r’.
The conversion between the two forms of notation is
easily done (see the following equations).
r = v x 524288.0 + 0.5; (−1.0 ≤ v < 1.0)
(EQ 1)
v = r / 524288.0; (−524288 < r < 524287)
(EQ 2)
The control interface is also used for low bit rate data
transmission, e.g. MPEG-embedded ancillary data
transmission. The data information is performed by
sending a ‘read memory’ command to the MAS 3507D
and by reading the memory block that temporarily contains the required information. The synchronization
between the controller and the MAS 3507D is done via
a MPEG-FRAME-SYNC signal or by monitoring the
MPEGFrameCount register (at the cost of a higher
work load for the controller).
The MAS 3507D firmware scans the I2C interface periodically and checks for pending or new commands.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected. The theoretical worst case response time
does not exceed 4 ms. Table 3–4 shows the basic controller commands that are available by the
MAS 3507D.
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3.2.2. Conventions for the Command Description
3.3. Detailed MAS 3507D Command Syntax
The description of the various controller commands
uses the following formalism:
3.3.1. Run
– A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble.
– Data values in nibbles are always shown in hexadecimal notation indicated by a preceding $.
– A hexadecimal 20-bit number d is written, e.g. as
d = $17C63, its five nibbles are
d0 = $3, d1 = $6, d2 = $C, d3 = $7, and d4 = $1.
– Abbreviations used in the following descriptions:
a address
d data value
n count value
o offset value
r register number
x don’t care
– Variables used in the following descriptions:
dev_write
$3a
dev_read
$3b
data_write $68
data_read $69
control
$6a
S
dev_write
A
data_write
A
a3,a2
A
a1,a0
A P
The ‘run’ command causes the start of a program part
at address a = (a3,a2,a1,a0). The nibble a3 is
restricted to $0 or $1 which also acts as command
selector. Run with address a = $0 will suspend normal
MPEG decoding and only I2C commands are evaluated. This freezing will be required if alternative software is downloaded into the internal RAM of the
MAS 3507D. Detailed information about downloading
is provided in combination with a MAS 3507D software
development package or together with MAS 3507D
software modules available from Micronas.
If the address $1400 ≤ a < $1800, the MAS 3507D
continues execution of the program with the downloaded code. For detailed information, please refer to
the MASC software development kit. This is for starting
the downloaded program code.
Example 1: ‘run’ at address $fcd (override start-up
configuration) has the following I2C protocol:
<$3a><$68><$0f><$cd>
Example 2: ‘run’ at address $475 (activate PLLOffset
and OutputConfig after change by write command) has
the following I2C protocol:
<$3a><$68><$04><$75>
Table 3–4: Basic controller commands
Code
Command
Comment
$0
$1
run
Start execution of an internal program. (Run 0 means freeze operating system.)
$3
read Control Information and Ancillary Data
fast read of a block of information organized in 16-bit words (see Section
3.7.1. on page 30)
$9
write register
An internal register of the MAS 3507D can be written directly to by the controller.
$A
$B
write to memory
A block of the DSP memory can be written to by the controller. This feature
may be used to download alternate programs.
$D
read register
The controller can read an internal register of the MAS 3507D.
$E
$F
read memory
A block of the DSP memory can be read by the controller.
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act with built-in hardware blocks. A list of useful registers is given in the next section.
3.3.2. Read Control Interface Data
1) send command
S
dev_write
A
A S
data_write
$3, x2
A
A P
x1,x0
<$3a><$68><$9a><$a1><$00><$00>
2) get ancillary data values
S
dev_write
A
Example: Muting can be realized by writing the value 1
into the register with the number $aa:
A S
(ancillary word 0)
A
data_read
dev_read
d3, d2
A
3.3.4. Write D0 Memory
d1,d0
....repeat for n data values....
A
d3, d2
A
d1,d0
Nak
P
x2...x0: combined count, offset value
d3...d0: 16-bit data values
An internal memory array keeps the status information
of the MAS 3507D (see Table 3–10). The ‘read control
interface data’ command can be used for quick access
to this memory array. A successive range of memory
locations may be read by passing a 6-bit offset value
“o” and a 6-bit count value “n” as parameter.
Both values are combined in a 12-bit = 4 nibble field
x2, x1, x0. If, for example, 4 words (n = 4) starting with
one word offset (o = 2), i.e. the MPEG Status 2, the
CRCErrorCount, and NumberOfAncillaryBits are read
from the control memory array, the 3 nibbles x2, x1 and
x0 are evaluated as shown in the following table.
11
10
6-bit values
offset: 2
bit
0
nibble
0
0
9
8
7
6
5
4
3
2
1
0
number of words: 3
0
0
1
0
0
0
8
0
0
1
1
3
S
dev_write
A
data_write
A
A
A
A
A
$A, $0
n3,n2
a3,a2
n3,n2
d3,d2
$0,$0
A
A
A
A
A
$0,$0
n1,n0
a1,a0
d1,d0
$0,d4
....repeat for n data values....
A
A
n3,n2
d3,d2
$0,$0
A
A
d1,d0
$0,d4
A P
n3..n0: number of words
a3..a0: start address in MASD memory
d4..d0: data value
The MAS 3507D has 2 memory areas of 2048 words
each called D0 and D1 memory. For both memory
areas, read and write commands are provided.
Example: reconfiguration of the output to 16 bit without
delay has the following I2C protocol:
<$3a><$68><$a0><$00>
<$00><$01>
<$03><$2f>
<$00><$10>
<$00><$00>
<$3a><$68><$04><$75>
(write D0 memory)
(1 word to write)
(start address)
(value = $00010)
(run command)
The complete I2C protocol reads as:
3.3.5. Write D1 Memory
<$3a><$68><$30><$83>
<$3a><$69><$3b><receive 3 16-bit data values>
The ‘read control interface data’ command resets the
MPEG-FRAME-SYNC at PI4 pin (see Section 2.9. on
page 16).
3.3.3. Write Register
S
dev_write
A
data_write
dev_write
A
data_write
A
A
A
A
A
$B, $0
n3,n2
a3,a2
n3,n2
d3,d2
$0,$0
A
A
A
A
A
$0,$0
n1,n0
a1,a0
d1,d0
$0,d4
....repeat for n data values....
A
$9, r1
d4, d3
A
A
r0, d0
d2, d1
A
A P
The
controller
writes
the
20-bit
value
(d = d4,d3,d2,d1,d0) into the MAS 3507D register
(r = r1,r0). In contrast to memory cells, registers are
always addressed individually, and they may also inter-
Micronas
S
A
A
n3,n2
d3,d2
$0,$0
A
A
d1,d0
$0,d4
A P
n3..n0: number of words to be transmitted
a3..a0: start address in MASD memory
d4..d0: data value
For further details, see ‘write D0 memory’ command.
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3.3.6. Read Register
3.3.8. Read D1 Memory
1) send command
1) send command
S
dev_write
A
data_write
A
$D, r1
A
r0,$0
A P
S
dev_write
A
data_write
2) get register value
S
dev_write
A
A
data_read
d3, d2
A
A S
A
dev_read
d1,d0
X,X
A
X, d4
Nak
P
dev_write
A
A
Example:
Read the content of the PIO data register ($c8):
<$3a><$68><$dc><$80>
<$3a><$69><$3b>
now read:
<d3,d2><d1,d0><x,x><x,d4>
1) send command
A
data_write
A
A
A
$E, $0
n3,n2
a3,a2
A
A
A
$0,$0
n1,n0
a1,a0
A P
2) get memory value
S
dev_write
A
A
a3,a2
A
A
A
$0,$0
n1,n0
a1,a0
A P
A
A S
A d1,d0 A
data_read
d3, d2
dev_read
$0,$0
A
$0, d4
A S
A d1,d0 A
data_read
d3, d2
d3, d2
A
d1,d0
A
$0,$0
A
$0, d4
NaK P
n3..n0: number of words
a3..a0: start address in MASD memory
d4..d0: data value
The ‘read D1 memory’ command is provided to get
information from memory cells of the MAS 3507D. It
gives the controller access to all memory cells of the
internal D1 memory.
3.3.9. Default Read
S
3.3.7. Read D0 Memory
dev_write
n3,n2
....repeat for n data values....
The MAS 3507D has an address space of 256 registers. Some of the registers (r = r1,r0 in the figure
above) are direct control inputs for various hardware
blocks, others do control the internal program flow. In
the next section, those registers that are of any interest
with respect to the MPEG decoding are described in
detail.
S
$F, $0
2) get memory value
S
r1, r0: register r
d3...d0: data value in r
X:
don’t care
A
A
A
dev_write
A
data_read
A S
A
device_read
d3,d2
A
d1,d0
Nak
P
The ‘default read’ command immediately returns the
content of the MPEGFrameCount (D0:$300) of the
MAS 3507D in the variable (d = d3,d2,d1,d0). The
‘default read’ command is the fastest way to get information from the MAS 3507D. Executing the ‘default
read’ command in a polling loop can be used to detect
the availability of new ancillary data.
dev_read
$0,$0
A
$0, d4
....repeat for n data values....
A
d3, d2
A
d1,d0
A
$0,$0
A
$0, d4
NaK P
n3..n0: number of words
a3..a0: start address in MASD memory
d4..d0: data value
The ‘read D0 memory’ command is provided to get
information from memory cells of the MAS 3507D. It
gives the controller access to all memory cells of the
internal D0 memory. Direct access to memory cells is
an advanced feature of the DSP. It is intended for users
of the MASC software development kit.
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3.4. Protocol Description
3.4.1. Run Command
S
$3A
ACK
$68
ACK
a3, a2
ACK
a1, a0
Wait ACK P
ACK
x1, x0
Wait ACK P
3.4.2. Read Control Interface Data
Send Command
S
$3A
ACK
$68
ACK
$3, x2
ACK
S
$3B
Wait
ACK
d3, d2
ACK
Get Ancillary Data Values
S
$3A
ACK
$69
d1, d0
Wait
.... repeat for n data values
ACK
d3, d2
ACK
d1, d0
Wait Nak
P
3.4.3. Write to MAS 3507D Register
S
$3A
ACK
$68
ACK
$9,r1
ACK
r0,d0
Wait ACK
d4,d3
ACK
d2,d1
Wait ACK P
3.4.4. Write to MAS 3507D D0 Memory
S
$3A
ACK
$68
ACK
$A, $0
ACK
$0, $0
Wait
ACK
n3, n2
ACK
n1, n0
Wait
ACK
a3, a2
ACK
a1, a0
Wait
ACK
d3, d2
ACK
d1, d0
Wait
ACK
$0, $0
ACK
$0, $d4
Wait
.... repeat for n data values
Micronas
ACK
d3, d2
ACK
d1, d0
Wait
ACK
$0, $0
ACK
$0, $d4
Wait
Ack
P
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3.4.5. Write to MAS 3507D D1 Memory
S
$3A
ACK
$68
ACK
$B, $0
ACK
$0, $0
Wait
ACK
n3, n2
ACK
n1, n0
Wait
ACK
a3, a2
ACK
a1, a0
Wait
ACK
d3, d2
ACK
d1, d0
Wait
ACK
$0, $0
ACK
$0, $d4
Wait
.... repeat for n data values
ACK
d3, d2
ACK
d1, d0
Wait
ACK
$0, $0
ACK
$0, $d4
Wait
$68
ACK
$D, r1
ACK
r0, $0
Wait ACK P
$69
ACK
S
$3B
Wait
ACK
d3, d2
ACK
d1, d0
Wait
ACK
X, X
ACK
X, d4
Wait Nak
Ack
P
3.4.6. Read Register
Send command
S
$3A
ACK
Get register value
S
$3A
ACK
P
3.4.7. Read D0 memory
Send Command
S
$3A
ACK
$68
ACK
$E, $0
ACK
$0, $0
Wait
ACK
n3, n2
ACK
n1, n0
Wait
ACK
a3, a2
ACK
a1, a0
Wait ACK P
ACK
S
$3B
Wait
ACK
d3, d2
ACK
Get memory values
S
$3A
ACK
$69
d1, d0
Wait ACK
$0, $0
ACK
$0, d4
Wait
ACK
d1, d0
Wait Nak
.... repeat for n data values
ACK
d3, d2
ACK
d1, d0
Wait ACK
d3, d2
P
3.4.8. Read D1 memory
Send Command
S
24
$3A
ACK
$68
ACK
$F, $0
ACK
$0, $0
Wait
ACK
n3, n2
ACK
n1, n0
Wait
ACK
a3, a2
ACK
a1, a0
Wait ACK P
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Get memory values
S
$3A
ACK
$69
ACK
S
$3B
Wait
ACK
d3, d2
ACK
d1, d0
Wait ACK
$0, $0
ACK
$0, d4
Wait
ACK
d1, d0
Wait Nak
.... repeat for n data values
ACK
d3, d2
ACK
S
$3B
Wait
ACK
d3, d2
ACK
d1, d0
Wait ACK
d3, d2
d1, d0
Wait Nak
P
P
3.4.9. Default Read
S
$3A
ACK
$69
ACK
3.4.10.Write Data to the Control Register
S
$3A
ACK
$6A
ACK
d3, d2
ACK
d1, d0
Wait ACK P
3.5. Version Number
Table 3–5 shows where the MAS 3507D hardware version, its software and additional information is located.
Table 3–5: MAS 3507D Version
Addr.
Content
Example Value
D1:$ff6
name of
MAS 3507D version
0x03507
3507
D1:$ff7
hardware/software
design code
MAS 3507D F10
0x00601
(increases
for new
versions)
0601
D1:$ff9
description:
“MPEG 1/2.5 L23”
0x04d50
MP
D1:$ffa
0x04547
EG
D1:$ffb
0x02031
1
D1:$ffc
0x02f32
/2
D1:$ffd
0x02e35
.5
D1:$ffe
0x0204C
L
D1:$fff
0x03233
23
Micronas
25
MAS 3507D
PRELIMINARY DATA SHEET
3.6. Register Table
3.6.1. DC/DC Converter
In Table 3–6, the internal registers that are useful for
controlling the MAS 3507D are listed. They are accessible by ‘register read/write’ I2C commands (see Section 3.3. on page 20).
The DCCF Register controls both the internal voltage
monitor and DC/DC converter. Between output voltage
of the DC/DC converter and the internal voltage monitor threshold an offset exists which is shown in the following table. Please pay attention to the fact, that I2C
protocol is working only if the processor is active
(WSEN = 1). However, the setting for the DCCF register will remain active if the DCEN and WSEN lines are
deasserted
Important note! Writing into undocumented registers
or read-only registers is always possible, but it is highly
recommended not to do so. It may damage the function of the firmware and may even lead to a complete
system crash of the decoder operation which can only
be restored by a reset.
Table 3–6: Command Register Table
Address
R/W
Name
Comment
Default
$8e
w
DCCF
Set DC/DC converter mode
(see Table 3–7 on page 27)
$08000
$aa
r/w
Mute / Bypass
Tone Control
Forces a mute of the digital output
bypass Bass / Treble / Volume matrix
$0
$ed1)
r
PIOData
Read back the PIO pin levels. The PI0 pin corresponds to bit
0 in the PIOData register.
This register can be used to detect the actual state of the
PIO pins, regardless of the PIO configuration.
$e6
r/w
StartupConfig
Shadows the start-up configuration set via PIO pins or I2C
command (valid are bits 8, 4...0 as described in Table 2–8.
$e7
r/w
KPrescale
responsible for prescale of the tone filter (prevent overflows)
(see Section 3.6.3. on page 28)
$80000
$6b
r/w
KBass
responsible for increase / decrease of low frequencies
(see Section 3.6.3. on page 28)
$0
$6f
r/w
KTreble
responsible for increase / decrease of high frequencies
(see Section 3.6.3. on page 28)
$0
1) In order to get the right information of the PIO pin levels (except for PI19, Demand Pin), register $ed should be
read and evaluated. However, the Demand Pin PI19 is shadowed in bit 19 of register $c8.
26
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
Table 3–7: DC/DC-converter switch frequency (Bits 8,
13..10 of DCCF-register)
DCCF Value
(hex)1)
fSW
Table 3–8: DC Converter Output Voltages (Bits
16..14, Bit 9 of DCCF-register)
DCCF Value
(hex)1)
DC/DC
Converter
Output
Internal
Voltage
Monitor 2)
Bit 8 = 0
Bit 8 = 1
0CC00
156 kHz
238 kHz
1C000
3.5 V
3.3 V
0C800
160 kHz
245 kHz
18000
3.4 V
3.2 V
0C400
163 kHz
253 kHz
14000
3.3 V
3.1 V
0C000
167 kHz
263 kHz
10000
3.2 V
3.0 V
04C00
171 kHz
272 kHz
0C000
3.1 V
2.9 V
04800
175 kHz
283 kHz
08000
3.0 V
2,8 V
04400
179 kHz
295 kHz
04000
2.9 V
2.7 V
04000
184 kHz
307 kHz
00000
2,8 V
2.6 V
01C00
188 kHz
320 kHz
1C200
2.7 V
2.5 V
01800
194 kHz
335 kHz
18200
2.6 V
2.4 V
01400
199 kHz
351 kHz
14200
2.5 V
2.3 V
01000
204 kHz
368 kHz
10200
2.4 V
2.2 V
00C00
210 kHz
387 kHz
0C200
2.3 V
2.1 V
00800
216 kHz
409 kHz
08200
2.2 V
2.0 V
00400
223 kHz
433 kHz
04200
2.1 V
1.9 V
00000
230 kHz
460 kHz
00200
2.0 V
1.8 V
1) All other bits are set to zero (DC/DC-converter
output voltage = 3.0 V)
1)
2)
All other bits are set to zero (fSW = 230 kHz)
PUP signal becomes inactive when output below
The DC/DC converter may generate interference noise
that could be unacceptable for some applications.
Thus the oscillator frequency may be adjusted in 16
steps in order to allow the system controller to select a
base frequency that does not interfere with an other
application.
The CLKI input provides the base clock fCKLI for the
frequency divider whose output is made symmetrical
with an additional divider by two. The divider quotient
is determined by the content of the DCCF register.
This register allows 32 settings generating a DC/DC
converter clock frequency fdc between:
f CKLI
f SW = -----------------------2 ⋅ (m + n)
Micronas
n ∈ {0, 15} , m ∈ { 16, 32 }
(EQ 3)
27
MAS 3507D
PRELIMINARY DATA SHEET
3.6.2. Muting / Bypass Tone Control
Address
R/W
Name
Comment
Default
$aa
r/w
Mute / Bypass
Tone Control
Forces a mute of the digital output
$0
0
1
2
no mute, Tone control active
mute output, but continue decoding
bypass Bass / Treble / Volume matrix
To enable fast and simple mute functionality, set bit 0 in register $aa to ‘1’. Writing a ‘0’ deactivates mute.
It is possible to bypass the complete bass / treble / volume control by setting bit 1 in register $aa (write a ‘2’). Resetting bit 1 to ‘0’ enables tone control again.
3.6.3. Bass and Treble Control
Address
R/W
Name
Comment
Default
$e7
r/w
KPrescale
responsible for prescale of the tone filter (prevent overflows)
(see Section 2.4.3. on page 8)
$80000
$6b
r/w
KBass
responsible for increase / decrease of low frequencies
(see Section 2.4.3. on page 8)
$0
$6f
r/w
KTreble
responsible for increase / decrease of high frequencies
(see Section 2.4.3. on page 8)
$0
Tone control is implemented in the MAS 3507D. It
allows the control of bass and treble in a range up to
±15 dB, as Table 3–9 shows. To prevent overflow or
clipping effects, the prescaler is built-in. The prescaler
decreases the overall gain of the tone filter, so the full
range up to +15 dB is usable without clipping.
28
To select a special setting, max. 3 coefficients have to
be written into registers of the MAS 3507D. This has to
be done via the ‘write register’ I2C command (see
Section 3.3.3.).
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
Table 3–9: Tone control registers
Boost in
dB
Bass
(Reg. $6b)
Treble
(Reg. $6f)
Prefactor
(Reg $e7)
+15
$61800
$5f800
$e9400
+14
$5d400
$58400
$e6800
+13
$58800
$51800
$e3400
+12
$53800
$49c00
$dfc00
+11
$4e400
$42c00
$dc000
+10
$48800
$3c000
$d7800
+9
$42800
$35400
$d25c0
+8
$3c000
$2ec00
$cd000
+7
$35800
$28400
$c6c00
+6
$2e400
$22000
$bfc00
+5
$27000
$1c000
$b8000
+4
$1f800
$16000
$af400
+3
$17c00
$10400
$a5800
+2
$10000
$ac00
$9a400
+1
$800
$5400
$8e000
0
0
0
$80000
−1
$f7c00
$fac00
$80000
−2
$efc00
$f5c00
$80000
−3
$e8000
$f0c00
$80000
−4
$e0400
$ec000
$80000
−5
$d8c00
$e7e00
$80000
−6
$d1800
$e2800
$80000
−7
$ca400
$de000
$80000
−8
$c3c00
$d9800
$80000
−9
$bd400
$d5000
$80000
−10
$b7400
$d0400
$80000
−11
$b1800
$cbc00
$80000
−12
$ac400
$c6c00
$80000
−13
$a7400
$c1800
$80000
−14
$a2800
$bb400
$80000
−15
$9e400
$b2c00
$80000
Micronas
29
MAS 3507D
PRELIMINARY DATA SHEET
3.7. Memory Area
3.7.1. Status Memory
The memory cells given in the following table should be accessed by the ‘read control interface data’ I2C command
(see Section 3.3.2. on page 21) because only the 16 LSBs of these memory blocks are used. The memory area
table is a consecutive memory block in the D0 memory that keeps all important status information that monitors the
MPEG decoding process. The ‘read control interface data’ command resets the MPEG-FRAME-SYNC at PI4 as
described in Section 2.9.
Table 3–10: Status Memory Area
Address
Offset1)
R/W
Name
Function
D0:$300
0
r
MPEGFrameCount
counts the MPEG frames
D0:$301
1
r
MPEGStatus1
MPEG header / status information
D0:$302
2
r
MPEGStatus2
MPEG header
D0:$303
3
r
CRCErrorCount
counts CRC errors during MPEG decoding
D0:$304
4
r
NumberOfAncillaryBits
number of bits in ancillary data
D0:$305
... $321
5
r
AncillaryData
organized in words a 16 bit (MSB first)
1) Offset applies to the ‘read control interface data’ command
3.7.1.1. MPEG Frame Counter
Address
D0:$300
Offset
0
R/W
Name
Function
r
MPEGFrameCount
counts the MPEG frames
The counter will be incremented with each new frame that is decoded. With an invalid MPEG bit stream as its input
(e.g. if an invalid header is detected), the MAS 3507D resets the MPEGFrameCount cell to ‘0’. The MPEGFrameCount is also returned by the ‘default read’ command as described in Section 3.3.9.
30
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
3.7.1.2. MPEG Status 1
Address
Offset
R/W
Name
Function
D0:$301
1
r
MPEGStatus 1
MPEG header / status information
The MPEG Status 1 contains the bits 15...11 of the MPEG header and some status bits. It will be set each frame,
directly after the header has been decoded from the bit stream.
Table 3–11: MPEG Status 1
Bits
Name/Value
Comment
19, 15
%xxxx.x
don’t care
14, 13
MPEG ID
Bits 11, 12 of the MPEG-header
%00
%01
%10
%11
MPEG 2.5
reserved
MPEG 2
MPEG 1
Layer
Bits 13, 14 of the MPEG-header
%00
%01
%10
%11
reserved
Layer 3
Layer 2
Layer 1 (Not supported)
%1
not protected by CRC
12, 11
10
9...2
private bits
1
%1
CRC Error
0
%1
invalid frame
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
3.7.1.3. MPEG Status 2
Address
Offset
R/W
Name
Function
D0:$302
2
r
MPEG Status 2
MPEG header
The MPEG Status 2 contains the 16 LSBs of the MPEG header. It will be set directly after synchronizing to the bit
stream.
Table 3–12: MPEG Status 2
Bits
Value/Name
19, 16
15...12
11, 10
don’t care
Bit rate index
MPEG 1
(Layer 2)
in kbit/s
MPEG 1
(Layer 3)
in kbit/s
MPEG 2 in kbit/s
(Layer 2 & 3)
MPEG 2.5 in kbit/s
%0000
%0001
%0010
%0011
%0100
%0101
%0110
%0111
%1000
%1001
%1010
%1011
%1100
%1101
%1110
%1111
free
32
48
56
64
80
96
112
128
160
192
224
256
320
384
forbidden
free
32
40
48
56
64
80
96
112
128
160
192
224
256
320
forbidden
free
8
16
24
32
40
48
56
64
80
96
112
128
144
160
forbidden
Sampling frequency
MPEG 1
MPEG 2
MPEG 2.5
%00
%01
%10
%11
44.1 kHz
48 kHz
32 kHz
reserved
22.05 kHz
24 kHz
16 kHz
reserved
11.025 kHz
12 kHz
8 kHz
reserved
9
Padding bit
8
Private bit
7, 6
Mode
5, 4
3
32
Comment
%00
%01
%10
%11
stereo
joint_stereo (intensity stereo / ms_stereo)
dual channel
single_channel
Mode extension
(if joint stereo only)
intensity stereo
ms_stereo
%00
%01
%10
%11
off
on
off
on
off
off
on
on
%0 / 1
copyright not protected / copyright protected
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
Table 3–12: MPEG Status 2
Bits
Value/Name
Comment
2
%0 / 1
copy / original
1, 0
Emphasis
indicates the type of emphasis
%00
%01
%10
%11
none
50/15 µs
reserved
CCITT J.17
3.7.1.4. CRC Error Counter
Address
D0:$303
Offset
3
R/W
Name
Function
r
CRCErrorCount
counts CRC errors during MPEG decoding
The counter will be increased by each CRC error in the MPEG bit stream. It will not be reset by losing the synchronization.
3.7.1.5. Number Of Ancillary Bits
Address
D0:$304
Offset
4
R/W
Name
Function
r
NumberOfAncillaryBits
number of bits in ancillary data
This cell displays the number of valid ancillary bits stored beginning at D0:$305.
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
3.7.1.6. Ancillary Data
Address
Offset
D0:$305 ...
D0:$321
5
R/W
Name
Function
r
AncillaryData
organized in words a 16 bit (MSB first)
This memory field contains the ancillary data. It is organized in words 16 bit each. The last ancillary bit transmitted in
a frame is placed at bit 0 in D0:$305. The position of the first ancillary data bit is locatable via the content of NumberOfAncillaryBits.
An example: 17 bits ancillary data in a frame:
A possible ‘read ancillary data’ algorithm would read the NumberOfAncillaryBits and the complete ancillary data
area using the telegram:
<$3a><$68><$31><$1e> (offset=4, n=30)
<$3a><$69><$3b><receive 30 16-bit words>
For reducing the I2C protocol transfer traffic, it may be useful to split up the ‘read ancillary data’ algorithm into a first
part that reads NumberOfAncillaryBits and a second that reads only NumberOfAncillaryBits/16+1 words.
Table 3–13: Ancillary data bit assignment
D0: $305
15 MSB
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00 LSB
ancillary data
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
bit 11
bit 12
bit 13
bit 14
bit 15
bit 16
Table 3–14: Ancillary data bit assignment
D0: $306
15 MSB
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00 LSB
ancillary data
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
bit 0
34
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
3.7.2. Configuration Memory
The configuration memory allows the controller advanced configuration possibilities, e.g. changing setups for the
crystal frequency or changing the digital format of the serial audio output data interface.
Table 3–15: Configuration memory area1)
Address
R/W
Name
Function
Default
D0:$36d
r/w
PLLOffset48
PLL offset (if fs = 48, 24, 12, 32, 16, or 8 kHz),
validate by ‘run $475’ command
D0:$36e
r/w
PLLOffset44
PLL offset (if fs = 44.1, 22.05, 11.025 kHz),
validate by ‘run $475’ command
D0:$36f
r/w
OutputConfig
Configuration of the I2S audio output interface
validate by ‘run $475’ command
D1:$7f8
r/w
LL
Left → Left Gain
$80000
D1:$7f9
r/w
LR
Left → Right Gain
0
D1:$7fa
r/w
RL
Right → Left Gain
0
D1:$7fb
r/w
RR
Right → Right Gain
$80000
1) Important note: Writing into undocumented memory cells is always possible, but it is highly recommended not to
do so. It may damage the function of the firmware and may even lead to a complete system crash of the decoder
operation which can only be restored by a reset.
Micronas
35
MAS 3507D
PRELIMINARY DATA SHEET
3.7.2.1. PLL Offset for 44/48 kHz Sampling Frequency
Address
R/W
Name
Function
D0:$36d
r/w
PLLOffset48
PLL offset (if fs = 48, 24, 12, 32, 16, or 8 kHz),
validate by ‘run $475’ command
D0:$36e
r/w
PLLOffset44
PLL offset (if fs = 44.1, 22.05, 11.025 kHz),
validate by ‘run $475’ command
With these memory cells it is possible to choose other
frequencies than the standard CLKI frequencies.
Please note:
– PLLOffset48 is valid for
fs = 48, 24, 12, 32, 16, or 8 kHz.
– PLLOffset44 is valid for
fs = 44.1, 22.05, 11.025 kHz.
Table 3–16 shows the default values which will be set
by the firmware according to the start-up configuration.
Table 3–16: PLLOffset48 and PLLOffset44
fCLKI
PLLOffset48
PLLOffset44
14.725 MHz
0.351986
−0.732862
Default
Table 3–17: fClkI for max./ min. PLLOffsets
PLLOffset
fCLKI for fs
related to
48 kHz
fCLKI for fs
related to
44.1 kHz
−0.74
16.0365 MHz
14.7336 MHz
0.74
14.309 MHz
13.1465 MHz
Example:
A very common crystal frequency is 14.31818 MHz
(NTSC color subcarrier). The
⋅8
------------------------ – 13 = 0,7314
PLLOffset48 = 24,576
14,31818
and
It is also possible to run the MAS 3507D with other
clocks. In broadcast mode, it is necessary to adjust the
PLLOffsets to this clock, otherwise it will not lock to the
MPEG bit stream. In multimedia mode, it is recommended to adjust the PLLOffsets to the crystal, otherwise it would result in a frequency shift (music will be
played faster or slower). For adjusting, the following
procedure must be done:
⋅8
--------------------------- – 13 = – 0,3843
PLLOffset44 = 22,5792
14,31818
are inside the range −0.74 ... 0.74.
– Calculate the PLLOffsets according to:
24,576 ⋅ 8
22,5792 ⋅ 8
f CLKI = ---------------------------------------------- = ---------------------------------------------13 + PLLOffset48
13 + PLLOffset44
with −0.74 < PLLOffset < 0.74. This corresponds to
a frequency range of 14.31...14.73 MHz for the
crystal, if both 44.1 kHz and 48 kHz based sample
frequencies are used. The range is extended in an
application with a fixed sampling frequency, as
Table 3–17 shows.
– Write the PLLOffsets to the memory (PLLOffset48
D0:$36d, PLLOffset44 D0:$36e).
– Send a ‘run $475’ command. With the jump to this
address, the settings in the memory will be valid for
the internal processing.
36
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
3.7.2.2. Output Configuration
Address
R/W
Name
Function
D0:$36f
r/w
OutputConfig
Configuration of the I2S audio output interface
validate by ‘run $475’ command
The content of this memory cell depends on the startup configuration and will be set by the firmware. Nevertheless, the audio output interface is configurable by
the software to work in different 16 bit/sample modes
and 32 bit/sample modes (see Section 2.7.4. on
page 13). For adjusting to this, the following procedure
has to be done:
Default
Table 3–18: Output Configuration
Bits
Value
Comment
19...15
%0000.0
don’t care
14
%0
%1
SOC standard timing
SOC inverted timing
13..12
%00.
don’t care
11
%0
%1
no delay
additional delay of
data related to word
strobe
10...6
%000.00
don’t care
5
%0
%1
not invert
invert outgoing
word strobe signal
4
%0
%1
32 bits/sample
16 bits/sample
3...0
%0000
don’t care
– Choose the output mode (see Table 3–18).
– Write this value to the memory (D0:$36f).
– Send a ‘run $475’ command. With the jump to this
address, the settings in the memory will become
valid for the internal processing. This overrides all
start-up settings
3.7.3. Baseband Volume Matrix
Address
R/W
Name
Function
Default
D1:$7f8
r/w
LL
Left->Left gain
$80000
D1:$7f9
r/w
LR
Left->Right gain
$0
D1:$7fa
r/w
RL
Right->Left gain
$0
D1:$7fb
r/w
RR
Right->Right gain
$80000
The digital Baseband volume Matrix is used for controlling the digital gain and a simple kind of stereo
basewidth enlargement as shown in Fig. 3–2. Table 3–
20 shows the proposed settings for the 4 volume
matrix coefficients for stereo, left and right mono. The
gain factors are given in fixed point notation. The gain
values may be written to the MAS 3507D by the controller command ’write D1 memory’.
Table 3–19: Bit Assignment of the Volume Cells
Bits
Name Value
Comment
19..0
LL/LR/RL/RR
−524288/524288..524287/524288 = −1.0 .. 1.0 − 2^−19
Micronas
37
MAS 3507D
PRELIMINARY DATA SHEET
Table 3–20: Settings for the digital volume matrix
left audio
−1
−1
right audio
+
LL
LR
−1
RL
−1
RR
Memory
location
D1:
$7f8
D1:
$7f9
D1:
$7fa
D1:
$7fb
Name
LL
LR
RL
RR
Stereo
(default)
−1.0
0
0
−1.0
Mono
left
−1.0
−1.0
0
0
Mono
right
0
0
−1.0
−1.0
The fixed point gain values correspond to 20 bit 2’s
complement notation. The conversion between fixed
point and 2’s complement notation is done easily by
the algorithms described in Section 3.2.1.
+
Fig. 3–2: Digital volume matrix
Table 3–21: Volume matrix conversion (dB into hexadecimal)
Volume
(in dB)
Hexa
decimal
Volume
(in dB)
Hexa
decimal
Volume
(in dB)
Hexa
decimal
Volume
(in dB)
Hexa
decimal
Volume
(in dB)
Hexa
decimal
0
80000
−20
F3333
−40
FEB85
−60
FFDF4
−80
FFFCC
−1
8DEB8
−21
F4979
−41
FEDBF
−61
FFE2D
−81
FFFD1
−2
9A537
−22
F5D52
−42
FEFBB
−62
FFE60
−82
FFFD6
−3
A5621
−23
F6F03
−43
FF180
−63
FFE8D
−83
FFFDB
−4
AF3CD
−24
F7EC8
−44
FF314
−64
FFEB5
−84
FFFDF
−5
B8053
−25
F8CD5
−45
FF47C
−65
FFED9
−85
FFFE3
−6
BFD92
−26
F995B
−46
FF5BC
−66
FFEF9
−86
FFFE6
−7
C6D31
−27
FA485
−47
FF6DA
−67
FFF16
−87
FFFE9
−8
CD0AD
−28
FAE78
−48
FF7D9
−68
FFF2F
−88
FFFEB
−9
D2958
−29
FB756
−49
FF8BC
−69
FFF46
−89
FFFED
−10
D785E
−30
FBF3D
−50
FF986
−70
FFF5A
−90
FFFEF
−11
DBECC
−31
FC648
−51
FFA3A
−71
FFF6C
−91
FFFF1
−12
DFD91
−32
FCC8E
−52
FFADB
−72
FFF7C
−92
FFFF3
−13
E3583
−33
FD227
−53
FFB6A
−73
FFF8B
−93
FFFF4
−14
E675F
−34
FD723
−54
FFBEA
−74
FFF97
−94
FFFF6
−15
E93CF
−35
FDB95
−55
FFC5C
−75
FFFA3
−95
FFFF7
−16
EBB6A
−36
FDF8B
−56
FFCC1
−76
FFFAD
−96
FFFF8
−17
EDEB6
−37
FE312
−57
FFD1B
−77
FFFB6
−97
FFFF9
−18
EFE2C
−38
FE638
−58
FFD6C
−78
FFFBE
−98
FFFF9
−19
F1A36
−39
FE905
−59
FFDB4
−79
FFFC5
−99
FFFFA
Table 3–21 contains the converted gain values as used in the ’write D1 memory’ command
38
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
4. Specifications
0.9 ± 0.2
4.1. Outline Dimensions
1.1 x 45 °
5
17
29
18
1.9 ±0.05
28
1.27
5
0.71 ± 0.05
17.52 ± 0.12
2
2
8.6
10 x 1.27 = 12.7 ± 0.1
39
1.6
16.5 ± 0.1
7
0.48 ± 0.06
40
15.7 ± 0.3
1
0.28 ± 0.04
6
10 x 1.27 = 12.7 ± 0.1
1.27
1.2 x 45°
4.05 ±0.1
17.52 ± 0.12
4.75 ±0.15
16.5 ± 0.1
0.1
SPGS0027-2(P44/K)/1E
Fig. 4–1:
44-Pin Plastic Leaded Chip Carrier Package
(PLCC44)
Weight approximately 2.5 g
Dimensions in mm
10 x 0.8 = 8 ± 0.1
0.17 ± 0.06
12
44
1
11
1.75
10 ± 0.1
0.375 ± 0.075
13.2 ± 0.2
1.3
0.8
22
34
1.75
0.8
23
10 x 0.8 = 8 ± 0.1
33
2.0 ± 0.1
13.2 ± 0.2
2.15
± 0.2
0.1
10 ± 0.1
SPGS706000-2(P44)/1E
Fig. 4–2:
44-Pin Plastic Quad Flat Package
(PMQFP44)
Weight approximately 0.4 g
Dimensions in mm
Note: Start pin and orientation of pin numbering is different for PLCC and PMQFP packages!
Micronas
39
MAS 3507D
PRELIMINARY DATA SHEET
A1 Ball Pad Corner
7
6
5
4
3
1.4
0.36
2 1
A
C
0.8
D
∅ 0.46
6 x 0.8 = 4.8
7
B
E
F
1.1
G
0.8
1.1
1.04
6 x 0.8 = 4.8
7
SPGS0007-1/2E
Fig. 4–3:
49-Ball Plastic Ball Grid Array
(PBGA49)
Weight approximately 0.13 g
Dimensions in mm
4.2. Pin Connections and Short Descriptions
NC
LV
X
not connected, leave vacant
If not used, leave vacant
obligatory, pin must be connected as described
in application information
Pin No.
Pin Name
Type
VDD connect to positive supply
VSS connect to ground
Connection
Short Description
PMQFP
44-pin
PLCC
44-pin
PBGA
49-ball
Test Alias in ()
1
6
C3
TE
IN
VSS
Test Enable
2
5
C2
POR
IN
VDD
Reset, Active Low
3
4
B1
I2CC
IN/OUT
X
I2C Clock Line
4
3
D2
I2CD
IN/OUT
X
I2C Data Line
5
2
C1
VDD
SUPPLY
X
Positive Supply for Digital Parts
6
1
D1
VSS
SUPPLY
X
Ground Supply for Digital Parts
7
44
E2
DCEN
IN
VSS
Enable DC/DC Converter
8
43
E1
EOD
OUT
LV
PIO End of DMA, Active Low
9
42
F2
RTR
OUT
LV
PIO Ready to Read, Active Low
10
41
F1
RTW
OUT
LV
PIO Ready to Write, Active Low
11
40
G1
DCSG
SUPPLY
VSS
DC Converter Transistor Ground
12
39
E3
DCSO
OUT
VSS
DC Converter Transistor Open Drain
13
38
F3
VSENS
IN
VDD
DC Converter Voltage Sense
14
37
G2
PR
IN
X
PIO-DMA Request or Read/Write
40
(If not used)
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
Pin No.
Pin Name
Type
Connection
Short Description
PMQFP
44-pin
PLCC
44-pin
PBGA
49-ball
Test Alias in ()
(If not used)
15
36
F4
PCS
IN
X
PIO Chip Select, Active Low
16
35
G3
PI19
IN/OUT
LV
PIO Data [19]
1. Demand Pin in SDI mode
2. data bit [7], MSB (PIO-DMA input
mode)
17
34
E4
PI18
IN/OUT
LV
PIO Data [18]
1. MPEG header bit 11 − MPEG ID
(SDI mode)
2. data bit [6] (PIO-DMA input mode)
18
33
G4
PI17
IN/OUT
LV
PIO Data [17]
1. MPEG header bit 12 – MPEG ID
(SDI mode)
2. data bit [5] (PIO-DMA input mode)
19
32
F5
PI16
IN/OUT
LV
PIO Data [16]
1. SIC*, alternative input for SIC (SDI
mode)
2. data bit [4] (PIO-DMA input mode)
20
31
G5
PI15
IN/OUT
LV
PIO Data [15]
1. SII*, alternative input for SII (SDI
mode)
2. data bit [3] (PIO-DMA input mode)
21
30
F6
PI14
IN/OUT
LV
PIO Data [14]
1. SID*, alternative input for SID (SDI
mode)
2. data bit [2] (PIO-DMA input mode)
22
29
G6
PI13
IN/OUT
LV
PIO Data [13]
1. MPEG header bit 13 – Layer ID (SDI
mode)
2. data bit [1] (PIO-DMA input mode)
23
28
E5
PI12
IN/OUT
LV
PIO Data [12]
1. MPEG header bit 14 – Layer ID (SDI
mode)
2. data bit [0] (PIO-DMA input mode)
24
27
E6
SOD
(PI11)
OUT
LV
Serial Output Data
25
26
F7
SOI
(PI10)
OUT
LV
Serial Output Frame Identification
26
25
D6
SOC
(PI9)
OUT
LV
Serial Output Clock
27
24
E7
PI8
IN
X
Start-up1): Clock output scaler on / off
Operation2): MPEG CRC error
OUT
28
23
D7
XVDD
SUPPLY
X
Positive Supply of Output Buffers
29
22
C6
XVSS
SUPPLY
X
Ground of Output Buffers
30
21
C7
SID
(PI7)
IN
X
Serial Input Data
31
20
B6
SII
(PI6)
IN
VSS
Serial Input Frame Identification
Micronas
41
MAS 3507D
Pin No.
PRELIMINARY DATA SHEET
Pin Name
PMQFP
44-pin
PLCC
44-pin
PBGA
49-ball
Test Alias in ()
32
19
B7
SIC
33
18
A7
PI4
(PI5)
Type
Connection
(If not used)
IN
X
Serial Input Clock
IN
X
Start-up1): Select SDI / PIO-DMA input
mode
Operation2): MPEG-Frame Sync
OUT
34
17
B5
PI3
IN
X
16
A6
PI2
IN
X
15
B4
PI1
IN
X
14
A5
PI0
IN
Start-up1):
SDO: Select 32-bit mode / 16-bit I2S
mode
Operation2): MPEG header bit 30
(Emphasis)
OUT
37
Start-up1):
Enable Layer 2 / Disable Layer 2
decoding
Operation2): MPEG header bit 21
(Sampling frequency)
OUT
36
Start-up1):
Enable Layer 3 / Disable Layer 3
decoding
Operation2): MPEG header bit 20
(Sampling frequency)
OUT
35
Short Description
X
Start-up1):
Select Multimedia mode / Broadcast
mode
Operation2): MPEG header bit 31
(Emphasis)
OUT
38
13
C4
CLKO
OUT
LV
Clock Output for the D/A converter
39
12
A4
PUP
OUT
LV
Power Up, i.e. status of voltage supervision
40
11
B3
WSEN
IN
X
Enable DSP and Start DC/DC Converter
41
10
A3
WRDY
OUT
LV
If WSEN = 0: valid clock input at CLKI
If WSEN = 1: clock synthesizer PLL
locked
42
9
B2
AVDD
SUPPLY
VDD
Supply for analog circuits
43
8
A2
CLKI
IN
X
Clock input
44
7
A1
AVSS
SUPPLY
VSS
Ground supply for analog circuits
1)
2)
42
Start-up configuration see Section 2.8.
Not available in PIO-DMA mode, see Section 2.8.1.
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
4.2.1. Pin Descriptions
4.2.1.3. Control Lines
4.2.1.1. Power Supply Pins
I2CC
I2CD
Connection of all power supply pins is mandatory for
the function of the MAS 3507D.
VDD
VSS
SCL
SDA
IN/OUT
IN/OUT
Standard I2C control lines. Normally there are Pullupresistors tied from each line to VDD.
SUPPLY
SUPPLY
4.2.1.4. Parallel Interface Lines
The VDD/VSS pair is internally connected with all digital modules of the MAS 3507D.
XVDD
XVSS
SUPPLY
SUPPLY
The XVDD/XVSS pins are internally connected with
the pin output buffers.
AVDD
AVSS
SUPPLY
SUPPLY
The AVDD/AVSS pair is connected internally with the
analog blocks of the MAS 3507D, i.e. clock synthesizer
and supply voltage supervision circuits.
4.2.1.4.1. PIO Handshake Lines
PIO handshake lines are not used during start-up but
in operation mode. Read out of the status information
and the demand mode work in µP-mode: set PCS = ’0’
and PR = ’1’. Usage of PIO-DMA mode is possible
with input mode via PIO.
PCS
The PIO chip select must be set to ‘0’ to activate the
PIO as Output in operation mode (e.g. PI19 = demand
signal in mutimedia mode & SDI input mode).
PR
IN
The PIO PR must be set to ‘1’ to validate data output
from MAS 3507D.
4.2.1.2. DC/DC Converter Pins
DCEN
IN
IN
RTW
The DCEN input signal enables the DC/DC converter
operation.
RTW is not supported by the built-in firmware.
DCSG
RTR
SUPPLY
OUT
OUT
The DC converter Signal Ground pin is used as a
basepoint for the internal switching transistor of the
DC/DC converter. It must always be connected to
ground.
RTR is only supported by the built-in firmware in PIODMA input mode.
DCSO
End of DMA (EOD) is only supported by the built-in
firmware in PIO-DMA input mode.
OUT
DCSO is an open drain output and should be connected with external circuitry (inductor/diode) to start
the DC/DC converter. When the DC/DC converter is
not used, it has to be connected to VSS.
VSENS
IN
The VSENS pin is the input for the DC/DC converter
feedback loop. It must be connected directly with the
Schottky diode and the capacitor as shown in Fig. 2–3.
When the DC/DC converter is not used, it has to be
connected to VDD.
Micronas
EOD
OUT
4.2.1.4.2. PIO Data Lines
The function of the parallel interface is separated into
two parts. During start-up, the PIO will read the startup configuration (independent from the PIO handshake lines). This is done to define the environment for
the MAS 3507D (see Section 2.8.1. for details).
After start-up, the PIO will be switched to µP-mode.
With the PR = ‘1’ and the PCS = ‘0’, the PIO interface
is defined as output and displays some status information of the MPEG decoder. The PIO can be connected
to an external controller or to a display unit (e.g. LED).
The internal MPEG decoder firmware attaches specific
functions to the following pins:
43
MAS 3507D
PI19
PRELIMINARY DATA SHEET
DEMAND PIN
OUT
When MAS 3507D is in multimedia mode it demands
with PI19 = ’1’ for new input data.
PI18
PI17
MPEG-IDEX
MPEG-ID
OUT
OUT
4.2.1.5. Voltage Supervision And Other Functions
CLKI
IN
This is the clock input of the MAS 3507D. CLKI should
be a buffered output of a crystal oscillator. Standard
clock frequency is 14.725. Others can be used, if
PLL_offset register is changed by I2C.
These pins mirror the according bits of the MPEG
header (see Table 2–9 for details).
CLKO
PI16
PI15
PI14
The CLKO is an oversampling clock that is synchronized to the digital audio data (SOD) and the frame
identification (SOI).
(SIC*)
(SII*)
(SID*
IN
IN
IN
The SIC*, SID*, and SII* may be configured as alternative serial input lines in order to support alternative
serial digital inputs.
PI13
PI12
LAYER ID
LAYER ID
OUT
OUT
PUP
OUT
OUT
The PUP output indicates that the power supply voltage exceeds its minimal level (software adjustable).
WSEN
IN
These pins mirror the according bits of the MPEG
header (see Table 2–9 for details).
WSEN enables DSP operation and starts DC/DC-converter.
PI8
WRDY
MPEG-CRC-ERROR
OUT/IN
The MPEG-CRC-ERROR pin is activated if no successful MPEG decoding is possible. The reason might
be that the CRC check of the MPEG Frame header
has detected an error or that no valid bit stream is
available. The error signal will stay active for the entire
duration of one MPEG frame.
During start-up, this pin is an input for enabling/disabling the CLKO+divider (see Section 3.6.).
PI4
MPEG-FRAME-SYNC
OUT
WRDY has two functions depending on the state of the
WSEN signal.
If WSEN = ’0’, it indicates that a valid clock has been
recognized at the CLKI clock input.
If WSEN = ’1’, the WRDY output will be set to ‘0’ until
the internal clock synthesizer has locked to the incoming audio data stream, and thus, the CLKO clock output signal is valid.
OUT/IN
The MPEG-FRAME-SYNC signal indicates that a
MPEG header has been decoded properly and the
internal MPEG decoder is in a synched state. The
MPEG-FRAME-SYNC signal is inactive after Power
On Reset and will be activated if a valid MPEG Layer 2
or 3 header has been recognized. The signal will be
cleared if the ancillary data information is read out by
the controller via I2C interface.
4.2.1.6. Serial Input Interface
SID
SII
SIC
IN
IN
IN
Data, Frame Indication, and Clock line of the serial
input interface. The SII line should be connected with
VSS in the standard mode.
During start-up, this pin sets either SDI- or PIO-DMAinput mode (see Section 3.6.).
4.2.1.7. Serial Output Interface
PI3
PI2
PI1
PI0
SAMPLING FREQUENCY
SAMPLING FREQUENCY
EMPHASIS
EMPHASIS
OUT
OUT
OUT
OUT
These pins mirror the according bits of the MPEG
header (see Table 2–9 for details).
During start-up, these pins are input pins (see
Section 3.6.).
44
SOD
SOI
SOC
OUT
OUT
OUT
Data, Frame Indication, and Clock line of the serial output interface. The SOI indicates whether the left or the
right audio sample is transmitted. Besides the two
modes (selected by the PI1 during start-up), it is possible to reconfigure the interface.
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
4.2.1.8. Miscellaneous
IN
POR
The Power On Reset pin is used to reset the digital
parts of the MAS 3507D. POR is a low active signal.
TE
IN
The TE pin is for production test only and must be connected with VSS in all applications.
4.2.2. Pin Configurations
XVDD
VSS
VDD
XVSS
DCEN
I2CD
I2CC
5
4
3
2
1
SOD
PI4
DCSG
6
SOI
SIC
RTW
TE
SOC
SII
RTR
POR
PI8
SID
EOD
PI12
33 32 31 30 29 28 27 26 25 24 23
44 43 42 41 40
AVSS
7
39
DCSO
PI3
34
22
PI13
CLKI
8
38
VSENS
PI2
35
21
PI14
AVDD
9
37
PR
PI1
36
20
PI15
WRDY
10
36
PCS
PI0
37
19
PI16
WSEN
11
35
PI19
CLKO
38
18
PI17
PUP
12
34
PI18
PUP
39
17
PI18
CLKO
13
33
PI17
WSEN
40
16
PI19
PI0
14
32
PI16
WRDY
41
15
PCS
PI1
15
31
PI15
AVDD
42
14
PR
PI2
16
30
PI14
CLKI
43
13
VSENS
PI3
17
29
PI13
AVSS
44
12
DCSO
MAS 3507D
1
18 19 20 21 22 23 24 25 26 27 28
PI4
PI12
SIC
SOD
SII
SOI
SID
SOC
XVSS
PI8
XVDD
Fig. 4–4: 44-pin PLCC package
Micronas
MAS 3507D
2
3
4
5
6
7
8
9
10 11
TE
DCSG
POR
RTW
I2CC
RTR
EOD
I2CD
VDD
DCEN
VSS
Fig. 4–5: 44-pin PMQFP package
45
MAS 3507D
PRELIMINARY DATA SHEET
4.2.3. Internal Pin Circuits
TTLIN
DCSO
DCSG
Fig. 4–6: Input pins PCS, PR
VSS
Fig. 4–12: Input/Output pins DCSO, DCSG
VDD
Fig. 4–7: Input pin TE, DCEN
P
N
VSS
Fig. 4–8: Input pins WSEN, POR
Fig. 4–13: Output pins WRDY, RTW, EOD, RTR,
CLKO, PUP
VSENS
Fig. 4–9: Input pin CLKI
VDD
VSS
P
Fig. 4–14: Input pin VSENS
N
VSS
Fig. 4–10: Input/Output pins PI0...PI4, PI8, SOC, SOI,
SOD, PI12...PI19
VDD
P
N
VDD
VSS
Fig. 4–15: Input/Output pins SIC, SII, SID
N
VSS
Fig. 4–11: Input/Output pins I2CC, I2CD
46
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
4.2.4. Electrical Characteristics
4.2.4.1. Absolute Maximum Ratings
Symbol
Parameter
TA
Pin
Name
Min.
Max.
Unit
Ambient Operating Temperature
−30
85
°C
TS
Storage Temperature
−40
125
°C
PMAX
Power dissipation
VDD,
XVDD,
AVDD
600
mW
VDD,
XVDD,
AVDD
5.5
V
400 (PBGA)
VSUP
Supply voltage
VIdig
Input voltage, all digital inputs
−0.3
VSUP +0.3
V
IIdig
Input current, all digital inputs
−20
+20
mA
IOut
Current, all digital output
0.5
A
IOutDC
Current
1.5
A
DCSO
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
4.2.4.2. Recommended Operating Conditions
Symbol
Parameter
TA
Ambient temperature range
VSUP
Supply voltage
Pin
Name
Min.
Typ.
−30
VDD,
XVDD,
AVDD
2.5
2.7
Max.
Unit
85
°C
3.6
V
Reference Frequency Generation
CLKF
Clock Frequency1)
CLKI_V
Clock Input Voltage
0
CLKAmp
Clock Amplitude
0.5
1)
CLKI
14.725
MHz
VSUP
V
Vpp
range acc. to Section 3.7.2.1.
Micronas
47
MAS 3507D
Symbol
PRELIMINARY DATA SHEET
Parameter
Pin
Name
IIL27
Input Low Voltage
@VSUP = 2.5 V ... 3.6 V
IIH36
Input High Voltage
@VSUP = 2.5 V ... 3.6 V
POR
I2CC,
I2CD,
DCEN,
WSEN
IIH33
Min.
Typ.
Max.
Unit
0.4
V
Levels
1.8
V
Input High Voltage
@VSUP = 2.5 V ... 3.3 V
1.7
V
IIH30
Input High Voltage
@VSUP = 2.5 V ... 3.0 V
1.6
V
IILD
Input Low Voltage
IIHD
Input High Voltage
Trf
Rise / Fall time of digital inputs
PI<i>,
SII,
SIC,
SID,
PR,
PCS,
CLKI
Dcycle
Duty cycle of digital clock inputs
SIC, CLKI
PI<i>2),
SII,
SIC,
SID,
PR,
PCS,
TE,
0.4
VSUP− 0.5
40
V
V
50
10
ns
60
%
DC-DC converter external circuitry
C1
Blocking Capacitor
(25 mΩ ESR)3)
VSENS,
DCSG
VF
Schottky Diode Forward voltage4)
DCSO,
VSENS
L
Inductance of Ferrite ring core coil5)
(50 mΩ),VAC 616/103
DCSO
2)
3)
4)
5)
48
µF
330
0.35
0.45
20
V
µH
i = 0 to 4, 8 , 12 to 19
Sanyo Oscon 6SA330M
(distributed by Endrich Bauelemente, D-72202 Nagold-lselshausen, www.endrich.com)
ZETEX ZMCS1000
(distributed by ZETEX, D-81673 München, [email protected]), standard Schottky 1N5817
C8 R/4L, SDS0604 (distributed by Endrich Bauelemente, see above)
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
4.2.4.3. Characteristics
at TA = −30 to 85 °C, VSUP = 2.5 to 3.6 V, typ. values at TA = 27°C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty
cycle = 50%
Symbol
Parameter
Pin
Name
Min.
Typ.
Max.
Unit
Test Conditions
32
mA
2.7 V, sampling
frequency ≥ 32kHz
17
mA
2.7 V, sampling
frequency ≤ 24 kHz
11
mA
2.7 V, sampling
frequency ≤ 12 kHz
V
Iload = 6mA
V
Iload = 6mA
Supply Voltage
ISUP
Current consumption
VDD,
XVDD,
AVDD
Digital Outputs and Inputs
VDOL
Output Low Voltage
VDIH
Output High Voltage
ZDigI
Input Impedance
IDLeak
Digital Input Leakage
Current
1)
SOI1),
SOC1),
SOD1),
EOD,
RTR,
RTW,
WRDY,
PUP,
CLKO
PI<i>
PI<i>,
SII,
SIC,
SID,
PR,
PCS,
CLKI
0.3
VSUP−
0.3
−1
7
pF
1
µA
0 V < Vpin < VSUP
in low inpedance mode
Micronas
49
MAS 3507D
PRELIMINARY DATA SHEET
4.2.4.3.1. I2C Characteristics
at TA = −30 to 85 °C, VSUP =2.5 to 3.6 V, typ. values at TA = 27°C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty
cycle = 50 %
Symbol
Parameter
Pin
Name
RON
Output resistance
fI2C
Min.
Typ.
Max.
Unit
Test Conditions
I2CC,
I2CD
60
Ω
Iload = 5 mA,
VSUP = 2.7 V
I2C Bus Frequency
I2CC
400
kHz
tI2C1
I2C START Condition Setup
Time
I2CC,
I2CD
300
ns
tI2C2
I2C STOP Condition Setup
Time
I2CC,
I2CD
300
ns
tI2C3
I2C Clock Low Pulse Time
I2CC
1250
ns
tI2C4
I2C Clock High Pulse Time
I2CC
1250
ns
tI2C5
I2C Data Hold Time before
rising edge of clock
I2CC
80
ns
tI2C6
I2C Data Hold Time after
falling edge of clock
I2CC
80
ns
VI2COL
I2C Output Low Voltage
I2CC,
I2CD
0.3
V
ILOAD = 5 mA
II2COH
I2C Output high leakage
current
I2CC,
I2CD
1
uA
VI2CH = 3.6 V
tI2COL1
I2C Data Output Hold Time
after falling edge of clock
I2CC,
I2CD
20
ns
tI2COL2
I2C Data Output Setup Time
before rising edge of clock
I2CC,
I2CD
250
ns
fI2C = 400kHz
1/fI2C
tI2C4
tI2C3
H
L
I2CC
tI2C1
tI2C5
tI2C6
tI2C2
H
L
I2CD as input
tI2COL2
tIC2OL1
H
L
I2CD as output
Fig. 4–16: I2C timing diagram
50
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
4.2.4.3.2. I2S Bus Characteristics – SDI
at TA = −30 to 85 °C, VSUP =2.5 to 3.6 V, typ. values at TA = 27°C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty
cycle = 50 %
Symbol
Parameter
Pin
Name
Min.
tSICLK
I2S Clock Input Clockperiod
SIC
960
tSIIDS
I2S Data SetupTime before
falling edge of clock
SIC,
SID
50
tSIIDH
I2S data hold time
SID
50
tbw
Burst wait time
SIC,
SID
480
Typ.
Max.
tSICLK100
Unit
Test Conditions
ns
multimedia mode, mean
data rate < 150 kbit/s
ns
ns
TSICLK
H
SIC
L
H
(SII)
L
H
SID
L
TSIIDS
TSIIDH
Fig. 4–17: Serial input
Micronas
51
MAS 3507D
PRELIMINARY DATA SHEET
4.2.4.3.3. I2S Characteristics – SDO
at TA = −30 to 85 °C, VSUP = 2.5 to 3.6 V, typ. values at TA = 27°C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty
cycle = 50 %
Symbol
Parameter
Pin
Name
Min.
Typ.
Max.
tSOCLK
I2S Clock Output Period
SOC
tSOISS
I2S Wordstrobe Hold Time
after falling edge of clock
SOC,
SOI
10
tSOCLK/
2
ns
tSOODC
I2S Data Hold Time after
falling edge of clock
SOC,
SOD
10
tSOCLK/
2
ns
325
Unit
Test Conditions
ns
48 kHz Stereo
32 bit/sample
TSOCLK
H
SOC
L
H
SOI
L
TSOISS
TSOISS
H
SOD
L
TSOODC
Fig. 4–18: Serial output
52
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
4.2.4.4. Firmware Characteristics
at TA = −30 to 85 °C, VSUP = 2.5 to 3.6 V, typ. values at TA = 27°C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty
cycle = 50 %
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
12...36
72
ms
fs = 32 kHz, MPEG 2.5
200
ppm
Broadcast mode
Synchronization Times
Synchronization on MPEG Bit Streams
tmpgsync
Ranges
PLLRange
−200
Tracking range of sampling clock
recovery PLL
4.2.4.4.1. Input Timing Parameters of the MultimediaMode
Symbol
Parameter
Pin Name
Min.
Tsdstart
Reaction time for data source
PI19
Tsdstart
Typ.
Max.
Unit
Test Conditions
3.1
5.7
ms
fs = 48 kHz,
320...64 kbit/s
Reaction time for data source
4.2
9.2
ms
fs = 24 kHz,
320...32 kbit/s
Tsdstar
Reaction time for data source
23.1
25.6
ms
fs = 12 kHz,
64...16 kbit/s
Tsdstar
Reaction time for data source
34.8
38.4
ms
fs = 8 kHz,
64...8 kbit/s
Tsdstop
Reaction time for data source
1.3
ms
H
PI19
L
Tsdstart
Tsdstop
Fig. 4–19: Demand mode
Tsdstart refers to the maximal response time for a serial data source to start data transmission with respect to the rising edge of the demand signal at the pin PI19.
Tsdstop refers to the maximal response time for a serial data source to stop data transmission with respect to the falling edge of the demand signal at the pin PI19.
Micronas
53
MAS 3507D
PRELIMINARY DATA SHEET
4.2.4.5. DC/DC Converter Characteristics
at TA = −30 to 85 °C, VSUP = 3.0 V, CLKF = 14.725 MHz, fsw = 230 kHz, typ. values at TA = +27 °C
Symbol
Parameter
VIN1
VIN2
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Minimum Start-Up Input
Voltage
0.9
1.0
V
ILOAD = 0 mA
DCCF = $08000
(Reset)
Minimum Operating Voltage
0.6
0.8
V
ILOAD = 55 mA,
DCCF = $08000
(Reset)
1.3
1.8
V
ILOAD = 250 mA,
DCCF = $08000
(Reset)
3.5
V
see Section 4.2.4.6.
2.0 1)
VOUT
Output Voltage
dVOUT/dVIN/
VOUT
Line Regulation
1
%
VIN = 1.0...3.0 V,
ILOAD = 55 mA
dVOUT/dILOAD/
VOUT
Load Regulation
0.6
%
VIN = 1.2 V,
ILOAD = 0...55 mA,
fSW = 230 kHz
dVOUT/dILOAD/
VOUT
Load Regulation
1.2
%
VIN = 1.2 V,
ILOAD = 0...55 mA,
fSW = 165 kHz
hmax
Maximum Efficiency
90
%
ISUPPLY
Supply Current
1.1
5
mA
IL,MAX
Inductor Current Limit
DCSO,
DCSG
1.0
1.4
A
RON
Switch On-Resistance
DCSO,
DCSG
0.2
0.4
Ω
Tj = 25 °C
ILEAK
Switch Leakage Current
DCSO,
DCSG
0.1
1
µA
Tj = 25 °C
fSW
Switch Frequency
DCSO,
DCSG
230
460
kHz
Depending on DCCF
tSTART
Start Up Time to PUP-Enable
DCEN,
PUP
8
ms
VIN = 1.0 V,
ILOAD = 1 mA,
PUPLIM = 010 (Reset)
VSTARTTRAN
Start-Up to Normal Mode
Transition Voltage
VSENSE
1.9
V
156
VIN = 3.0 V, ILOAD = 0,
includ. switch current
1) see Section 4.2.4.2.
All measurements are made with a C8 R/4L 20 µH, 25 mΩ ferrite ring-core coil, Zetex ZLMCS1000 Schottky diode,
and Sanyo/Oscon 6SA330M 330 µF, 25 mΩ ESR capacitors at input and output (see Section 4.2.4. on page 47).
54
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
4.2.4.6. Typical Performance Characteristics
Efficiency vs. Load Current
(Vout=3.5V)
Efficiency vs. Load Current
(Vout=3.0V)
100
100
Vin
80
1.8 V
Efficiency (%)
Efficiency (%)
80
2.4 V
3.0 V
60
40
Vin:
3.0V
2.4V
1.8V
20
0
10 -4
10-3
10-2
10-1
Vin
0.7 V
60
Vin:
2.4V
1.8V
1.5V
1.2V
0.9V
0.7V
40
20
0
10 -4
1
Load Current (A)
10-3
10-2
10-1
1
Load Current (A)
Efficiency vs. Load Current
(Vout=2.7V)
Efficiency vs. Load Current
(Vout=2.2V)
100
100
Vin
2.4 V
Vin
80
1.5 V
80
Efficiency (%)
Efficiency (%)
1.2 V
60
40
Vin:
2.4V
1.8V
1.2V
20
0.7 V
60
40
Vin:
1.5V
1.2V
0.9V
0.7V
20
0
0
10 -4
10-3
10-2
Load Current (A)
10-1
1
10 -4
10-3
10-2
10-1
1
Load Current (A)
Fig. 4–20: Efficiency vs. Load Current
Micronas
55
MAS 3507D
PRELIMINARY DATA SHEET
Output Voltage vs. Input Voltage
Iload=250mA
Output Voltage vs. Input Voltage
Iload=50mA
3.6
3.2
3.1 V
3.5 V
3
3.4
Output Voltage (V)
Output Voltage (V)
2.8
3.2
3.1 V
3
2.8
2.7 V
2.6
2.4
2.2 V
2.2
2.7 V
2.6
2
1.5
2
2.5
3
3.5
0.9
Input Voltage (V)
1.4
1.9
2.4
2.9
Input Voltage (V)
Fig. 4–21: Output Voltage vs. Input Voltage
Output Voltage
vs. Load Current
3.6
Output Voltage
vs. Load Current
Vin
3.4
Vin=3V, 2.4V, 1.8V
3.4
Vin
3.2
3.2
Output Voltage
Output Voltage (V)
3
3
Vin=1.5V, 0.9V
2.8
2.6
2.4
Vin
2.8
2.2
Vin=1.5V, 0.9V
Vin=2.4V
2.6
0
0.1
2
0.2
Load Current (A)
0.3
0
0.02
0.04
0.06
0.08
Load Current (A)
Fig. 4–22: Output Voltage vs. Load Current
56
Micronas
MAS 3507D
PRELIMINARY DATA SHEET
0.8
6.0
0.6
3.5V
2.2V
Vout
0.4
Vout=
3.5V
3.1V
2.7V
2.2V
0.2
0
0
1
2
Input Voltage (V)
3
Vout = 3 V
No Load Supply Current (mA)
Maximum Load Current (A)
No Load Supply Current
vs. Input Voltage
Maximum Load Current
vs. Input Voltage
4.0
2.0
0
0
1
2
3
Input Voltage (V)
Fig. 4–23: Maximum Load Current vs. Input Voltage
Micronas
Fig. 4–24: No Load Supply Current vs. Input Voltage
57
MAS 3507D
PRELIMINARY DATA SHEET
3V
3V
3V
3V
0A
0A
0A
500 µs/Div
500.00 µs/Div
Vin = 1 V; Iload = 0 mA
Vin = 1.2 V; Vout = 3 V
1 Load Current
2 Output Voltage
3 Inductor Current
200.0 mA/Div
100.0 mV/Div / AC-coupled
500.0 mA/Div
1
2
3
4
V (DCEN)
V (PUP)
Inductor Current
Output Voltage
2.000 V/Div
2.000 V/Div
500.0 mA/Div
2.000 V/Div
Fig. 4–27: Startup Waveform
Fig. 4–25: Load Transient-Response
3V
200 mA
2V
5.00 ms/Div
Iload = 100 mA; Vout = 3 V
2.000 V/Div
1 Vin
2 Output Voltage 50.00 mV/Div / AC-coupled
3 Inductor Current 200.0 mA/Div
Fig. 4–26: Line Transient-Response
58
Micronas
PRELIMINARY DATA SHEET
Micronas
MAS 3507D
59
MAS 3507D
PRELIMINARY DATA SHEET
5. Data Sheet History
1. Preliminary data sheet: “MAS 3507D MPEG 1/2
Layer2/3 Audio Decoder”, Feb. 25, 1998,
6251-459-1PD. First release of the preliminary data
sheet.
2. Preliminary data sheet: “MAS 3507D MPEG 1/2
Layer 2/3 Audio Decoder”, Oct. 21, 1998,
6251-459-2PD. Second release of the preliminary data
sheet. Major changes:
– Table 3–20: Volume matrix conversion added
– Address for Prefactor register corrected
– Definition for register $aa changed
– Fig. 4–1: Outline Dimension for PLCC44 changed
– Fig. 4–2: PQFP44 package diagram changed
– Fig. 4–3 and Fig. 4–4: Pin configurations added
3. Preliminary data sheet: “MAS 3507D MPEG 1/2
Layer 2/3 Audio Decoder, March 16, 2000,
6251-459-3PD. Third release of the preliminary data
sheet.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-459-3PD
60
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
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Micronas GmbH.
Micronas