19-3662; Rev 1; 5/07 Push-Pull FET Driver with Integrated Oscillator and Clock Output Features The MAX5075 is a +4.5V to +15V push-pull, current-fed topology driver subsystem with an integrated oscillator for use in telecom module power supplies. The device drives two MOSFETs connected to a center-tapped transformer primary providing secondary-side, isolated, negative or positive voltages. This device features a programmable, accurate, integrated oscillator with a synchronizing clock output that synchronizes an external PWM regulator. A single external resistor programs the internal oscillator frequency from 50kHz to 1.5MHz. The MAX5075 incorporates a dual MOSFET driver with ±3A peak drive currents and 50% duty cycle. The MOSFET driver generates complementary signals to drive external ground-referenced n-channel MOSFETs. The MAX5075 is available with a clock output frequency to MOSFET driver frequency ratio of 1x, 2x, and 4x. The MAX5075 is available in a thermally enhanced 8-pin µMAX ® package and is specified over the -40°C to +125°C operating temperature range. ♦ Current-Fed, Push-Pull Driver Subsystem ♦ Programmable, Accurate Internal Oscillator ♦ Single +4.5V to +15V Supply Voltage Range ♦ Dual ±3A Gate-Drive Outputs ♦ 1mA Operating Current at 250kHz with No Capacitive Load ♦ Synchronizing Clock Frequency Generation Options ♦ Thermally Enhanced 8-Pin µMAX Package ♦ -40°C to +125°C Operating Temperature Range Ordering Information Applications Current-Fed, High-Efficiency Power-Supply Modules Power-Supply Building Subsystems PINPACKAGE TOP MARK PKG CODE fCLK/fNDRV_ RATIO MAX5075AAUA 8 µMAX-EP* AAAU U8E-2 1 MAX5075BAUA 8 µMAX-EP* AAAV U8E-2 2 MAX5075CAUA 8 µMAX-EP* AAAW U8E-2 4 PART *EP = Exposed paddle. Push-Pull Driver Subsystems µMAX is a registered trademark of Maxim Integrated Products, Inc. Note: All devices specified for -40°C to +125°C operating temperature range. Pin Configuration appears at end of data sheet. Typical Operating Circuit VIN VIN VOUT DRVH PWM CONTROLLER VCC VCC SYNCIN NDRV2 CLK MAX5075 NDRV1 RT DRVL GND 4.7kΩ I.C. PGND 1nF GND ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5075 General Description MAX5075 Push-Pull FET Driver with Integrated Oscillator and Clock Output ABSOLUTE MAXIMUM RATINGS VCC to DGND, PGND .............................................-0.3V to +18V CLK, RT to DGND.....................................................-0.3V to +6V NDRV1, NDRV2 to PGND...........................-0.3V to (VCC + 0.3V) DGND to PGND.....................................................-0.3V to +0.3V CLK Current......................................................................±20mA NDRV1, NDRV2 Peak Current (200ns) ..................................±5A NDRV1, NDRV2 Reverse Current (Latchup Current)......±500mA Continuous Power Dissipation (TA = +70°C) 8-Pin µMAX (derate 10.3mW/°C above +70°C) ...........825mW Operating Temperature Range .........................-40°C to +125°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +12V, RRT = 124kΩ, NDRV1 = NDRV2 = open, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are measured at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SUPPLY Input Voltage Supply Range VCC 4.5 Switching Supply Current ICCSW fOSC = 250kHz Undervoltage Lockout VUVLO VCC rising 3 UVLO Hysteresis 15.0 V 1 3 mA 3.5 4 300 V mV OSCILLATOR Frequency Range fOSC Accuracy (Note 2) 50 1500 kHz fOSC = 250kHz , 6V ≤ VCC ≤ 15V (Note 3) -8 +10 % Oscillator Jitter ±0.6 CLK Output High Voltage ICLK = 1mA % 7V ≤ VCC ≤ 15V 3.9 5.0 4.5V ≤ VCC ≤ 7V 3.35 5.0 50 V CLK Output Low Voltage ICLK = -1mA CLK Output Rise Time CCLK = 30pF 35 mV ns CLK Output Fall Time CCLK = 30pF 10 ns GATE DRIVERS (NDRV1, NDRV2) Output High Voltage VOH INDRV1 = INDRV2 = 100mA Output Low Voltage VOL INDRV1 = INDRV2 = -100mA Output Peak Current IP Driver Output Impedance Latchup Current Protection Sourcing and sinking VCC 0.3 V 0.3 3 V A NDRV_ sourcing 100mA 1.8 3 NDRV_ sinking 100mA 1.6 2.6 Ω Reverse current at NDRV1/NDRV2 400 mA Rise Time tR CLOAD = 2nF 10 ns Fall Time tF CLOAD = 2nF 10 ns Note 1: The MAX5075 is 100% tested at TA = TJ = +125°C. All limits over temperature are guaranteed by design. Note 2: Use the following formula to calculate the MAX5075 oscillator frequency: fOSC = 1012/(32 x RRT). Note 3: The accuracy of the oscillator’s frequency is lower at frequencies greater than 1MHz. 2 _______________________________________________________________________________________ Push-Pull FET Driver with Integrated Oscillator and Clock Output SUPPLY CURRENT vs. CCLK 3 fOSC = 250kHz fOSC = 100kHz 2 fOSC = 50kHz 1 0 1.35 1.30 1.25 1.20 1.15 7 8 1.10 1.08 1.06 1.04 1.02 9 10 11 12 13 14 15 MAX5075 toc03 1.12 1.05 1.00 0 20 40 60 100 80 -50 -25 0 25 50 75 SUPPLY VOLTAGE (V) CCLK (pF) TEMPERATURE (°C) CLK RISE TIME vs. SUPPLY VOLTAGE CLK RISE TIME vs. TEMPERATURE CLK FALL TIME vs. SUPPLY VOLTAGE CCLK = 30pF 45 39.5 MAX5075 toc04 50 40 39.0 CLK RISE TIME (ns) 35 CCLK = 30pF 30 25 20 15 10 38.5 38.0 37.5 100 125 14 CCLK = 30pF 12 CLK FALL TIME (ns) 6 1.14 1.10 MAX5075 toc05 5 fOSC = 250kHz 1.16 1.00 4 10 8 6 4 37.0 2 5 0 36.5 5 6 7 8 9 10 11 12 13 14 15 -50 -25 0 SUPPLY VOLTAGE (V) 25 50 75 100 4 125 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V) TEMPERATURE (°C) CLK FALL TIME vs. TEMPERATURE OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 12 CCLK = 30pF 10 8 6 4 2 256 RRT = 124kΩ OSCILLATOR FREQUENCY (kHz) 4 TA = -40°C 254 MAX5075 toc08 0 CLK FALL TIME (ns) CLK RISE TIME (ns) 1.18 MAX5075 toc06 fOSC = 500kHz 1.20 SUPPLY CURRENT (mA) 4 1.40 MAX5075 toc07 SUPPLY CURRENT (mA) 5 RRT = 124kΩ 1.45 SUPPLY CURRENT (mA) fOSC = 1.25MHz 6 1.50 MAX5075 toc01 7 SUPPLY CURRENT vs. TEMPERATURE MAX5075 toc02 SUPPLY CURRENT vs. SUPPLY VOLTAGE 252 TA = +25°C 250 248 246 TA = +125°C 244 0 242 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 4 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3 MAX5075 Typical Operating Characteristics (VCC = +12V, RRT = 124kΩ, NDRV_ = open, CLK = open.) Typical Operating Characteristics (continued) (VCC = +12V, RRT = 124kΩ, NDRV_ = open, CLK = open.) NDRV FREQUENCY vs. CLK FREQUENCY OSCILLATOR FREQUENCY vs. RRT 100 MAX5075 toc11 MAX5075 toc10 RRT = 124kΩ NDRV1 5V/div 5A 700 600 MA X50 7 NDRV FREQUENCY (kHz) 1000 MAX5075A WAVEFORM 800 MAX5075 toc09 10,000 OSCILLATOR FREQUENCY (kHz) MAX5075 Push-Pull FET Driver with Integrated Oscillator and Clock Output 500 B 75 50 AX M 400 75C NDRV2 5V/div X50 300 MA 200 100 10 CLK 5V/div 0 10 100 1000 0 250 RRT (kΩ) 500 750 1000 1250 1500 MAX5075B WAVEFORM MAX5075C WAVEFORM MAX5075 toc12 MAX5075 toc13 RRT = 124kΩ RRT = 124kΩ 2µs/div 4 2µs/div CLK FREQUENCY (kHz) NDRV1 5V/div NDRV1 5V/div NDRV2 5V/div NDRV2 5V/div CLK 5V/div CLK 5V/div 4µs/div _______________________________________________________________________________________ Push-Pull FET Driver with Integrated Oscillator and Clock Output PIN NAME FUNCTION 1 CLK Synchronizing Clock Output. Clock output with a ±10mA peak current drive that can be used to synchronize an external PWM regulator. CLK/NDRV1 frequency has a 1x, 2x, or 4x ratio. See the Synchronizing Clock Output section. 2 I.C. Internal Connection. Connect to ground. Internal function. 3 RT Oscillator Timing Resistor Connection. Bypass RT with a series combination of a 4.7kΩ resistor and a 1nF capacitor to DGND. Connect a resistor from RT to DGND to set the internal oscillator. 4 DGND Digital Ground. Connect DGND to ground plane. 5 PGND Power Ground. Connect PGND to ground plane. 6 NDRV1 Gate Driver 1. Connect NDRV1 to the gate of the external n-channel FET. 7 NDRV2 Gate Driver 2. Connect NDRV2 to the gate of the external n-channel FET. 8 VCC EP EP Power-Supply Input. Bypass VCC to PGND with 0.1µF||1µF ceramic capacitors. Exposed Pad. Internally connected to DGND. Connect exposed pad to ground plane. MAX5075 A (1x) B (2x) UVLO 3.5V VCC C (4x) VCC Q 5V LDO Q NDRV2 Q T-FF Q NDRV1 CLK PGND Q Q RT OSC DGND INTERNAL FUNCTION I.C. Figure 1. MAX5075 Functional Diagram _______________________________________________________________________________________ 5 MAX5075 Pin Description MAX5075 Push-Pull FET Driver with Integrated Oscillator and Clock Output Detailed Description The MAX5075 is a +4.5V to +15V push-pull, current-fed topology driver subsystem with an integrated oscillator for use in 48V module power supplies. The MAX5075 features a programmable, accurate integrated oscillator with a synchronizing clock output that can be used to synchronize an external PWM stage. A single external resistor programs the internal oscillator frequency from 50kHz to 1.5MHz. The MAX5075 incorporates a dual MOSFET driver with ±3A peak drive currents and a 50% duty cycle. The MOSFET driver generates complementary signals to drive external ground-referenced n-channel MOSFETs. The MAX5075 is available with a clock output frequency to MOSFET driver frequency ratios of 1x , 2x, and 4x. Table 1. MAX5075 CLK Output Frequency PART fCLK fNDRV1 fCLK to fSW RATIO MAX5075A fOSC / 2 fOSC / 2 1 MAX5075B fOSC fOSC / 2 2 MAX5075C fOSC fOSC / 4 4 NDRV2 NDRV1 CLK OSC MAX5075A Internal Oscillator An external resistor at RT programs the MAX5075 internal oscillator frequency from 50kHz to 1.5MHz. The MAX5075A/B NDRV1 and NDRV2 switching frequencies are one-half the programmed oscillator frequency with a nominal 50% duty cycle. The MAX5075C NDRV1 and NDRV2 switching frequencies are one-fourth the oscillator frequency. Use the following formula to calculate the internal oscillator frequency: NDRV2 NDRV1 CLK OSC MAX5075B NDRV2 NDRV1 CLK 12 fOSC = 10 32 xRRT where fOSC is the oscillator frequency and RRT is a resistor connected from RT to DGND in ohms. Place a series combination of a 4.7kΩ resistor and a 1nF capacitor from RT to DGND for stability and to filter out noise. Synchronizing Clock Output The MAX5075 provides a buffered clock output that can be used to synchronize the oscillator input of a PWM controller. CLK is powered from an internal 5V regulator and sources/sinks up to 10mA. The MAX5075 has internal CLK output frequency to NDRV1 and NDRV2 switching frequency ratios set to 1x, 2x, or 4x (Table 1). The MAX5075A has a CLK frequency to NDRV_ frequency ratio set to 1x. The MAX5075B has a CLK frequency to NDRV_ frequency ratio set to 2x and the MAX5075C has a CLK frequency to NDRV_ frequency ratio set to 4x. There is a typical 30ns delay from CLK to NDRV_ output. 6 OSC MAX5075C Figure 2. MAX5075 CLK Timing Diagrams Applications Information Supply Bypassing Pay careful attention to bypassing and grounding the MAX5075. Peak supply and output currents may exceed 3A when driving large MOSFETs. Ground shifts due to insufficient device grounding may also disturb other circuits sharing the same ground-return path. Any series inductance in the VCC, NDRV1, NDRV2, and/or GND paths can cause noise due to the very high di/dt when switching the MAX5075 with any capacitive load. Place one or more 0.1µF ceramic capacitors in parallel as close to the device as possible to bypass VCC to PGND. Use a ground plane to minimize ground-return resistance and inductance. Place the external MOSFETs as close as possible to the MAX5075 to further minimize board inductance and AC path impedance. _______________________________________________________________________________________ Push-Pull FET Driver with Integrated Oscillator and Clock Output • Two AC current loops form between the device and the gate of the driven MOSFETs. The MOSFETs look like a large capacitance from gate to source when the gate pulls low. The current loop is from the MOSFET gate to NDRV1 and NDRV2 of the MAX5075, to PGND, and to the source of the MOSFET. When the gate of the MOSFET pulls high, the current is from the VCC terminal of the decoupling capacitor, to VCC of the MAX5075, to NDRV1 and NDRV2, and to the MOSFET gate and source. Both charging current and discharging current loops are important. Minimize the physical distance and the impedance in these AC current paths. • Keep the device as close to the MOSFET as possible. PDISS = VCC x ICCSW For capacitive loads, use the following equation to estimate the power dissipation: PLOAD = 2 x CLOAD x VCC2 x fNDRV_ where C LOAD is the capacitive load at NDRV1 and NDRV2, VCC is the supply voltage, and fNDRV_ is the MAX5075 NDRV_ switching frequency. Pin Configuration Calculate the total power dissipation (PT) as follows: PT = PDISS + PLOAD Layout Recommendations The MAX5075 sources and sinks large currents that can create very fast rise and fall edges at the gate of the switching MOSFETs. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. Use the following PC board layout guidelines when designing with the MAX5075: • Place one or more 0.1µF decoupling ceramic capacitors from V CC to PGND as close to the device as possible. Connect VCC and all ground pins to large copper areas. Place one bulk capacitor of 10µF on the PC board with a low-impedance path to the VCC input and PGND of the MAX5075. TOP VIEW CLK 1 I.C. 2 RT 3 DGND 4 8 *EP MAX5075 VCC 7 NDRV2 6 NDRV1 5 PGND µMAX *EXPOSED PADDLE CONNECTED TO DGND. Chip Information TRANSISTOR COUNT: 1335 PROCESS: BiCMOS _______________________________________________________________________________________ 7 MAX5075 Power Dissipation The power dissipation of the MAX5075 is a function of the sum of the quiescent current and the output current (either capacitive or resistive load). Maintain the sum of the currents so the maximum power dissipation limit is not exceeded. The power dissipation (PDISS) due to the quiescent switching supply current (ICCSW) can be calculated as: Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 8L, µMAX, EXP PAD.EPS MAX5075 Push-Pull FET Driver with Integrated Oscillator and Clock Output 21-0107 C 1 1 Revision History Pages changed at Rev 1: 1, 2, 5, 6, 8 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.