HV7022-C 34-Channel Symmetric Row Driver Ordering Information Package Options Device 44 J-Lead Quad Ceramic Chip Carrier 44 J-Lead Quad Plastic Chip Carrier Die in waffle pack 44 J-Lead Quad Ceramic Chip Carrier (MIL-Std-883 Processed*) HV7022DJ-C HV7022PJ-C HV7022X-C RBHV7022DJ-C HV7022-C *For Hi-Rel process flows, refer to page 5-3 of the databook. Features General Description ❏ Processed with HVCMOS® technology The HV7022-C is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suited for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. The HV70 offers 34 output lines, a direction (DIR) pin to give CW or CCW shift register loading, output enable (OE), and polarity (POL) control. After DATA INPUT is entered (on the falling edge of CLOCK), a logic high will cause the output to swing to VPP if POL is high, or to GND if POL is low. ❏ Symmetric row drive (reduces latent imaging in ACTFEL displays) ❏ Output voltages up to 230V ❏ Low-power level shifting ❏ Source/Sink current 70mA (min.) ❏ Shift register speed 4MHz ❏ Pin-programmable shift direction ❏ 44-lead plastic & ceramic surface-mount packages ❏ Hi-Rel processing available Absolute Maximum Ratings Supply voltage, VDD1 -0.3V to +15V VPP1 -0.3V to +250V Supply voltage, Logic input Ground levels1 -0.3V to VDD +0.3V current 2 Continuous total power 1.5A dissipation3: Operating temperature range Plastic Ceramic Plastic Ceramic Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds 1200mW 1500mW -40°C to +85°C -55°C to 125°C -65°C to +150°C 260°C Notes: 1. All voltages are referenced to GND. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 25mW/°C for plastic and at 15mW/°C for ceramic. For Detailed circuit and application information, please refer to Application Note AN-H3. 02/96/022 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, 1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. HV7022-C Electrical Characteristics (over recommended operating conditions of VDD = 12V, TA = 25°C and VPP = 230V unless otherwise noted) DC Characteristics Symbol Parameter Min Max Units Conditions IDD VDD supply current 10 mA fCLK = 4MHz IPP High voltage supply current 4 mA 1 Output high1 100 µA All Outputs low or High-Z 750 µA All Outputs low or High-Z (125°C) 100 µA All VIN = GND or VDD IDDQ Quiescent VDD supply current VOH High-level output VOL Low-level output HVOUT 195 V IO= -70mA (-50mA)2 Data out 11 V IO= -500µA HVOUT 30 V IO= 70mA (+50mA)2 Data out 1 V IO= 500µA IIH High-level logic input current 1 µA VIH = 12V IIL Low-level logic input current -1 µA VIL = 0V Notes: 1. The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation. 2. Over military temperature range (-55°C to 125°C). AC Characteristics (VDD = 12V, TC = 25°C) Symbol Parameter Min Max Units fCLK Clock frequency 4 MHz tW Pulse duration clock high or low 125 ns tSUD Data set-up time before falling clock 100 ns tHD Data hold time after falling clock 100 ns tSUC Setup time clock low before VPP↑ or GND↓ 300 ns tSUE Setup time enable high before VPP↑ or GND↓ 300 ns tSUP Setup time polarity high or low before VPP↑ or GND↓ 300 ns tHC Hold time clock high after VPP↑ or GND↓ 500 ns tHE Hold time enable high after VPP↑ or GND↓ 300 ns 300 Conditions tHP Hold time polarity high or low after VPP↑ or GND↓ tDHL Delay time high to low level output from clock 150 ns CL = 10pF t DLH Delay time low to high level output from clock 200 ns CL = 10pF tTHL Transition time high to low level serial output 200 ns CL = 15pF tTLH Transition time low to high level serial output 100 ns CL = 15pF tONH High level turn-on time Q outputs from enable 500 ns IO = -50 mA,VOH =195V RL = 2 kΩ to 95V tONL Low level turn-on time Q outputs from enable 500 ns IO = 50 mA,VOH =130V RL = 2 kΩ to 30V tOFFH High level turn-off time Q outputs from enable 1000 ns IO = -50 mA,VOH =195V RL = 2 kΩ to 95V tOFFL Low level turn-off time Q outputs from enable 500 ns IO = 50 mA,VOH =130V RL = 2 kΩ to 30V Slew rate, VPP or GND 45 V/µs With one active output driving a 4.7 nF load to VPP or GND 2 ns HV7022-C Recommended Operating Conditions Symbol Parameter VDD Logic supply voltage VPP High voltage supply VIH High-level input voltage VIL Low-level input voltage fCLK Clock frequency TA Operating free-air temperature IOD Min Max Units 10.8 13.2 V 230 V VDD = 10.8V 8.1 VDD = 13.2V 9.9 V VDD = 10.8V 2.7 VDD = 13.2V 3.3 V 4 MHz Plastic -40 +85 °C Ceramic -55 +125 °C ±300 mA Allowable pulse current through output diodes Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Input and Output Equivalent Circuits VDD VDD VPP Data Out Input GND GND Logic Inputs HVOUT GND Logic Data Output 3 High Voltage Outputs HV7022-C Switching Waveforms l/fCLK tWL tWH VIH Clock 50% 50% tSUD Data Input 50% tHD VIH 50% 50% VIL tDLH Data Output (D IOA/D IOB) tDHL 90% 10% 10% tTLH V PP VOH 90% VOL tTHL 10% tHC tSUC 90% GND VIH POL 50% 50% VIL 90% GND tHP tSUP V PP 10% OE VIH 50% 50% VIL tHE tSUE VOH 90% HV OUT 10% High Impedance tONH tOFFH High Impedance 90% HV OUT 10% VOL tONL tOFFL 4 HV7022-C Functional Block Diagram VPP OE Polarity VDD P LT HVOUT1 Data In N LT CLK HVOUT2 S/R DIR LT HVOUT34 Data Out LT = Level Translator GND Function Table Inputs Outputs I/O CLK Relations DIR Data POL OE Shift Reg HV Outputs Data Out O/P HIGH X X H H H * H O/P OFF X X L H H * HIGH-Z * O/P LOW X X H L H * L * O/P OFF X X L L H * HIGH-Z * O/P OFF X X X X L * All O/P HIGH-Z * ↓ L X X X Qn →Qn+1 * Q34 ↓ H X X X Qn →Qn-1 * Q1 No ↓ X X X X * No Change No Change Load S/R, set DIR Notes: H = logic high level, L = logic low level, X = irrelevant, ↓ = high-to-low transition, Q1 = HVOUT 1, Qn = HVOUT(n), etc. * = dependent on previous state and whether an O/P or S/R command occured. 5 HV7022-C HVOUT Characteristics Temp = 25°C 180 140 140 VDD = 12 100 VDD = 14 I(mA) I(mA) Temp = 25°C 180 VDD = 10 60 VPP > 40V VDD = 12V & 14 V 100 60 20 20 0 20 40 60 80 100 0 20 Output N-Channel Characteristics through FET 100 Package Outline HV70 44 Pin J-Lead Package Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 80 Output P-Channel Characteristics through FET Pin Configurations Function HVOUT 18/17 HVOUT 17/18 HVOUT 16/19 HVOUT 15/20 HVOUT 14/21 HVOUT 13/22 HVOUT 12/23 HVOUT 11/24 HVOUT 10/25 HVOUT 9/26 HVOUT 8/27 HVOUT 7/28 HVOUT 6/29 HVOUT 5/30 HVOUT 4/31 HVOUT 3/32 HVOUT 2/33 HVOUT 1/34 Data Out Output Enable Clock GND 60 Volts (VPP - VOUT) Volts Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 Function DIR VDD Polarity Data In VPP N/C HVOUT 34/1 HVOUT 33/2 HVOUT 32/3 HVOUT 31/4 HVOUT 30/5 HVOUT 29/6 HVOUT 28/7 HVOUT 27/8 HVOUT 26/9 HVOUT 25/10 HVOUT 24/11 HVOUT 23/12 HVOUT 22/13 HVOUT 21/14 HVOUT 20/15 HVOUT 19/16 40 28 41 27 42 26 43 25 44 24 1 23 2 22 3 21 4 20 5 19 6 18 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin J-Lead Package Note: Pin designation for DIR L/H Example:For DIR = L, pin 1 is HVOUT 18 For DIR = H, pin 1 is HVOUT 17 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 6 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com Package Outline 44-Lead PQFP Package Outline (PG) D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 Gauge Plane 48 L 1 θ L1 b Seating Plane e Top View View B View B A A2 Seating Plane A1 Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX A A1 A2 b D D1 E E1 - 0.25 1.95 0.30 13.65 9.80 13.65 9.80 2.45 - 2.00 2.10 0.45 13.90 14.15 JEDEC Registration M0-112, Variation AA-2, Issue B, Sep.1995. Doc. #: DSPD-44PQFPPG A031607 10.00 10.20 13.90 14.15 10.00 10.20 e L L1 L2 0.73 0.80 BSC 0.88 1.03 1.95 REF 0.25 BSC θ θ1 3.5O 5O - - O 7 16O Package Outline 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max.), .050in pitch D D1 1 44 .048/.042 x 45O 6 .150 MAX .056/.042 x 45O 40 Note 1 (Index Area) .075 MAX E1 E Note 2 (3 places) 0.20max 3 Places Top View Side View View B b1 A Base Plane A2 .020 MIN Seating Plane e A1 b Side View View B Note: 1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Exact shape of this feature is optional. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 NOM .172 .105 - - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .036 .695 .656 .695 .656 JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. Drawings are not to scale. Doc. #: DSPD-44PLCCPJ B051607 e .050 BSC