TI PCI2030

PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
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Supports PCI Local Bus Specification 2.1
and PCI-to-PCI Bridge Specification 1.0
3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments
Supports Two 32-Bit, 33-MHz PCI Buses
Provides Internal Arbitration for Up to Six
Secondary Bus Masters With
Programmable Control
Provides Six Secondary PCI Bus Clock
Outputs
Supports Burst Transfers to Maximize Data
Throughput on Both PCI Buses
Provides Two Extension Windows
EEPROM Interface for Loading Texas
Instruments (TI) Subsystem ID and
Subsystem Vendor ID
Four Primary and Four Secondary
General-Purpose I/Os
Independent Read and Write Buffers for
Each Direction
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Secondary Positive Decode
Predictable Latency: Compliant With PCI
Local Bus Specification 2.1
External Arbiter Option
Provides Concurrent Operation
Serial IRQ Bridging
Propagates Bus Locking
Supports PCI Clock Run
Secondary Bus Driven Low During Reset
Docking Connect Detects
PCI Local Bus Specification 2.0-Compliant
Device Optimization
Advanced Submicron, Low-Power CMOS
Technology
Provides VGA/Palette Memory and I/O, and
Subtractive Decoding Options
Packaged in 176-Pin Plastic Quad Flatpack
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions for PCI Interface . . . . . .
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Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . .
PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
description
The TI PCI2030 PCI-to-PCI bridge provides a high-performance connection path between two peripheral
component interconnect (PCI) buses. Transactions can occur between a master on one PCI bus and a target
on another PCI bus. The bridge supports burst-mode transfers to maximize data throughput, and the two bus
traffic paths through the bridge act independently.
The PCI2030 bridge is compliant with the PCI Local Bus Specification 2.1, and can be used to overcome the
electrical loading limit of ten devices per PCI bus by creating hierarchical buses. Furthermore, add-in cards
requiring multiple PCI devices can use the bridge to overcome the electrical loading limit of one PCI device
per slot.
The PCI2030 bridge is also compliant with the PCI-to-PCI Bridge Specification 1.0, and implements many
additional features that make it an ideal solution for bridging two PCI buses. It can be configured for subtractive
decoding, and negative decoding can be disabled on the secondary interface. Two extension windows are also
included for special decoding purposes. The serial- and parallel-port addresses can also be programmed for
positive decoding on the primary interface. The bridge implements many other features, listed above, that add
performance and flexibility.
An advanced CMOS process is utilized to achieve low system-power consumption while operating at PCI clock
rates up to 33 MHz.
system block diagram
Primary PCI Bus
Video Controller
IDE Controller
PCI2030
PCI-To-PCI Bridge
Secondary PCI Bus
Add-In Card
2
Add-In Card
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South Bridge
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
terminal assignments
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56
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54
53
52
51
50
49
48
47
46
45
S_AD16
S_C/BE2
GND
S_FRAME
VCC
S_IRDY
S_TRDY
S_DEVSEL
S_STOP
S_VCCP
S_LOCK
GND
S_PERR
S_SERR
S_PAR
S_C/BE1
S_AD15
S_AD14
VCC
S_AD13
S_AD12
S_AD11
VCC
S_AD10
S_AD9
GND
S_AD8
S_C/BE0
S_AD7
S_VCCP
S_AD6
S_AD5
VCC
S_AD4
S_AD3
GND
S_AD2
S_AD1
S_AD0
GND
P_GPIO0
P_GPIO1
P_GPIO2
P_GPIO3
1
2
3
4
5
6
7
8
9
10
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12
13
14
15
16
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168
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P_AD19
P_AD18
P_AD17
P_AD16
GND
P_C/BE2
P_FRAME
P_IRDY
P_TRDY
P_DEVSEL
P_STOP
V CC
P_LOCK
P_V CCP
P_PERR
P_SERR
P_PAR
P_C/BE1
P_GND
P_AD15
P_AD14
GND
P_AD13
P_AD12
P_AD11
V CC
P_AD10
P_V CCP
P_AD9
GND
P_AD8
P_C/BE0
GND
P_AD7
P_AD6
V CC
P_AD5
P_AD4
P_AD3
V CC
P_AD2
P_V CCP
P_AD1
P_AD0
S_GPIO1
S_GPIO2
S_GPIO3
GND
S_PCLK0
S_PCLK1
VCC
S_PCLK2
S_VCCP
S_PCLK3
S_PCLK4
VCC
S_PCLK5
GND
RST_MODE
P_CLKRUN
P_VCCP
P_RST
GND
P_CLK
VCC
P_GNT
P_REQ
P_VCCP
P_AD31
VCC
P_AD30
P_AD29
VCC
P_AD28
P_AD27
P_AD26
GND
P_AD25
P_AD24
P_C/BE3
GND
P_IDSEL
P_AD23
VCC
P_AD22
P_VCCP
P_AD21
P_AD20
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S_GPIO0
S_FLSHREQ
S_FLSHACK
S_EXTARB
V CC
S_CLKRUN
S_RST
S_GNT5
S_GNT4
S_GNT3
S_GNT2
GND
S_GNT1
S_GNT0
S_REQ5
S_VCCP
S_REQ4
S_REQ3
V CC
S_REQ2
S_REQ1
S_REQ0
S_AD31
S_AD30
S_AD29
GND
S_AD28
S_AD27
S_AD26
GND
S_AD25
S_AD24
V CC
S_C/BE3
S_VCCP
S_AD23
S_AD22
S_AD21
S_AD20
GND
S_AD19
S_AD18
S_AD17
V CC
PGF PACKAGE
(TOP VIEW)
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3
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions
primary PCI system
TERMINAL
NAME
NO.
I/O
TYPE
FUNCTION
P_CLK
152
I
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI signals
are sampled at rising edge of P_CLK.
R_RST
150
I
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to 3-state all output buffers
and reset all internal registers. When asserted, the device is completely nonfunctional. During P_RST, the
secondary interface is driven low. After P_RST is deasserted, the bridge is in its default state.
primary PCI address and data
TERMINAL
4
I/O
TYPE
FUNCTION
I/O
Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary bus PCI cycle, P_AD31–P_AD0 contain a 32-bit address
or other destination information. During the data phase, P_AD31–P_AD0 contain data.
168
6
18
32
I/O
Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary bus PCI cycle, P_C/BE3–P_C/BE0 define the bus command. During the
data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full
32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7–P_AD0), P_C/BE1 applies to
byte 1 (P_AD15–P_AD8), P_C/BE2 applies to byte 2 (P_AD23–P_AD16), and P_C/BE3 applies to byte 3
(P_AD31–P_AD24).
148
I/O
Primary PCI bus clock run. P_CLKRUN is used by the central resource to request permission to stop the
PCI clock or to slow it down.
NAME
NO.
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
P_AD8
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
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160
162
163
164
166
167
171
173
175
176
1
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4
20
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23
24
25
27
29
31
34
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P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
P_CLKRUN
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PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions (Continued)
primary PCI interface control
TERMINAL
NAME
NO.
I/O
TYPE
FUNCTION
P_DEVSEL
10
I/O
Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the primary bus, the bridge monitors P_DEVSEL until a target responds. If no target responds
before time-out occurs, then the bridge terminates the cycle with an initiator abort.
P_FRAME
7
I/O
Primary cycle frame. P_FRAME is driven by the initiator of a primary bus cycle. P_FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
P_FRAME is deasserted, the primary bus transaction is in the final data phase.
P_GNT
154
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Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access to the
primary PCI bus after the current data transaction has completed. P_GNT may or may not follow a primary
bus request, depending on the primary bus parking algorithm.
P_GPIO3
P_GPIO2
P_GPIO1
P_GPIO0
45
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47
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I/O
Primary bus general-purpose I/O terminals. These terminals are provided for general input/output use in
system design.
Initialization device select. P_IDSEL selects the bridge during configuration space accesses. P_IDSEL can
be connected to one of the upper 24 PCI address lines on the primary PCI bus.
P_IDSEL
170
I
P_IRDY
8
I/O
Primary initiator ready. P_IRDY indicates the primary bus initiator’s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY and P_TRDY
are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are inserted.
P_LOCK
13
I/O
Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as an initiator.
P_PAR
17
I/O
Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the P_AD
and P_C/BE buses. As an initiator during PCI write cycles, the bridge outputs this parity indicator with a
one-P_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the initiator’s parity
indicator; a misdemeanor can result in a parity error assertion (P_PERR).
P_PERR
15
I/O
Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated parity
does not match P_PAR when P_PERR is enabled through bit 6 of the command register.
P_REQ
155
O
Primary PCI bus request. P_REQ is asserted by the bridge to request access to the primary PCI bus as an
initiator.
Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space of the
bridge can only be accessed from the primary bus.
P_SERR
16
O
Primary system error. Output pulsed from the bridge when enabled through the command register indicating
a system error has occurred. The bridge need not be the target of the primary PCI cycle to assert P_SERR.
When bit 6 is enabled in the bridge control register, P_SERR will also pulse, indicating that a system error
has occurred on one of the subordinate buses downstream from the bridge.
P_STOP
11
I/O
Primary cycle stop signal. P_STOP is driven by a PCI target to request the initiator to stop the current primary
bus transaction. P_STOP is used for target disconnects and is commonly asserted by target devices that do
not support burst data transfers.
RST_MODE
147
I
If RST_MODE is asserted during P_RST, it causes S_RST to be asserted and the secondary clocks to be
turned off.
P_TRDY
9
I/O
Primary target ready. P_TRDY indicates the primary bus target’s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY and P_TRDY
are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are inserted.
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5
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions (Continued)
secondary PCI system
TERMINAL
6
I/O
TYPE
FUNCTION
145
143
142
140
138
137
O
Secondary PCI bus clock. Provides timing for all transactions on the secondary PCI bus. All secondary PCI
signals are sampled at the rising edge of S_CLK5–S_CLK0.
S_CLKRUN
127
I/O
Secondary PCI bus clock run. S_CLKRUN is output by the bridge to indicate that S_CLK will be stopped.
S_CLKRUN is driven by secondary bus PCI devices to request that S_CLK be stopped.
S_EXTARB
129
I
Secondary external arbiter enable. When S_EXTARB is asserted, the secondary external arbiter is enabled.
When the external arbiter is enabled, S_REQ0 is reconfigured as a secondary bus grant input to the bridge
and S_GNT0 is reconfigured as a secondary bus master request to the external arbiter on the secondary bus.
S_RST
126
O
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit of the
bridge control register. S_RST is asynchronous with respect to the state of the secondary interface CLK
signal.
NAME
NO.
S_PCLK5
S_PCLK4
S_PCLK3
S_PCLK2
S_PCLK1
S_PCLK0
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PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions (Continued)
secondary PCI address and data
TERMINAL
I/O
TYPE
FUNCTION
I/O
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on the
secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31–S_AD0 contain a
32-bit address or other destination information. During the data phase, S_AD31–S_AD0 contain data.
99
87
73
61
I/O
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a secondary bus PCI cycle, S_C/BE3–S_C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths
of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0 (S_AD7–S_AD0), S_C/BE1
applies to byte 1 (S_AD15–S_AD8), S_C/BE2 applies to byte 2 (S_AD23–S_AD16), and S_C/BE3 applies
to byte 3 (S_AD31–S_AD24).
S_DEVSEL
81
I/O
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the secondary bus, the bridge monitors S_DEVSEL until a target responds. If no target responds
before timeout occurs, then the bridge terminates the cycle with an initiator abort.
S_FRAME
85
I/O
Secondary cycle frame. S_FRAME is driven by the initiator of a secondary bus cycle. S_FRAME is asserted
to indicate that a bus transaction is beginning and data transfers continue while S_FRAME is asserted. When
S_FRAME is deasserted, the secondary bus transaction is in the final data phase.
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
125
124
123
122
120
119
NAME
NO.
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
110
109
108
106
105
104
102
101
97
96
95
94
92
91
90
88
72
71
69
68
67
65
64
62
60
58
57
55
54
52
51
50
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
O
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used to grant
potential secondary PCI bus masters access to the bus. Seven potential initiators (including the bridge) can
be located on the secondary PCI bus.
When the internal arbiter is disabled, S_GNT0 is reconfigured as an external secondary bus request signal
for the bridge.
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7
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions (Continued)
secondary PCI interface control
TERMINAL
I/O
TYPE
FUNCTION
135
134
133
132
I/O
Secondary general-purpose I/O terminals. These terminals are provided for general-purpose input/output
use in system design.
S_IRDY
83
I/O
Secondary initiator ready. S_IRDY indicates the secondary bus initiator’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and
S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_LOCK
78
I/O
Secondary lock S_LOCK is used to lock the secondary bus and gain exclusive access as an initiator.
NAME
NO.
S_GPIO3
S_GPIO2
S_GPIO1
S_GPIO0
S_PAR
74
I/O
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across the
S_AD and S_C/BE buses. As an initiator during PCI write cycles, the bridge outputs this parity indicator with
a one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the initiator’s
parity indicator. A miscompare can result in a parity error assertion (S_PERR).
S_PERR
76
I/O
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that
calculated parity does not match S_PAR when enabled through the command register.
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
118
116
115
113
112
111
I
S_SERR
75
I
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled through
the bridge control register. S_SERR is never asserted by the bridge.
S_STOP
80
I/O
Secondary cycle stop signal. S_STOP is driven by a PCI target to request the initiator to stop the current
secondary bus transaction. S_STOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
S_TRDY
82
I/O
Secondary target ready. S_TRDY indicates the secondary bus target’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and
S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_FLSHREQ
131
I
Flush request. When S_FLSHREQ is asserted, it signals a request to the PCI2030 to suspend internal write
posting. When the bridge is ready to suspend internal write posting, it responds by asserting S_FLSHACK.
S_FLSHACK remains asserted until the write posting buffers are empty.
S_FLSHACK
130
O
Flush acknowledge. S_FLSHACK is asserted by the PCI2030 to indicate that the internal write posting is
suspended. S_FLSHACK remains asserted until the write posting buffers are empty.
Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used as
inputs from secondary PCI bus initiators requesting the bus. Seven potential initiators (including the bridge)
can be located on the secondary PCI bus.
When the internal arbiter is disabled, S_REQ0 is reconfigured as an external secondary bus grant for the
bridge.
power supply
TERMINAL
8
FUNCTION
NAME
NO.
GND
5, 19, 22. 30, 33, 49, 53, 63, 77, 86, 93, 103,
107, 121, 136, 146, 151, 161, 165, 169
VCC
12, 26, 36, 40, 56, 66, 70, 84, 89, 100, 114,
128, 139, 144, 153, 158, 172
P_VCCP
14, 28, 42, 149, 156, 174
Primary bus-signaling environment supply. P_VCCP is used in protection circuitry
on primary bus I/O signals.
S_VCCP
59, 79, 98, 117, 141
Secondary bus-signaling environment supply. S_VCCP is used in protection
circuitry on primary bus I/O signals.
Device ground terminals
Power-supply terminal for core logic (3.3 V)
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PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
absolute maximum ratings over operating temperature ranges (unless otherwise noted)†
Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input voltage range, VI: Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO: Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies to external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals.
2. Applies to external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals.
recommended operating conditions
MIN
tt
TA
Input transition (rise and fall) time
CMOS compatible
1
Operating ambient temperature range
Commercial
0
TJ‡
Virtual junction temperature
Commercial
0
NOM
MAX
UNIT
4
ns
25
70
°C
25
115
°C
‡ These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
recommended operating conditions for PCI interface
OPERATION
VCC
Core voltage
Commercial
3.3 V
VCCP
PCI supply voltage
Commercial
VI
Input voltage
VO§
Output voltage
VIH¶
High le el input
High-level
inp t voltage
oltage
CMOS compatible
VIL¶
Low level input voltage
Low-level
CMOS compatible
3.3 V
5V
MIN
NOM
MAX
3
3.3
3.6
3
3.3
3.6
4.75
5
5.25
3.3 V
0
5V
0
3.3 V
0
5V
0
3.3 V
5V
3.3 V
5V
UNIT
V
V
VCCP
VCCP
V
VCCP
VCCP
V
0.5 VCCP
V
2
0.3 VCCP
0.8
V
§ Applies to external output buffers
¶ Applies to external input and bidirectional buffers without hysteresis
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PCI2030
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XCPS012 – DECEMBER 1997
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High le el output
o tp t voltage
oltage
High-level
VOL
Low level output voltage
Low-level
IIH
IIL
SIDE
TEST CONDITIONS
OPERATION
IOH = –0.5 mA
5V
IOL = 1.5 mA
3.3 V
0.1 VCC
5V
Input pins
VI = VCC†
3.6 V
10
5.25 V
20
I/O pins‡
VI = VCC†
3.6 V
20
Input pins
VI = GND
VI = GND
I/O pins‡
UNIT
V
2.4
IOL = 6 mA
High level input current
High-level
Low level input current
Low-level
MAX
0.9 VCC
3.3 V
IOH = –2 mA
MIN
0.55
5.25 V
25
3.6 V to 5.25 V
–1
3.6 V to 5.25 V
–20
±20
IOZ
High-impedance output current
VO = VCCP or GND
† For PCI pins, VCC = VCCP.
‡ For I/O pins, the input leakage current includes the off-state output current IOZ.
V
µA
µA
A
µA
PCI clock/reset timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Figure 1, Figure 2, and Figure 3)
ALTERNATE
SYMBOL
MIN
MAX
∞
UNIT
tc
Cycle time, PCLK
tcyc
30
twH
Pulse duration, PCLK high
thigh
11
ns
twL
Pulse duration, PCLK low
tlow
11
ns
∆v/∆t
Slew rate, PCLK
tr, tf
1
tw
Pulse duration, RSTIN
trst
1
4
ns
V/ns
ms
tsu
Setup time, PCLK active at end of RSTIN (see Note 3)
trst-clk
100
ms
NOTE 3: The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary PCI
close.
PCI timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4 and Figure 1 and Figure 4)
ALTERNATE
SYMBOL
tpd
d
Propagation delay time
MIN
PCLK to shared signal
valid delay time
tval
PCLK to shared signal
invalid delay time
tinv
2
2
Enable time,
high-impedance-to-active delay time from PCLK
ton
tdis
Disable time,
active-to-high-impedance delay time from PCLK
toff
Setup time before PCLK valid
UNIT
11
tsu, See Note 6
th, See Note 6
Hold time after PCLK high
MAX
pF See Note 5
CL = 50 pF,
ten
tsu
th
TEST CONDITIONS
ns
ns
28
ns
7
ns
0
ns
NOTES: 4. This data sheet uses the following conventions to describe time (t) intervals. The format is: tA, where subscript A indicates the type
of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time,
and th = hold time.
5. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
6. The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary
PCI close.
10
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PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT PARAMETERS
TIMING
PARAMETER
tPZH
ten
tPZL
tPHZ
tdis
tPLZ
tpd
CLOAD†
(pF)
IOL
(mA)
IOH
(mA)
VLOAD
(V)
50
8
–8
0
3
50
8
–8
1.5
50
8
–8
‡
IOL
Test
Point
From Output
Under Test
VLOAD
CLOAD
† CLOAD includes the typical load-circuit distributed capacitance.
IOH
‡ VLOAD – VOL = 50 Ω, where V
OL = 0.6 V, IOL = 8 mA
IOL
LOAD CIRCUIT
VCC
Timing
Input
(see Note A)
50% VCC
0V
tsu
Data
Input
High-Level
Input
90% VCC
10% VCC
th
50% VCC
50% VCC
Low-Level
Input
0V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT RISE AND FALL TIMES
50% VCC
tPLZ
tpd
50% VCC
tpd
50% VCC
VOH
50% VCC
VOL
tpd
VOH
50% VCC
VOL
Waveform 1
(see Note B)
50% VCC
tPHZ
tPZH
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
50% VCC
0V
tPZL
0V
In-Phase
Output
VCC
50% VCC
0V
VCC
Output
Control
(low-level
enabling)
50% VCC
tpd
Out-of-Phase
Output
50% VCC
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
VCC
50% VCC
0V
tw
VCC
tr
Input
(see Note A)
50% VCC
50% VCC
VCC
≈ 50% VCC
VOL + 0.3 V
VOL
VOH
VOH – 0.3 V
≈ 50% VCC
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For tPLZ and tPHZ, VOL and VOH are measured values.
Figure 1. Load Circuit and Voltage Waveforms
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PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
PCI BUS PARAMETER MEASUREMENT INFORMATION
twH
twL
2V
2 V MIN Peak to Peak
0.8 V
tf
tr
tc
Figure 2. PCLK Timing Waveform
PCLK
tw
RSTIN
tsu
Figure 3. RSTIN Timing Waveforms
PCLK
1.5 V
tpd
PCI Output
tpd
Valid
1.5 V
ton
toff
PCI Input
Valid
tsu
th
Figure 4. Shared-Signals Timing Waveforms
12
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XCPS012 – DECEMBER 1997
MECHANICAL DATA
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
88
133
0,27
0,17
0,08 M
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
SQ
25,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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