Data Sheet OXU121HP USB On-The-Go Full-Speed Host and High-Speed Peripheral Controller Features DS-0040 Aug 06 Single‐chip USB OTG full‐speed host and high‐speed peripheral controller Replaces two‐chip system Reduces system cost and board space Minimizes system design complexity and power consumption Simultaneous host and peripheral operation Compatible with the Universal Serial Bus Specification, Revision 2.0 and the On‐The‐Go Supplement to the USB Specification 2.0, Revision 1.0 Single 3.3 V power supply, flexible I/O voltage of 1.65 V to 3.6 V (LVCMOS/TTL) to interface to a wide range of MCUs Low power operation, suitable for mobile applications 30 mA (max) for host operation 75 mA (max) for peripheral operation Power saving mode for the host controller and suspend mode for peripheral controller Integrated on‐chip charge pump, supports up to 100 mA of current, enables support for broad range of USB devices Small package and footprint saves board space 7×7 mm BGA, 84‐ball, RoHS compliant 12×12 mm LQFP, 100‐pin, RoHS compliant 16‐bit memory mapped interface can gluelessly interface to most popular microprocessors and DSPs Fast microprocessor access cycle and double/multi‐buffering support for all four types of USB transfers Two DMA (slave) channels for the high‐speed peripheral controller, lowering CPU utilization Integrated PLL supports external crystal or crystal oscillators of 12 MHz and 30 MHz, for system flexibility 16 Kbytes of on‐chip SRAM, optimized buffer size for performance/cost External--Free Release 1 OXU121HP Data Sheet Device Overview Oxford Semiconductor, Inc. Allows up to 8 bi‐directional endpoints and transfers for support of multi‐function systems Configurable hardware Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Transaction scheduling and transfer level protocol implemented in hardware (including data toggle, retry and bandwidth management) for high performance Operating temperature range: ‐40 to 85 degrees C The Oxford Semiconductor OXU121HP (formerly TD1120) is a single‐ chip USB On‐The‐Go (OTG) controller that incorporates a full‐speed host and a high‐speed peripheral controller. It enables an embedded system to operate as a USB host and a peripheral simultaneously, thereby dramatically expanding the degree of interconnectivity and extending the applicability of USB into many new areas, especially in mobile communication, consumer electronics, and printer applications. The combination of the OXU121HP high‐speed peripheral and full‐speed host controller enables users to perform high‐speed USB data transfer for peripheral connectivity when connected to a host device, and operate at full speed in host mode operation to maximize system battery life in a mobile environment. The OXU121HP is ideal for mobile applications. It enables high‐speed PC synchronization to reduce data file transfer time when operating in USB peripheral mode. In host mode, it enables the system to connect to a wide range of USB devices such as flash drives, keyboards, mice, and digital still cameras (DSC). These mobile applications include smart phones, PDAs, MP3 players, portable media players, digital photo albums, and GPS devices. The OXU121HP is well suited for PictBridge printers. It enables high‐ speed data transfer between PC and printer. While utilizing the host port, it adds PictBridge printing capability to the printer to support direct photo printing from a DSC. The OXU121HP replaces existing two‐ chip solutions by combining discrete host and peripheral controllers into a single chip, thus minimizing system cost, board space, design complexity, and power consumption. The OXU121HP allows for simultaneous host and peripheral operation. The ports can be configured in one of two modes: 1 OTG + 1 Host: one OTG port and one full‐speed host port 1 Peripheral + 2 Host: one high‐speed peripheral port and two full‐speed host ports Software solutions for the OXU121HP include USB device drivers and the Oxford Semiconductor USBLinkTM product suite. The USBLink host, 2 External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. OXU121HP Data Sheet peripheral, and OTG stacks have been ported to a wide variety of real time operating systems including VxWorks®, ThreadX®, and Nucleus®. In addition, Oxford Semiconductor also makes available low‐level controller drivers for other native USB stacks such as those included with Windows® CE and Linux® 2.6.x. Figure 1 shows the OXU121HP architectural diagram. Figure 1 OXU121HP Architectural Diagram OSC1 OSC2 Clock/ Osc Pads and Clk Div ENVREG Voltage Regulator ACK[1:0] REQ[1:0] DMA Interface VREGOUT VBus Control Circuit and Vbus Charge Pump VBUS /EXVBO /PO /OC HNP/SRP Logic ID System Configuration & Control Registers /RESET USB Peripheral Controller Registers /CS USB Peripheral Controller /WR /RD INT µP Interface P_DM P_DP OTG XCVR Memory Blocks A[12:1] DM1 D[15:0] TEST DP1 Test Control Development Support USB Host Controller Registers USB Host Control Logic Host SIE & Root Hub USB Xcvr DM2 DP2 The OXU121HP product suite includes the USB controller as well as the protocol stacks and the driver software that enable a wide variety of USB applications. This unique ability to deliver a total hardware and software solution sets Oxford Semiconductor apart from other semiconductor companies and benefits customers by: Shortening time to market Reducing risk Offering a single source for hardware and software, thereby reducing the number of suppliers the customer has to deal with Oxford Semiconductor is a Microsoft® Windows® Embedded Partner and has developed host and peripheral controller drivers for Windows CE 5.0. Similar software support is also available for Linux® 2.6.x. DS-0040 Aug 06 External--Free Release 3 OXU121HP Data Sheet Oxford Semiconductor, Inc. For customers using a real time operating system (RTOS) such as VxWorks®, ThreadX®, Nucleus®, OSE, LynxOS® and AMXTM among others, Oxford Semiconductor offers its USBLink host, peripheral and On‐The‐Go software solutions. The USBLink Product Suite is a modularized approach to providing USB connectivity for a wide variety of embedded products. Due to its flexible architecture and broad based support for USB host, peripheral and OTG applications, Oxford Semiconductor can tailor the USBLink software deliverables to meet each customer’s USB requirements. The USBLink solutions are configurable and can support systems with: Big or little endian processors DMA or non‐DMA USB controllers A wide variety of USB controllers, including the OXU121HP A broad range of operating systems Oxford Semiconductor has over eight years of experience developing embedded USB technology. Its USBLink software has been ported to twenty different operating systems and a wide variety of embedded architectures. USBLink is shipping in many millions of units. Sample Applications 4 Portable media players MP3 players Car audio & navigation Printers Smart mobile phones Digital televisions Home media centers Digital video cameras Digital still cameras External storage products Set‐Top Boxes (STB) Personal Video Recorders (PVR) Personal Digital Assistants (PDA) DVD recorders External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. Electrical Characteristics OXU121HP Data Sheet Tables 3 to 11 detail the required operating conditions for the device and the DC and AC electrical characteristics. Table 1 Absolute Maximum Device Ratings Symbol Parameter Condition Min Max Unit VDD3.3 3.3 V power supply -0.3 4.0 V VDD1.8 1.8 V power supply -0.3 2.16 V VDDW 1.8 V to 3.3 V power supply -0.3 4.0 V VI DC input voltage -0.3 4.0 V TS Storage temperature -40 +150 °C Note: 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the normal operating conditions speci‐ fied in the following section. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2 Recommended Operating Conditions Symbol Parameter Condition Min Max Unit VDD3.3 3.3 V power supply 2.97 3.63 V VDD1.8 1.8 V power supply 1.62 1.98 V VDDW 1.8 - 3.3 V wide-range I/O power supply 1.62 3.63 V VI3.3 DC input voltage of 3.3 V pins 0 3.6 V VIW DC input voltage of wide-range pins 0 1.1*VDDW V TO Operating temperature -40 +85 °C DS-0040 Aug 06 External--Free Release 5 OXU121HP Data Sheet Oxford Semiconductor, Inc. Table 3 DC Characteristics, Full-Speed USB I/O Signals: DP1, DP2, DM1, DM2 Symbol Parameter Condition Min Max Unit VDI Diff. input sensitivity VCM Diff. comm. mode range 0.8 2.5 V VOL Static output low 0.0 0.3 V VOH Static output high 2.8 3.6 V VCRS Output signal crossover 1.3 2.0 V CIN Input capacitance 20 pF Max Unit |VI(DPN) -- VI(DMN)| (where N = 1 or 2) 0.2 V Table 4 DC Characteristics, High-Speed USB I/O Signals: DPP and DMP Only Symbol 6 Parameter VHSDIFF High-speed differential input sensitivity VHSCM High-speed data signaling common mode range VHSSQ High-speed squelch detection threshold Condition |VI(DPP) -- VI(DMP)| Min 300 -50 Squelch detected No squelch detected mV 500 mV 100 mV 150 mV VHSIO High-speed idle output voltage (differential) -10 10 mV VHSOL High-speed low-level output voltage (differential) -10 10 mV VHSOH High-speed high-level output voltage (differential) -360 400 mV VCHIRPK Chirp-K output voltage (differential) -900 -500 mV External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. OXU121HP Data Sheet Table 5 DC Characteristics, Logic Signals Symbol Parameter VOL Low-level output voltage VOH High-level output voltage Low-level input voltage VIL VIH High-level input voltage Condition Min Max Unit 0.4 V VDDW = 3.3 V 2.4 V VDDW = 1.8 V 0.75*VDDW V VDDW = 3.3 V 0.8 V VDDW = 1.8 V 0.3*VDDW V VDDW = 3.3 V 2.0 V VDDW = 1.8 V 0.7*VDDW V CIN Input capacitance 2.2 (typical) pF COUT Output capacitance 2.2 (typical) pF CBI Bi-directional capacitance 2.2 (typical) pF IIN Input leakage current Note: No pull up or pull down -10 10 µA The capacitances listed above do not include pad capacitance and package capacitance. One can estimate pin capacitance by adding pad capacitance of about 0.5 pF; and the package capacitance, which is about 0.86 pF max for QFP and 0.42 pF max for BGA. Table 6 DC Characteristics, ID Resistance Symbol Parameter Condition RB-PLUG-ID Resistance to ground on mini-B plug RA-PLUG-ID Resistance to ground on mini-A plug Min Max Unit Ω 100 K 10 Ω Max Unit Table 7 DC Characteristics, Regulator Symbol Parameter Condition RVout Output voltage Driving current <= 100 mA RIdrive Driving current VDD3.3A = 3.3 V Output voltage = 1.8 V Rtst Start-up time when enabled VDD3.3A = 3.3 V RVout = 1.62 V (90%) Note: DS-0040 Aug 06 Min 1.8 (typical) 150 25 (typical) V mA µs The VDD3.3A pin that corresponds to the regulator supply is QFP pin 81 and BGA pin B9. External--Free Release 7 OXU121HP Data Sheet Oxford Semiconductor, Inc. Table 8 DC Characteristics, Charge Pump Symbol Parameter Condition CVout Output voltage Driving current <= 100 mA VDD1.8 Driving current VCPSUPPLY = 3.3 V Output voltage = 5 V VDDW Start-up time when enabled VCPSUPPLY = 3.3 V RVout = 4.5 V (90%) Min Max Unit 4.75 5.07 V 100 mA 400 (typical) µs The charge pump supply VCPSUPPLY supplies the external components of the charge pump circuit. Note: Table 9 AC Characteristics, High-Speed DPP and DMP Driver Characteristics Symbol Parameter Condition Min Max Unit tHSR High-speed differential rise time 500 ps tHSF High-speed differential fall time 500 ps RDRV Driver output impedance Equivalent resistance used as internal chip 40.5 49.5 Ω Min Max Unit Table 10 AC Characteristics, Full-Speed DP1, DP2, DM1, DM2 Driver Characteristics Symbol Parameter Condition tFR Rise time CL = 50 pF 4 20 ns tFF Fall time CL = 50 pF 4 20 ns tFRFM TR/TF matching 90 110 % ZDRV Driver output resistance 3 9 Ω Min Max Unit Steady state drive with external 33 Ω series resistor Table 11 AC Characteristics, Low-Speed DP1, DP2, DM1, DM2 Driver Characteristics Symbol 8 Parameter Condition tLR Rise time CL = 200 - 600 pF 75 300 ns tLF Fall time CL = 200 - 600 pF 75 300 ns tFRFM TR/TF matching 80 125 % External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. Power Consumption OXU121HP Data Sheet Table 12 gives typical power consumption figures for the OXU121HP. Table 12 OXU121HP Power Consumption Condition Min Max Unit Host operational current ENVREG = 1 30 mA Peripheral operational current High-speed, ENVREG = 1 75 mA Full-speed, ENVREG = 1 50 mA Host suspend state current ENVREG = 1 150 (typical) µA Peripheral suspend state current ENVREG = 1 400 (typical) µA Power save state current ENVREG = 1 150 (typical) µA The above measurements are at typical process corner and room temperature and do not account for process and temperature variations. Peripheral operational current is measured with 5 m cable with maximum switching and BULK OUT transfer at 400 Mbps with 92.6% bus utilization during one microframe. The actual average current in customer applications will be lower. DS-0040 Aug 06 External--Free Release 9 OXU121HP Data Sheet Oxford Semiconductor, Inc. Pin Layout The OXU121HP is supplied as a 100‐pin LQFP package and as a 84‐ball BGA package. Figure 2 shows the chip layout of the 100‐pin LQFP package. 67 66 NC VSS V DD1.8 DP1 /OC VDD 3.3 61 60 59 58 57 56 55 54 53 52 51 DM1 62 VDD 1.8 63 /EXVBO 65 64 VBP ID 68 /PO PD_PMOS 69 CLKCFG VSSA 70 XMODE VDD 3.3A 72 71 VDD 1.8 EXT 73 VSS VBUS 74 VOUT VSSA VDD 3.3A 75 DP2 76 50 OSC 1 DM2 77 49 OSC 2 VDD3.3 78 48 VDD3.3A ENVREG 79 47 VSSA VREGOUT 80 46 RREF VDD3.3A 81 45 DMP VSSA 82 44 DPP VSS 83 43 VDD3.3A V DD1.8 84 42 VSSA VDDW 85 41 VSS /RESET 86 40 V DD1.8 . TEST 87 39 /CS GPIO 88 38 NC DRQ 0 89 37 ATEST13 36 A12 OXU121HP-LQBG ACK 0 90 RSVD 0 91 35 A11 92 34 A10 ACK 1 93 33 A9 RSVD 1 94 32 A8 VDDW 95 31 V DDW D0 96 30 A7 D1 97 29 A6 D2 98 28 A5 99 27 VSS 26 VDDW External--Free Release 20 21 22 23 24 25 A4 19 A3 18 A2 17 A1 16 /RD 15 /WR D8 13 14 INT V DDW 11 12 V DD1.8 V DD1.8 10 D 15 D7 9 V DDW 8 D 14 7 D 13 6 D 12 5 D 11 4 VSS 3 D9 2 D 10 1 D6 100 D5 V DD1.8 . D4 D3 VSS DRQ 1 10 VSS Figure 2 OXU121HP 100-Pin LQFP Package (Top View) DS-0040 Aug 06 Oxford Semiconductor, Inc. OXU121HP Data Sheet Table 13 lists the LQFP pin allocations. Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 1 of 3) Pin No. Bits Name Type(1) Description Processor Interface (37 pins) 2, 3, 4, 5, 8, 9, 10, 11, 13, 14, 15, 16, 96, 97, 98, 99 16 MSBCT D0 - D15 16-bit data bus. Pull-up/pull-down can be controlled through register 0x034, bits 2:1. Default is none 22, 23, 24, 25, 28, 29, 30 32, 33, 34, 35, 36 12 MSID A1 - A12 Address bus for direct address space of 8 Kbytes. Pull-up can be enabled through register 0x034, bits 9:8. Default is pull-down 20 1 MSIU /WR Write strobe. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up 21 1 MSIU /RD Read strobe. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up 39 1 MSIU /CS Chip select. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up 19 1 MOCT /INT Interrupt to the MCU.This pin can be software configured as a driven output or open drain. Open drain is the default 86 1 MSIU /RESET Hardware reset. Pull-up is always enabled 89, 92 2 MOCT DRQ1, DRQ0 DMA request outputs to support two channels 90, 93 2 MSI ACK1, ACK0 DMA acknowledge. Pull-up/pull-down can be controlled through register 0x03A, bits 1:0. Default is none BC GPIO General purpose I/O General Purpose I/O (1 pin) 88 1 Power & Ground (34 pins) 1, 12, 27, 41, 51, 65, 75, 83 8 VSS Digital/wide-range ground 42, 47, 69, 74, 82 5 VSSA Analog ground 6, 18, 40, 53, 57, 66, 84, 100 8 VDD1.8 1.8 V core power. VREGOUT may be used for the supplies 43, 48, 70, 73, 81 5 VDD3.3A Analog +3.3 V power 56, 78 2 VDD3.3 Digital +3.3 V power 7, 17, 26, 31, 85, 95 6 VDDW Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V, VREGOUT may be used for these supplies USB Interface (13 pins) 76, 77 2 B DP2, DM2 Data lines for host port 2, a dedicated USB host port. If not used, these pins should be left floating 54, 55 2 B DP1, DM1 Data lines for host port 1, which can serve as a USB host or an OTG port in combination with the peripheral port. If not used, these pins should be left floating DS-0040 Aug 06 External--Free Release 11 OXU121HP Data Sheet Oxford Semiconductor, Inc. Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 2 of 3) Pin No. Bits Name Type(1) Description 44, 45 2 B DPP, DMP Data lines for USB peripheral port, which can serve as an OTG port in combination with host port 1. If not used, these pins should be left floating 46 1 B RREF Connect external reference resistor (12 KΩ +/- 1%) to VSSA 72 1 5I VBUS VBUS input used by the voltage comparators of the OTG port for connection. This pin should be left floating in a host-only application 60 1 OC VBP VBUS pulsing control. This pin is used only when the OTG port is operating as a B-device 59 1 O /EXVBO Turn on/off the external VBUS (5 V) for OTG operation (1:VBUS off, 0: VBUS on) when using the external VBUS source 58 1 IU /OC Over current condition indicator for powered host ports. Pull-up is always enabled 62 1 IU ID Connected to the ID pin of the mini-AB connector for OTG applications. With the help of an internal pull-up resistor, this pin determines the chip’s responsibility in an OTG application (0: A-device, 1:B-device). Pull-up can be disabled through register 0x038, bits 7:6. Default is pull-up 61 1 O /PO Turn on/off gang power for all host ports Clock Interface (3 pins) 50 1 I OSC1 Input. A 12 MHz or 30 MHz passive crystal should be connected across the two pins (OSC1 and OSC2). Optionally, a 12 MHz or 30 MHz oscillator can be connected to OSC1 while keeping OSC2 unconnected 49 1 O OSC2 Output 63 1 I CLKCFG Indicates whether a 12 MHz or a 30 MHz crystal/ oscillator is being used. 0 = 12 MHz crystal or 12 MHz 3.3 V oscillator input on OSC1 1 = 30 MHz crystal or 30 MHz 3.3 V oscillator input on OSC1 Internal VBUS Charge Pump (3 pins) 68 1 O PD_PMOS Internal charge pump output for P-MOSFET (optional switch on the VOUT) 71 1 O EXT Internal charge pump output for N-MOSFET 67 1 I VOUT Internal charge pump output voltage feedback pin ENVREG Enables the internal voltage regulator if asserted. If not used, this pin should be tied to VSS Internal Voltage Regulator (2 pins) 79 12 1 I External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. OXU121HP Data Sheet Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 3 of 3) Pin 80 No. Bits Name Type(1) Description 1 O VREGOUT Internal voltage regulator output of 1.8 V. If enabled, this output should be connected to the VDD1.8 (and VDDW if wide-range IO is at 1.8 V) supplies of the chip. If the regulator is disabled, then this pin should be treated as another VDD1.8 supply input to the chip 87 1 ID TEST Factory test mode. This pin should be grounded or left floating (has an internal pull-down) for normal operation. Pull-down is always enabled 37 1 ID ATEST13 Additional address pin for debug use. Should be grounded or left floating (has an internal pull down) for normal use. Pull-down is always enabled 64 1 I XMODE This pin must be grounded for normal operation Test (3 pins) Miscellaneous (4 pins) 91, 94 2 - RSVD0, RSVD1 Reserved 38, 52 2 - NC No connection. This pin should be left floating Note to Table 13: L—Logic Level M(2) S Multi-voltage: 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS 1 W—Tolerance 5 Schmitt Trigger 2 3 DS-0040 Aug 06 Type key: format is [(L)(W_)X(Y)(_Z(A))] where the following conventions apply: X—Type Y—Pull 5V I Input U Pull up 3.3 V O Output D Pull down B Bidirectional Z—Drive C(3) T—Tristate T Tristate Normal None Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level. Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14, mA, or 16 mA via the I/O Configura‐ tion Register (0x034). External--Free Release 13 OXU121HP Data Sheet Oxford Semiconductor, Inc. Figure 3 shows the chip layout of the 84‐ball BGA package. Figure 3 OXU121HP 84-Ball BGA Package (Top View) 14 10 DM2 VSSA 9 DP2 VDD3.3A 8 VREGOUT 7 V SSA EXT VOUT XMODE /PO /OC DP1 OSC 1 VDD3.3A VDD3.3A PD_PMOS CLKCFG VBP DM 1 OSC 2 V DD3.3A ENVREG VSS VBUS VSSA ID /EXVBO V DD3.3 R REF V SSA TEST GPIO DRQ 0 V DD3.3A DPP DM P 6 DRQ 1 /RESET VDD3.3 VSS /CS V SSA 5 ACK0 RSVD0 V DD1.8 V DDW A 12 ATEST13 4 ACK 1 RSVD1 D1 A10 A9 A 11 3 D0 D2 VSS D11 VDD1.8 VDDW /WR VDD1.8 A7 A8 2 D3 D6 D8 D10 D 13 D14 INT A2 A3 A5 1 D4 D5 D7 D9 D 12 D15 /RD A1 A4 A6 A B C D E F G H J K OXU121HP-PBBG External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. OXU121HP Data Sheet Table 14 lists the BGA pin allocations. Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 1 of 3) Pin No. Bits Name Type(1) Description Processor Interface (37 pins) A3, C4, B3, A2, A1, B1, B2, C1, C2, D1, D2, D3, E1, E2, F2, F1 16 MSBCT D0 - D15 16-bit data bus. Pull-up/pull-down can be controlled through register 0x034, bits 2:1. Default is none H1, H2, J2, J1, K2, K1, J3, K3, J4, H4, K4, J5 12 MSID A1 - A12 Address bus for direct address space of 8 Kbytes. Pull-up can be enabled through register 0x034, bits 9:8. Default is pull-down G3 1 MSIU /WR Write strobe. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up G1 1 MSIU /RD Read strobe. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up J6 1 MSIU /CS Chip select. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up G2 1 MOCT /INT Interrupt to the MCU.This pin can be software configured as a driven output or open drain. Open drain is the default B6 1 MSIU /RESET Hardware reset. Pull-up is always enabled C7, A6 2 MOCT DRQ0, DRQ1 DMA request outputs to support two channels A5, A4 2 MSI ACK1, ACK0 DMA acknowledge. Pull-up/pull-down can be controlled through register 0x03A, bits 1:0. Default is none B GPIO General purpose I/O General Purpose I/O (1 pin) B7 1 Power & Ground (20 pins) C3, C8, H6 3 VSS Digital ground B10, C10, E8,K6, K8 5 VSSA Analog ground C5, E3, H3 3 VDD1.8 1.8 V core power. VREGOUT may be used for these supplies B9, C9, D9, H7, K9 5 VDD3.3A Analog +3.3 V power C6, H8 2 VDD3.3 Digital +3.3 V power F3, H5 2 VDDW Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V, VREGOUT may be used for these supplies USB Interface (13 pins) A9, A10 2 B DP2, DM2 Data lines for host port 2, a dedicated USB host port. If not used, these pins should be left floating J10, H9 2 B DP1, DM1 Data lines for host port 1, which can serve as a USB host or an OTG port in combination with the peripheral port. If not used, these pins should be left floating J7, K7 2 B DPP, DMP Data lines for USB peripheral port, which can serve as an OTG port in combination with host port 1. If not used, these pins should be left floating DS-0040 Aug 06 External--Free Release 15 OXU121HP Data Sheet Oxford Semiconductor, Inc. Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 2 of 3) Pin No. Bits Name Type(1) Description D8 1 5I VBUS VBUS input used by the voltage comparators of the OTG port for connection. This pin should be left floating in a host only application G9 1 OC VBP VBUS pulsing control. This pin is used only when the OTG port is operating as a B-device G8 1 P5O /EXVBO Turn on/off the external VBUS (5 V) for OTG operation (1:VBUS off, 0:VBUS on) when using the external charge pump H10 1 IU /OC Over current condition indicator for powered host ports. Pull-up is always enabled J8 1 B RREF Connect external reference resistor (12 KΩ +/- 1%) to VSSA F8 1 IU ID Connected to the ID pin of the mini-AB connector for OTG applications. With the help of an internal pull-up resistor, this pin determines the chip’s responsibility in an OTG application (0: A-device, 1:B-device). Pull-up can be disabled through register 0x038, bits 7:6. Default is pullup G10 1 P5O /PO Turn on/off gang power for all host ports K10 1 I OSC1 Input. A 12 MHz or 30 MHz passive crystal should be connected across the two pins (OSC1 and OSC2). Optionally, a 12 MHz or 30 MHz oscillator can be connected to OSC1 while keeping OSC2 unconnected J9 1 O OSC2 Output F9 1 I CLKCFG Indicates whether a 12 MHz or a 30 MHz crystal/oscillator is being used. 0 = 12 MHz crystal or 12 MHz 3.3 V oscillator input on OSC1 1 = 30 MHz crystal or 30 MHz 3.3 V oscillator input on OSC1 Clock Interface (3 pins) Internal VBUS Charge Pump (3 pins) E9 1 O PD_PMOS Internal charge pump output for P-MOSFET (optional switch on the VOUT) D10 1 O EXT Internal charge pump output for N-MOSFET E10 1 I VOUT Internal charge pump output voltage feedback pin Internal Voltage Regulator (2 pins) B8 1 I ENVREG Enables the internal voltage regulator if asserted. If not used, this pin should be tied to VSS A8 1 O VREGOUT Internal voltage regulator output of 1.8 V. If enabled, this output should be connected to the VDD1.8, (and VDDW if wide-range IO is at 1.8 V) supplies of the chip. If the regulator is disabled, then this pin should be treated as another VDD1.8 supply input to the chip 16 External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. OXU121HP Data Sheet Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 3 of 3) Pin No. Bits Name Type(1) Description Test (3 pins) A7 1 ID TEST Factory test mode. This pin should be grounded or left floating (has an internal pull-down) for normal operation. Pull-down is always enabled K5 1 ID ATEST13 Additional address pin for debug use. Should be grounded or left floating (has an internal pull down) for normal use. Pull-down is always enabled F10 1 I XMODE This pin must be grounded for normal operation 2 - RSVD0, RSVD1 Reserved Miscellaneous (2 pins) B5, B4 Note to Table 14: L—Logic Level M (2) S Multi-voltage: 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS 1 W—Tolerance 5 Schmitt Trigger 2 3 DS-0040 Aug 06 Type key: format is [(L)(W_)X(Y)(_Z(A))] where the following conventions apply: X—Type Y—Pull 5V I Input U Pull up 3.3 V O Output D Pull down B Bidirectional Z—Drive (3) C T—Tristate T Tristate Normal None Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level. Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14, mA, or 16 mA via the I/O Configura‐ tion Register (0x034). External--Free Release 17 OXU121HP Data Sheet Package Layout Oxford Semiconductor, Inc. Figure 4 shows the package layout for the 100‐pin LQFP package. Figure 4 100-Pin LQFP 18 External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. OXU121HP Data Sheet Figure 5 shows the layout for the 84‐ball TFBGA. Figure 5 84-Ball TFBGA Package 1 of 2 DS-0040 Aug 06 External--Free Release 19 OXU121HP Data Sheet Oxford Semiconductor, Inc. Figure 5 84-Ball TFBGA Package (continued) 2 of 2 20 External--Free Release DS-0040 Aug 06 Oxford Semiconductor, Inc. Ordering Information OXU121HP Data Sheet The following conventions are used to identify Oxford Semiconductor products. OXU121HP - LQBG Green (RoHS compliant) Revision Package Type: LQ 100-Pin LQFP Part Number OXU121HP - PBBG Green (RoHS compliant) Revision Package Type: PB 84-Ball TF-BGA Part Number Contacting Oxford Semiconductor Revision Information See the Oxford Semiconductor website (http://www.oxsemi.com) for further detail about Oxford Semiconductor devices, or email [email protected]. Table 15 documents the revisions of this guide. Table 15 Revision Information Revision August 06 DS-0040 Aug 06 Modification First publication External--Free Release 21 OXU121HP Data Sheet Oxford Semiconductor, Inc. USBLink is a trademark of Oxford Semiconductor, Inc. VxWorks is a registered trademark of Wind River Systems. ThreadX is a registered trademark of Express Logic, Inc. Nucleus is a registered trademark of Mentor Graphics Corporation. Symbian OS is a registered trademark of Symbian Ltd. Windows is a trademark of Microsoft, Inc., registered in the US and other countries. LynxOS is a registered trademark of LynuxWorks, Inc. AMX is a trademark of KADAK Products LTD. Linux is a registered trademark of Linus Torvalds. All other trademarks are the property of their respective owners. © Oxford Semiconductor, Inc. 2006 The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in this document. 22 External--Free Release DS-0040 Aug 06