19-6166; Rev 0; 1/12 EVALUATION KIT AVAILABLE MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface General Description The MAX5316 is a high-accuracy, 16-bit, serial SPI input, buffered voltage output digital-to-analog converter (DAC) in a 4mm x 5mm, 24-lead TQFN package. The device features Q1 LSB INL (max) accuracy and a Q0.25 LSB DNL (typ) accuracy over the temperature range of -40NC to +105NC. The DAC voltage output is buffered with a fast settling time of 3Fs and a low offset and gain drift of Q0.6ppm/NC of FSR (typ). The force-sense output (OUT) maintains accuracy while driving loads with long lead lengths. A separate AVSS supply pin is provided to permit the output amplifier to go to 0V (GND) to maintain full linearity performance near ground. At power-up, the device resets its outputs to zero or midscale. The wide 2.7V to 5.5V supply voltage range and integrated low-drift, low-noise reference buffer make for ease of use. The MAX5316 features a 50MHz 3-wire SPI interface. For an I2C interface, use the MAX5317. The MAX5316 is available in a 24-lead TQFN-EP package and operates over the -40NC to +105NC temperature range. Benefits and Features SIdeal for ATE and High-Precision Instruments INL Accuracy Guaranteed with ±1 LSB (Max) Over Temperature SFast Settling Time (3µs) with 10kI || 100pF Load SSafe Power-Up-Reset to Zero or Midscale DAC Output (Pin-Selectable) Predetermined Output Device State in Power-Up and Reset in System Design SNegative Supply (AVSS) Option Allows Full INL and DNL Performance to 0V SSPI Interface Compatible with 1.7V to 5.5V Logic SHigh Integration Reduces Development Time and PCB Area Buffered Voltage Output Directly Drives 2kI Load Rail-to-Rail Integrated Reference Buffer No External Amplifiers Required SSmall 4mm x 5mm, 24-Pin TQFN Package Functional Diagram Applications Test and Measurement VDDIO REF Automatic Test Equipment 22 Gain and Offset Adjustment LDAC 3 Process Control and Servo Loops Medical Equipment 12 15 REFO MAX5316 7.8kI CS 7 Programmable Voltage and Current Sources Communication Systems AVDD1 19 BUFFER Data-Acquisition Systems Automatic Calibration AVDD2 16 SCLK 6 SPI DIN 5 DOUT 4 INPUT/ DAC REGISTER SPI INTERFACE 16-BIT DAC 7.8kI 7.8kI READY 24 BUSY 2 M/Z 1 TC/SB 8 13 OUT OUTPUT BUFFER RST 23 Ordering Information appears at end of data sheet. 14 RFB CONTROL LOGIC POWER-ON RESET 7.8kI SHUTDOWN PD 9 21 DGND 20 11 BYPASS AGND 17 18 10 AGND_S AGND_F AVSS QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of Texas Instrument Incorporated. For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX5316.related. ����������������������������������������������������������������� Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface ABSOLUTE MAXIMUM RATINGS AGND to DGND....................................................-0.3V to +0.3V AGND_F, AGND_S to AGND................................-0.3V to +0.3V AGND_F, AGND_S to DGND................................-0.3V to +0.3V AVDD_ to AGND......................................................-0.3V to +6V AVDD_ to REF..........................................................-0.3V to +6V AVSS to AGND.........................................................-2V to +0.3V VDDIO to DGND........................................................-0.3V to +6V BYPASS to DGND........................................-0.3V to the lower of (VAVDD_ or VDDIO + 0.3V) and +6V OUT, REFO, RFB to AGND..........................-0.3V to the lower of (VAVDD_ + 0.3V) and +6V REF to AGND...............................................-0.3V to the lower of VAVDD and +6V SCLK, DIN, CS, BUSY, LDAC, READY, M/Z, TC/SB, RST, PD, DOUT to DGND........-0.3V to the lower of (VDDIO + 0.3V) and +6V Continuous Power Dissipation (TA = +70NC) TQFN (derate 28.6mW/NC above +70NC)................2285.7mW Operating Temperature Range......................... -40NC to +105NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Case Thermal Resistance (qJA)...............1.8°C/W Junction-to-Ambient Thermal Resistance (qJA)...........35°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VAVDD_ = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N Integral Nonlinearity (Note 3) INL Differential Nonlinearity (Note 3) DNL Zero Code Error OE Zero Code Error Drift Gain Error DIN = 0x0640 to 0xFFFF (binary mode), DIN = 0x8280 to 0x7FFF (two’s complement mode), VAVSS = 0V DIN = 0, TA = +25NC TCGE TA = +25NC Bits -1 Q0.25 -1 -19 DIN = 0, TA = -40NC to +105NC DIN = 0 GE Gain Error Temperature Coefficient 16 DIN = 0x0000 to 0xFFFF (binary mode), DIN = 0x8000 to 0x7FFF (two’s complement mode) +1 LSB Q0.25 +1 LSB Q1 +19 Q6 -2.5 Q0.4 +2.5 -4 Q0.25 +4 TA = -40NC to +105NC Q3 -2.75 Q0.6 +2.75 LSB ppm/NC LSB ppm/NC of FSR ����������������������������������������������������������������� Maxim Integrated Products 2 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD_ = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS Output Voltage Range VOUT-RESET Output Resistance (Power-Down Mode) Output Current IOUT Load Capacitance to GND CL Load Resistance to GND RL Short-Circuit Current ISC Short-Circuit Duration DC Power-Supply Rejection TSC DC PSRR UNITS V 75 M/Z = VDDIO 2.048 V M/Z = DGND 10 mV M/Z = VDDIO 2.048 V M/Z = DGND -40 mV M/Z = VDDIO 2.037 V M/Z = DGND 10 mV M/Z = VDDIO 2.037 V Closed-loop connection (RFB connected to OUT) 4 mI PD = VDDIO 2 kI RST = pulse low, VAVSS = 0V RST = DGND, VAVSS = 0V ROUT MAX VAVDD - 0.1 M/Z = DGND RST = DGND DC Output Impedance (Normal Mode) TYP 0 RST = pulse low Reset Voltage Output MIN Source/sink within 100mV of the supply rails Q4 Source/sink within 800mV of the supply rails Q25 FV mA 200 For specified performance 2 OUT shorted to AGND or AVDD Q60 REFO shorted to AGND or AVDD Q65 BYPASS shorted to AGND or AVDD Q48 Short to AGND or AVDD pF kI mA Indefinite s VOUT at full scale, VAVDD = 4.5V to 5.5V -1 Q0.05 +1 VAVSS = -1.5V to -0.5V -1 Q0.003 +1 LSB/V STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION VAVDD - 0.1 Reference High Input Range VREF Reference Input Capacitance CREF 10 pF Reference Input Resistance RREF 10 MI IB Q0.05 FA Reference Input Current 2.4 V STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION Reference High Output Range Reference High Output Load Regulation Reference Output Capacitor VAVDD - 0.1 2.4 ppm/ mA 500 RESR < 5I 0.1 V 0.15 nF ����������������������������������������������������������������� Maxim Integrated Products 3 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD_ = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2.3 2.4 UNITS STATIC PERFORMANCE—VBYPASS OUT SECTION Output Voltage VBYPASS Load Capacitance to GND CL Required for stability, RESR = 0.1I (typ) 2.5 V 1 10 FF POWER-SUPPLY REQUIREMENTS Positive Analog Power-Supply Range VAVDD 4.5 5.5 V Digital Interface Power-Supply Range VDDIO 1.7 VAVDD V Negative Analog Power-Supply Range VAVSS -1.5 -1.25 0 V Positive Analog Power-Supply Current IAVDD No load, external reference, output at zero scale 5.5 7.5 mA Negative Analog Power-Supply Current IAVSS No load, external reference, output at zero scale Interface Power-Supply Current IVDDIO Digital inputs at VDDIO or DGND 1 10 FA Positive Analog Power-Supply Power-Down Current PD = VDDIO, power-down mode 20 50 FA Negative Analog Power-Supply Power-Down Current PD = VDDIO, power-down mode -1.75 -10 -1.0 mA -3 FA 4.9 V/Fs 3 Fs 1.9 Fs DYNAMIC PERFORMANCE Voltage Output Slew Rate SR From 10% to 90% full scale, positive and negative transitions Voltage Output Settling Time tS From falling edge of LDAC to within 0.003% FS, RL = 10kI, DIN = 1000h (6.25% FS) to F000h (93.75% FS) Busy Time tBUSY (Note 4) DAC Glitch Impulse Major code transition (1FFFh to 8000h), RL = 10kI, CL = 50pF 4 nVs Digital Feed Through CSB = VDDIO, fSCLK = 1kHz, all digital inputs from 0V to VDDIO 1 nVs Output Voltage-Noise Spectral Density At f = 1kHz to 10kHz, without reference noise, code = 8000h 26 nV/√Hz Output Voltage Noise At f = 0.1Hz to 10Hz, without reference noise, code = 8000h 1.55 FVP-P Wake-Up Time From power-down mode 75 Fs Power-Up Time From power-off 1 ms ����������������������������������������������������������������� Maxim Integrated Products 4 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface ELECTRICAL CHARACTERISTICS (VAVDD_ = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N Integral Nonlinearity (Note 3) INL Differential Nonlinearity (Note 3) DNL Zero Code Error OE Zero Code Error Drift (Note 2) Gain Error GE Gain Error Temperature Coefficient (Note 2) 16 DIN = 0x0000 to 0xFFFF (binary mode), DIN = 0x8000 to 0x7FFF (two’s complement mode) DIN = 0x0640 to 0xFFFF (binary mode), DIN = 0x8280 to 0x7FFF (two’s complement mode), VAVSS = 0V DIN = 0, TA = +25NC Reset Voltage Output Output Current IOUT Load Capacitance to GND CL Load Resistance to GND RL Short-Circuit Current Short-Circuit Duration DC Power-Supply Rejection ISC TSC DCPSRR LSB -1.0 Q0.10 +1.0 LSB -20 +1.5 +20 Q4 Q0.35 +3 TA = +25NC -4 Q0.65 +4 TA = -40NC to +105NC RST = pulse low RST = pulse low, VAVSS = 0V RST = DGND, VAVSS = 0V ROUT +1.0 -3 RST = DGND DC Output Impedance Q0.20 DIN = 0 LSB ppm/NC LSB Q3 Output Voltage Range RESET -1.0 DIN = 0, TA = -40NC to +105NC TCGE VOUT- Bits -3 +3 ppm/NC of FSR 0 VAVDD - 0.1 V M/Z = DGND 75 FV M/Z = VDDIO 1.25 V M/Z = DGND 10 mV M/Z = VDDIO 1.25 V M/Z = DGND -40 mV M/Z = VDDIO 1.25 V M/Z = DGND 10 mV M/Z = VDDIO 1.24 V 4 mI Closed-loop connection, RFB connected to OUT Source/sink within 100mV of the supply rails Q4 Source/sink within 800mV of the supply rails Q25 mA 200 For specified performance 2 kI OUT shorted to AGND or AVDD Q60 REFO shorted to AGND or AVDD Q65 BYPASS shorted to AGND or AVDD Q48 Short to AGND or AVDD pF mA Indefinite s VOUT at full scale, VAVDD = 2.7V to 3.3V -1 Q0.1 +1 VAVSS = -1.5V to -0.5V -1 Q0.01 +1 LSB/V ����������������������������������������������������������������� Maxim Integrated Products 5 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD_ = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VAVDD - 0.1 V STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION Reference High Input Range VREF Reference Input Capacitance CREF 10 pF Reference Input Resistance RREF 10 MI IB Q0.05 FA Reference Input Current 2.4 STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION Reference High Output Range VAVDD - 0.1 2.4 Reference High Output Load Regulation 500 Reference Output Capacitor V ppm/mA 0.1 0.15 nF 2.4 2.5 V 1 10 FF RESR < 5I STATIC PERFORMANCE—VBYPASS OUT SECTION Output Voltage VBYPASS Load Capacitance to GND CL 2.3 Required for stability, RESR = 0.1I (typ) POWER-SUPPLY REQUIREMENTS Positive Analog Power-Supply Range VAVDD 2.7 3.3 V Interface Power-Supply Range VDDIO 1.7 VAVDD V Negative Analog Power-Supply Range VAVSS -1.5 -1.25 0 V Positive Analog Power-Supply Current IAVDD No load, external reference, output at zero scale 4 6.5 mA Negative Analog Power-Supply Current IAVSS No load, external reference, output at zero scale Interface Power-Supply Current IVDDIO Digital inputs at VDDIO or DGND 1 10 FA Positive Analog Power-Supply Power-Down Current PD = VDDIO, power-down mode 20 50 FA Negative Analog Power-Supply Power-Down Current PD = VDDIO, power-down mode -1.5 -10 -0.8 mA -3 FA 4.9 V/Fs 3 Fs DYNAMIC PERFORMANCE Voltage Output Slew Rate SR From 10% to 90% full scale, positive and negative transitions Voltage Output Settling Time tS From falling edge of LDAC to within 0.003% FS, RL = 10kI, DIN = 1000h (6.25% FS) to F000h (93.75% FS) ����������������������������������������������������������������� Maxim Integrated Products 6 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD_ = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Busy Time SYMBOL tBUSY CONDITIONS MIN TYP MAX UNITS (Note 4) 1.9 Fs DAC Glitch Impulse Major code transition (7FFFh to 8000h), RL = 10kI, CL = 50pF 2.5 nVs Digital Feedthrough CSB = VDDIO, fSCLK = 1kHz, all digital inputs from 0V to VDDIO 1 nVs Output Voltage-Noise Spectral Density At f = 1kHZ to 10kHz, without reference noise, code = 8000h 26 nV/√Hz Output Voltage Noise At f = 0.1Hz to 10Hz, without reference noise, code = 8000h 1.55 FVP-P Wake-Up Time From power-down mode 75 Fs Power-Up Time From power-off 1 ms Note 2: All devices are 100% tested at TA = +25°C and TA = +105°C. Limits at TA = -40°C are guaranteed by design. Note 3: Linearity is tested from VREFO to AGND. Note 4: The total analog throughput time from DIN to VOUT is the sum of tS and tBUSY (4.9µs, typ). DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (VAVDD_ = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z, CREFO = 100pF, CL = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, LDAC) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 0.7 x VDDIO 0.3 x VDDIO VIHYST Input Leakage Current IIN Input Capacitance CIN V 200 Input = 0V of VDDIO 300 Q0.1 mV Q1 10 DIGITAL OUTPUT CHARACTERISTICS (DOUT, READY, BUSY) Output Low Voltage VOL ISOURCE = 5.0mA V FA pF 0.25 V Q1 FA VDDIO - 0.25 Output High Voltage VOH ISINK = 5.0mA, except for BUSY Output Three-State Leakage IOZ DOUT only Q0.1 Output Three-State Capacitance COZ DOUT only 15 pF Output Short-Circuit Current IOSS VDDIO = 5.5V Q150 mA ����������������������������������������������������������������� Maxim Integrated Products 7 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued) (VAVDD_ = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z, CREFO = 100pF, CL = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS Stand-alone, write mode Serial Clock Frequency fSCLK 50 Stand-alone read mode and daisychained read and write modes (Note 5) 12.5 MHz Stand-alone, write mode 20 SCLK Period tCP Stand-alone read mode and daisychained read and write modes 80 SCLK Pulse Width High tCH 40% duty cycle 8 ns SCLK Pulse Width Low tCL 40% duty cycle 8 ns CS Fall to SCLK Fall Setup Time tCSSO First SCLK falling edge Stand-alone, write mode 8 Stand-alone read mode and daisychained read and write modes 28 ns ns CS Fall to SCLK Fall Hold Time tCSH0 Inactive falling edge preceding first falling edge 0 ns SCLK Fall to CS Rise Hold Time tCSH1 24th falling edge 2 ns DIN to SCLK Fall Setup Time tDS 5 ns DIN to SCLK Fall Hold Time tDH 4.5 ns SCLK Rise to DOUT Settle Time tDOT CL = 20pF (Note 6) SCLK Rise to DOUT Hold Time tDOH CL = 0pF (Note 6) 2 SCLK Fall to DOUT Disable Time tDOZ 24th active edge deassertion 2 30 ns CS Fall to DOUT Enable tDOE Asynchronous assertion 2 30 ns CS Rise to DOUT Disable tCSDOZ Daisy-chained, aborted sequence tCRF 24th falling-edge assertion, CL = 20pF SCLK Fall to READY Hold tCRH 24th falling-edge assertion, CL = 0pF SCLK Fall to BUSY Fall tCBF BUSY assertion CS Rise to READY Rise tCSR CL = 20pF CS Rise to SCLK Fall tCSA 24th falling edge, aborted sequence CS Pulse Width High tCSPW SCLK Fall to CS Fall tCSF LDAC Fall to SCLK Fall Hold RST Pulse Width tRSTPW 35 20 30 2 ns ns ns 5 ns 35 ns 20 ns Stand alone 20 ns 24th falling edge 100 ns 20 ns 20 ns 20 ns tLDPW tLDH ns ns Stand-alone, aborted sequence SCLK Fall to READY Fall LDAC Pulse Width 32 Last active falling edge ����������������������������������������������������������������� Maxim Integrated Products 8 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued) (VAVDD_ = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z, CREFO = 100pF, CL = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, LDAC) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 0.8 x VDDIO 0.2 x VDDIO VIHYST Input Leakage Current IIN Input Capacitance CIN V 200 Input = 0V or VDDIO 300 Q0.1 V mV Q1 10 FA pF DIGITAL OUTPUT CHARACTERISTICS (DOUT, READY, BUSY) Output Low Voltage Output High Voltage VOL ISOURCE = 1.0mA 0.2 VDDIO - 0.2 V VOH ISINK = 1.0mA, except for BUSY V Output Three-State Leakage IOZ DOUT only Q0.1 Output Three-State Capacitance COZ DOUT only 15 pF Output Short-Circuit Current IOSS VDDIO = 2.7V Q150 mA Q1 FA TIMING CHARACTERISTICS Serial Clock Frequency fSCLK Stand-alone, write mode 50 Stand-alone read mode and daisy chained read and write modes (Note 5) 8 MHz Stand-alone, write mode 20 SCLK Period tCP Stand-alone read mode and daisychained read and write modes 125 SCLK Pulse Width High tCH 40% duty cycle 12 ns SCLK Pulse Width Low tCL 40% duty cycle 12 ns Stand-alone, read mode 12 Stand-alone read mode and daisy-chained read and write modes 36 ns CS Fall to SCLK Fall Setup Time tCSSO First SCLK falling edge CS Fall to SCLK Fall Hold Time tCSH0 Inactive falling edge preceding first falling edge 0 ns SCLK Fall to CS Rise Hold Time tCSH1 24th falling edge 4 ns ns DIN to SCLK Fall Setup Time tDS 8 ns DIN to SCLK Fall Hold Time tDH 8 ns ����������������������������������������������������������������� Maxim Integrated Products 9 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued) (VAVDD_ = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z, CREFO = 100pF, CL = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL SCLK Rise to DOUT Settle Time tDOT CL = 20pF (Note 6) SCLK Rise to DOUT Hold Time tDOH CL = 0pF (Note 6) 2 SCLK Fall to DOUT Disable Time tDOZ 24th active edge deassertion 2 40 ns CS Fall to DOUT Enable tDOE Asynchronous assertion 2 50 ns CS Rise to DOUT Disable tCSDOZ CONDITIONS SCLK Fall to READY Hold 24th falling edge assertion, CL = 0pF SCLK Fall to BUSY Fall tCBF BUSY assertion CS Rise to READY Rise tCSR CL = 20pF CS Rise to SCLK Fall tCSA 24th falling edge, aborted sequence CS Pulse Width High tCSPW SCLK Fall to CS Fall tCSF ns 60 2 ns ns ns 5 ns 60 ns 20 ns Stand alone 20 ns 24th falling edge 100 ns 20 ns 20 ns 20 ns tLDPW tLDH ns 70 24th falling edge assertion, CL = 20pF tRSTPW UNITS 60 130 tCRF RST Pulse Width MAX Daisy-chained, aborted sequence tCRH LDAC Fall to SCLK Fall Hold TYP Stand-alone, aborted sequence SCLK Fall to READY Fall LDAC Pulse Width MIN Last active falling edge Note 5: Daisy-chain speed is relaxed to accommodate (tCRF + tCSS0). Note 6: DOUT speed limits overall SPI speed. 50MHz is only specified without DOUT functionality. ���������������������������������������������������������������� Maxim Integrated Products 10 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface DIN R3 R2 R1 R0 D17 tDS 1 3 2 4 D14 D1 D0 – 5 6 7 8 21 22 – X 23 24 25 tCSA tCH tCSSO tCSH0 D15 tCP tDH SCLK D16 tCSH1 tCL CS tCSPW DOUT tDOT tDOE Z 0 R3 R2 R1 R0 D17 D16 tDOH D15 D2 tDOZ D1 D0 tCSF 0 Z tCRH READY tCRF tCSR Figure 1. Serial Interface Timing Diagram, Stand-Alone Operation Typical Operating Characteristics (VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) VREF = 2.5V VAVDD = 3V 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 VREF = 2.5V VAVDD = 3V 0.4 INL (LSB) DNL (LSB) 0.5 MAX5316 toc01 0.5 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5316 toc02 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE -0.5 0 16384 32768 CODE 49152 65536 0 16384 32768 49152 65536 CODE ���������������������������������������������������������������� Maxim Integrated Products 11 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Typical Operating Characteristics (continued) (VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) 0.3 0.3 0.1 -0.1 DNL (LSB) 0.1 INL (LSB) 0.2 0.1 0 0 -0.1 0 -0.1 -0.2 -0.2 -0.2 -0.3 -0.3 -0.3 -0.4 -0.4 -0.4 -0.5 -0.5 32768 49152 -0.5 0 16384 32768 49152 65536 16384 32768 49152 CODE CODE INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. TEMPERATURE INTEGRAL NONLINEARITY vs. TEMPERATURE 0.4 0.3 0.2 0.1 0.1 DNL (LSB) 0.2 0 -0.1 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 MIN DNL 32768 CODE 49152 65536 0.8 VREF = 2.5V 0.6 MAX INL 0.4 0.2 0 -0.2 -0.4 MIN INL -0.6 -0.8 -0.5 16384 1.0 MAX DNL 0 -0.2 -0.5 VREF = 2.5V 65536 MAX5316 toc08 0.5 INL (LSB) 0.3 0 0 CODE VREF = 5V VAVDD = 5.25V 0.4 65536 MAX5316 toc07 0.5 16384 VREF = 5V VAVDD = 5.25V 0.4 0.2 0 INL (LSB) 0.5 0.2 MAX5316 toc06 DNL (LSB) 0.3 VREF = 4.096V VAVDD = 5V 0.4 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5316 toc05 VREF = 4.096V VAVDD = 5V 0.4 0.5 MAX5316 toc03 0.5 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5316 toc04 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE -1.0 -40 -25 -10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) -40 -25 -10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) ���������������������������������������������������������������� Maxim Integrated Products 12 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Typical Operating Characteristics (continued) (VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) 0.3 -0.1 0 -0.2 -0.3 -0.6 -0.4 -0.8 -0.5 -1.0 -40 -25 -10 5 20 35 50 65 80 95 110 0.1 0 -0.1 -0.2 MIN INL -0.4 -0.5 -40 -25 -10 5 2.7 20 35 50 65 80 95 110 3.1 3.5 3.9 4.3 4.7 TEMPERATURE (°C) VAVDD (V) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE 0.3 MAX DNL 0.3 0.1 0.1 0.1 -0.1 -0.2 INL (LSB) 0.2 DNL (LSB) 0.2 0 -0.1 -0.2 -0.3 3.1 3.5 3.9 4.3 VAVDD (V) 4.7 5.1 5.5 4.8 5.2 0 -0.1 -0.3 -0.4 -0.5 MAX INL -0.2 MIN DNL -0.3 MIN INL -0.4 VAVDD = 5.25V 0.4 0.2 0 5.5 MAX5316 toc14 VAVDD = 5.25V 0.4 5.1 0.5 MAX5316 toc13 MAX INL 0.3 0.5 MAX5316 toc12 VREF = 2.5V 2.7 MIN DNL -0.3 TEMPERATURE (°C) 0.5 0.4 0.2 0.2 -0.4 MIN DNL MAX DNL 0.3 DNL (LSB) INL (LSB) DNL (LSB) 0 VREF = 2.5V 0.4 MAX INL 0.4 0.1 -0.2 INL (LSB) 0.6 MAX DNL 0.2 VREF = 4.096V 0.8 0.5 MAX5316 toc10 VREF = 4.096V 0.4 1.0 MAX5316 toc09 0.5 DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs. TEMPERATURE MAX5316 toc11 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE MIN INL -0.4 -0.5 -0.5 2.4 2.8 3.2 3.6 4.0 4.4 REFERENCE VOLTAGE (V) 4.8 5.2 2.4 2.8 3.2 3.6 4.0 4.4 REFERENCE VOLTAGE (V) ���������������������������������������������������������������� Maxim Integrated Products 13 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Typical Operating Characteristics (continued) (VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) 0.1 0 -0.1 -0.2 0.2 0.1 0 -0.1 -0.2 0.4 0 -0.2 -0.6 -0.4 -0.4 -0.8 -1.0 -0.5 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 VAVDD (V) 0.4 SINKING 0 SOURCING -0.2 -0.4 2 0 -2 -8 -1.0 -10 9 12 15 18 21 24 27 30 OUTPUT CURRENT (mA) CODE = 0x0640 VAVSS = 0V VREF = 4.096V SINKING CURRENT TA = +25°C -4 9 12 15 18 21 24 27 30 10 MAX5316 toc19 4 -0.8 6 6 OUTPUT DRIVE CAPABILITY 6 -6 3 3 OUTPUT CURRENT (mA) 8 -0.6 0 0 5.5 OUTPUT DRIVE CAPABILITY OUTPUT ERROR (LSB) CODE = 0xFFFF VREF = 4.096V 0.2 5.1 10 MAX5316 toc18 1.0 0.6 4.7 VAVDD (V) FULL-SCALE OUTPUT ERROR vs. OUTPUT CURRENT 0.8 4.3 CODE = 0xFFFF VAVDD = 4.2V VREF = 4.096V SOURCING CURRENT TA = +25°C 8 6 OUTPUT ERROR (LSB) 3.1 SOURCING -0.4 -0.3 2.7 SINKING 0.2 -0.3 -0.5 OUTPUT ERROR (LSB) 0.6 MAX5316 toc20 0.2 CODE = 0x0000 VAVSS = -1.25V VREF = 4.096V 0.8 OUTPUT ERROR (LSB) 0.3 OUTPUT ERROR (LSB) OUTPUT ERROR (LSB) 0.3 VREF = 2.5V CODE = 0xFFFF 0.4 1.0 MAX5316 toc16 VREF = 2.5V CODE = 0x0000 0.4 0.5 MAX5316 toc15 0.5 ZERO-SCALE OUTPUT ERROR vs. OUTPUT CURRENT FULL-SCALE OUTPUT ERROR vs. SUPPLY VOLTAGE MAX5316 toc17 ZERO-SCALE OUTPUT ERROR vs. SUPPLY VOLTAGE 4 2 0 -2 -4 -6 -8 -10 0 1 2 3 4 5 6 OUTPUT CURRENT (mA) 7 8 0 1 2 3 4 5 6 7 8 OUTPUT CURRENT (mA) ���������������������������������������������������������������� Maxim Integrated Products 14 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Typical Operating Characteristics (continued) (VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) 0 CODE = 0x0000 VAVSS = -1.25V VREF = 4.096V SINKING CURRENT TA = +25°C -4 -6 -8 -10 0 -2 -4 -6 -8 5 10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 45 50 OUTPUT CURRENT (mA) OUTPUT DRIVE CAPABILITY SUPPLY CURRENT vs. SUPPLY VOLTAGE POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 0 -2 5.9 5.8 TA = +105°C 5.5 5.4 5.2 OUTPUT CURRENT (mA) TA = +105°C 25 20 TA = +25°C 5.1 5 10 15 20 25 30 35 40 45 50 55 60 VPD = VDDIO VREF = 4.096V 35 30 5.6 5.3 -10 40 5.7 -6 -8 VREF = 4.096V MAX5316 toc25 6.0 -4 0 0 IAVDD (µA) 2 -10 0 IAVDD (mA) 4 CODE = 0x0000 VAVSS = -1.25V VREF = 2.5V SINKING CURRENT TA = +25°C -4 OUTPUT CURRENT (mA) CODE = 0xFFFF VAVDD = 5V VREF = 2.5V SOURCING CURRENT TA = +25°C 6 0 -2 OUTPUT CURRENT (mA) 10 8 2 -8 10 15 20 25 30 35 40 45 50 MAX5316 toc24 5 4 -6 -10 0 OUTPUT ERROR (LSB) 2 6 MAX5316 toc26 2 4 8 OUTPUT ERROR (LSB) 4 -2 6 OUTPUT ERROR (LSB) 6 CODE = 0xFFFF VAVDD = 5V VREF = 4.096V SOURCING CURRENT TA = +25°C 8 OUTPUT DRIVE CAPABILITY 10 MAX5316 toc22 MAX5316 toc21 8 OUTPUT ERROR (LSB) OUTPUT DRIVE CAPABILITY 10 MAX5316 toc23 OUTPUT DRIVE CAPABILITY 10 TA = +25°C 15 TA = -40°C 5.0 TA = -40°C 10 4.50 4.75 5.00 VAVDD (V) 5.25 5.50 4.50 4.75 5.00 5.25 5.50 VAVDD (V) ���������������������������������������������������������������� Maxim Integrated Products 15 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Typical Operating Characteristics (continued) (VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) OUTPUT NOISE DENSITY MAX5316 toc27 400 300 200 0 0 16384 32768 49152 80 MAX5316 toc29 70 60 VOUT 1µV/div 50 40 30 20 CURRENT OUT OF AGND_F AND AGND_S VREF = 4.096V 100 CODE = 0x8000 90 VOLTAGE NOISE (nV/√Hz) CURRENT (µA) 500 0.1Hz TO 10Hz OUTPUT NOISE 100 MAX5316 toc28 GROUND CURRENT vs. CODE 600 10 0 65536 10 CODE 100 1k 10k 100k 1s/div FREQUENCY (Hz) MAJOR CARRY GLITCH (1 LSB NEGATIVE STEP) MAJOR CARRY GLITCH (1 LSB POSITIVE STEP) MAX5316 toc30 MAX5316 toc31 VLDAC 5V/div VLDAC 5V/div VOUT 10mV/div VOUT 10mV/div 400ns/div 400ns/div SETTLING TIME (CODE = 0x1000 TO 0xF000) SETTLING TIME (CODE = 0xF000 TO 0x1000) MAX5316 toc32 MAX5316 toc33 VLDAC 5V/div VLDAC 5V/div VOUT 2V/div VOUT 2V/div VOUT 200µV/div 1µs/div VOUT 200µV/div 1µs/div ���������������������������������������������������������������� Maxim Integrated Products 16 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Typical Operating Characteristics (continued) (VAVDD_ = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) DIGITAL CLOCK FEEDTHROUGH ENTERING POWER-DOWN RESPONSE MAX5316 toc34 MAX5316 toc35 VSCLK 5V/div VPD 1V/div VOUT 1mV/div VOUT 2V/div 10µs/div 2µs/div SLOW POWER-UP RESPONSE (RSTSEL = LOW) EXITING POWER-DOWN RESPONSE MAX5316 toc37 MAX5316 toc36 VAVDD 5V/div VPD 1V/div VAVSS 2V/div VREFO 2V/div VBYPASS 2V/div VOUT 2V/div VOUT 2V/div 4ms/div 10µs/div SLOW POWER-UP RESPONSE (RSTSEL = HIGH) MAX5316 toc38 VAVDD 5V/div VAVSS 2V/div VREFO 2V/div VBYPASS 2V/div VOUT 2V/div 4ms/div ���������������������������������������������������������������� Maxim Integrated Products 17 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface RST VDDIO DGND BYPASS TOP VIEW READY Pin Configuration 24 23 22 21 20 + M/Z 1 19 AVDD2 BUSY 2 18 AGND_F LDAC 3 17 AGND_S DOUT 4 16 REF DIN 5 15 REFO SCLK 6 14 RFB CS 7 13 OUT MAX5316 11 12 AVDD1 PD 10 AGND 9 AVSS 8 TC/SB *EP TQFN *EXPOSED PAD-CONNECT TO AGND. Pin Description PIN 1 NAME FUNCTION M/Z Reset Select Input. M/Z selects the default state of the analog output (OUT) after power-on or hardware or software reset. Connect M/Z to VDDIO to set the default output voltage to midscale or to DGND to set the default output voltage to zero scale. BUSY Digital Input/Open-Drain Output. Connect a 5.1kI pullup resistor from BUSY to VDDIO. BUSY goes low immediately after writing to the DIN register. During this time, the user can continue writing new data to the DIN register, but no further updates to the DAC register and DAC output can take place. If LDAC is asserted low while BUSY is low, this event is stored. BUSY is bidirectional, and can be asserted low externally to delay LDAC action. BUSY also goes low during power-on reset, when RST is low, or when software reset is activated. 3 LDAC Active-Low Load DAC Logic Input. If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC register and the DAC output is updated. If LDAC is taken low while BUSY is asserted low, the LDAC event is stored and the DAC register update is delayed until BUSY deasserts. Any event on LDAC during power-on reset or when RST is low is ignored. 4 DOUT SPI Bus Serial Data Output. See the Serial Interface section for details. 2 ���������������������������������������������������������������� Maxim Integrated Products 18 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Pin Description (continued) PIN NAME 5 DIN SPI Bus Serial Data Input. See the Serial Interface section for details. FUNCTION 6 SCLK SPI Bus Serial Clock Input. See the Serial Interface section for details. 7 CS 8 TC/SB SPI Bus Active-Low Chip-Select Input. See the Serial Interface section for details. DIN Format Select Input. Connect TC/SB to DGND to set the data input format to straight binary or to VDDIO to set it to two’s complement. Active-High Power-Down Input. Connect PD to DGND for normal operation. Connect PD to VDDIO to place the device in power-down. In power-down, OUT (analog voltage output) is connected to AGND through a 2kω resistor, but the contents of the input registers and the DAC latch do not change. The SPI interface remains active in power-down. 9 PD 10 AVSS Negative Analog Power-Supply Input. Connect to AGND or a negative supply voltage. When connected to the negative supply voltage, bypass AVSS with a 0.1µF capacitor to AGND. 11 AGND Analog Ground. Connect to the analog ground plane. 12, 19 AVDD1 Positive Analog Power-Supply Input. Bypass each AVDD_ locally with a 0.1µF and 10µF capacitor to AGND (analog ground plane). Connect AVDD1 and AVDD2 together. 13 OUT Buffered Analog Voltage Output. Connect OUT to RFB externally to close the output buffer feedback loop. The buffered output is capable of directly driving a 10kω load. The state of M/Z sets the power-on reset state of OUT (zero or midscale). In power-down, OUT is connected to AGND through a 2kω pulldown resistor. 14 RFB Feedback Resistor Input. RFB is connected through the internal feedback resistor to the inverting input of the analog output buffer. Externally connect RFB to OUT to close the output buffer feedback loop. 15 REFO 16 REF 17 AGND_S DAC Analog Ground Sense 18 AGND_F DAC Analog Ground Force. Connect to the analog ground plane. 19 AVDD2 Positive Analog Power-Supply Input. AVDD2 supplies power to the internal digital linear regulator. Bypass AVDD2 locally to AGND with 0.1µF and 10µF capacitors. Connect AVDD2 and AVDD1 together. 20 BYPASS Internal Bypass Connection. Connect BYPASS to DGND with 0.01µF and 1µF capacitors. 21 DGND Digital Ground 22 VDDIO Digital Interface Power-Supply Input. Connect to a 1.7V to 5.5V logic-level supply. Bypass VDDIO with a 0.1µF capacitor to DGND. The supply voltage at VDDIO sets the logic-level for the digital interface. 23 RST Active-Low Reset Input. Drive RST low to DGND to put the device into a reset state. A reset state sets all SPI input registers to their default power-on reset states as defined by the state of inputs M/Z and TC/SB. Set RST high to VDDIO, the DAC output remains at the state defined by M/Z until LDAC is taken low. 24 READY SPI Active-Low Ready Output. READY asserts low when the device successfully completes processing an SPI data frame. READY asserts high at the next rising edge of CS. In daisy-chain applications, the READY output typically drives the CS input of the next device in the chain or a GPIO of a microcontroller. — EP Voltage Reference Buffered Output. Bypass with a 100pF capacitor to AGND. High-Impedance 10Mω Voltage Reference Input Exposed Pad. EP is internally connected to AGND. Connect to the analog ground plane. ���������������������������������������������������������������� Maxim Integrated Products 19 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Detailed Description The MAX5316 is a high-accuracy, 16-bit, serial SPI input, buffered voltage output digital-to-analog converter (DAC) in a 4mm x 5mm, 24-lead TQFN package. The device features Q1 LSB INL (max) accuracy and a Q1 LSB DNL (max) accuracy over the -40NC to +105NC temperature range. The DAC voltage output is buffered with a fast settling time of 3Fs and a low offset and gain drift of Q0.6ppm/NC of FSR (typ). The force-sense output (OUT) maintains accuracy while driving loads with long lead lengths. A separate AVSS supply allows the output amplifier to go to 0V (GND) while maintaining full linearity performance. At power-up, the device resets its outputs to zero or midscale, providing additional safety for applications which drive valves or other transducers that need to be off on power-up. This is selected by the state of the M/Z input on power-up. The wide supply voltage range of 2.7V to 5.5V and integrated low-drift, low-noise reference buffer amplifier makes for ease of use. Since the reference buffer input has a high input resistance, an external buffer is not required. The device accepts an external reference between 2.4V and VAVDD - 0.1V for maximum flexibility. The MAX5316 features a 50MHz, 3-wire SPI, QSPI, MICROWIRE, and DSP-compatible serial interface. The separate digital interface supply voltage input (VDDIO) is compatible with a wide range of digital logic levels from 1.7V to 5.5V, eliminating the need for separate voltage translators. The positive analog supply voltage (AVDD_) determines the maximum output voltage of the device as AVDD_ powers the output buffer. The output is diode clamped to ground, preventing negative voltage excursions beyond approximately -0.6V. Negative Supply Voltage (AVSS) The negative supply voltage (AVSS) determines the minmum output voltage. If AVSS is connected to ground, the output voltage can be set to as low as 100mV without degrading linearity. For operation down to 0V, connect AVSS to a negative supply voltage between -0.1V and -1.25V. The MAX1735 is recommended for generating -1.25V from a -5V supply. Force/Sense The MAX5316 uses force/sense techniques to ensure that the load is regulated to the desired output voltage despite line drops due to long lead lengths. Since AGND_F and AGND_S have code dependent ground currents, a ground impedance less than 13mω ensures that the INL will not degrade by more than 0.1 LSB. Form a star ground connection (Figure 2a) near the device with AGND_F, AGND_S, and AGND tied together. Always refer remote DAC loads to this system ground for best performance. Figure 2b shows how to configure the device and an external op amp for proper force/sense operation. The amplifier provides as much drive as needed to force the sensed voltage (measured between RFB and AGND_S) to equal the desired voltage. DAC Reference Buffer The external reference input has a high input (REF) impedance of 10MI || 10pF and accepts an input voltage from +2.4V to VAVDD - 0.1V. Connect an external reference supply between REF and AGND. Bypass the reference buffer output REFO to AGND with a 100pF capacitor. Connect the anode of an external Schottky diode to REF and the cathode to AVDD1 to prevent internal ESD diode conduction in the event that the reference voltage comes up before AVDD at power up. Follow the recommendations described in the Power-Supply Sequencing section. OUT RFB MAX5316 Figure 2a. Star Ground Connection Visit www.maxim-ic.com/products/references for a list of available external voltage-reference devices. Output Amplifier (OUT) The MAX5316 includes an internal buffer for the DAC output. The internal buffer provides improved load regulation for the DAC output. The output buffer slews at 5V/Fs and can drive up to 2kI in parallel with 200pF. The buffer has a rail-to-rail output capable of swinging to within 100mV of AVDD_ and AVSS. AGND_F AGND_S AGND OUT RFB MAX5316 AGND AGND_F AGND_S Figure 2b. Force/Sense Connection ���������������������������������������������������������������� Maxim Integrated Products 20 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface 16-Bit Ideal Transfer Function Input Range The transfer function for the MAX5316 is given by: CODE V= OUT VREF × 216 (DIN code from 0x0000 to 0xFFFF) The range of DIN is summarized in Table 3 and Table 4. Also shown are the range values for the MAX5316 with a 4.096V reference. Note that VREF is the reference voltage applied to REF and 1 LSB is equal to VREF/216. For the simple binary case and: VOUT = VREF × VOUT (CODE − 0x8000) FULL-SCALE VREF 16 2 (DIN code from 0x8000 to 0xFFFF) VOUT =VREF × CODE 216 V + REF 2 VREF/2 MIDSCALE (DIN code from 0x0000 to 0xFFFF) ZERO-SCALE DIN 0V For the two’s complement case. 0x8000 0x0000 0x0000 0x8000 Straight Binary vs. Two’s Complement Table 1 and Table 2 show the math necessary to convert the DIN code into VOUT for the 16-bit DAC. 1 LSB is equal to VREF/216. 0xFFFF 0x7FFF STRAIGHT BINARY TWO’S COMPLEMENT Figure 3. DIN to VOUT Transfer Curve Table 1. Straight Binary Mode DIN CODE EQUATION FOR VOUT V= OUT VREF × 0x0000 to 0xFFFF RANGE CODE 0V to (VREF - 1 LSB) 216 Table 2. Two’s Complement Mode DIN CODE EQUATION FOR VOUT 0x8000 to 0xFFFF 0x0000 to 0x7FFF RANGE CODE − 0x8000 = VREF × VOUT 216 VOUT =VREF × CODE 216 + 0V to (VREF/2 -1 LSB) VREF 2 VREF/2 to (VREF - 1 LSB) Table 3. DIN Range (Straight Binary Mode) RANGE DIN CODE VOUT (V) MAX5316 VALUE (V) Minimum 0x0000 0 0 Maximum 0xFFFF (VREF - 1 LSB) 4.095938 Table 4. DIN Range (Two’s Complement Mode) RANGE DIN CODE VOUT (V) MAX5316 VALUE (V) Minimum 0x8000 0 0 Maximum 0x7FFF (VREF - 1 LSB) 4.095938 ���������������������������������������������������������������� Maxim Integrated Products 21 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Reset The device is reset upon power-on, hardware reset using RST, or software reset using register 0x4, bit 15, command RSTSW. After reset, the value of the input register, the DAC latch and the output voltage are set to the values defined by the M/Z input. If a hardware reset occurs during a SPI programming frame, anything before and after the reset for the frame will be ignored. A software reset initiated through the SPI interface takes effect after the end of the valid frame. Output State Upon Reset The output voltage can be set to either zero or midscale upon power-up, or a hardware or software reset, depending on the state of the M/Z input. After power-up, if the device detects that this input is low, the output voltage is set to zero scale. If M/Z is high, the output voltage is set to midscale. Note that during reset, when RST is low or RSTSW is set to 0, the output voltage is set slightly lower than the value after coming out of reset. During reset, the output voltage is set to the values shown for the VOUT-RESET specification in the Electrical Characteristics. Power-Down The device can be powered down by either hardware (pulling PD high) or software (setting the PD_SW bit in either the 0x4 or 0xC registers). Note that the hardware and software inputs are ORed. Asserting either is enough to place the device in power-down mode. LDAC and BUSY Interaction The BUSY line is open drain and is normally pulled up by an external resistor. It is software-configurable to be bidirectional and can be pulled down externally. Whenever the DIN register is changed, the device transfers the value to the DAC register. To indicate to the host processor that the device is busy transferring, the device pulls the BUSY output low. Once transfer is complete, the device releases BUSY and the host processor can load the DAC by toggling the LDAC input. If LDAC is set low while BUSY is low, the LDAC event is latched and implemented when the transfer is complete and BUSY rises. There are four ways in which the LDAC and BUSY outputs can be used. This is shown graphically in Figure 4. 1)The host sends a new command. The device sets BUSY low. The host monitors BUSY to determine when it goes high. The device then pulses LDAC low to update the DAC. 2)The host sends a new command. The device sets BUSY low. The host toggles LDAC low then high before BUSY goes high. The device latches the LDAC event but does not implement it until processing is complete. Then, BUSY goes high and the device updates the DAC. 3) LDAC is held low. The host sends a new command and the device sets BUSY low. The device updates the DAC when the processing is complete and BUSY goes high. In power-down, the output is internally connected to AGND through a 2kI resistor. The SPI interface remains active and the DAC register content remains unchanged. 4) BUSY is pulled down externally to delay DAC update. The BUSY pin is bidirectional. To use BUSY as an input, set the NO_BUSY bit to 1 using the 0x4 or 0xC command. When configured as an input, pulling BUSY low at least 50ns before the device releases the line delays DAC update. DAC update occurs only after BUSY is released and goes high. If used as an input, drive BUSY with an open-drain output with a pullup to VDDIO. Data Format Selection (Straight Binary vs. Two’s Complement) If the DAC must be updated at a precise time with the least amount of jitter, use option 1. In order to restore normal operation to the device, satisfy both of these conditions: 1) Pull PD low. 2) Set the bits PD_SW’s (in both 0x4 and 0xC registers) to 0. The MAX5316 interprets the data code input (DIN) as either straight binary or two’s complement. To choose the straight binary format, set the TC/SB input low. For two’s complement, set the input high. ���������������������������������������������������������������� Maxim Integrated Products 22 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface DIN X 1 2 X 21 22 23 X INPUT REGISTER LOADED SCLK BUSY tBUSY LDAC tS tCBF OPTION 1 VOUT tLDPW LDAC tLDH OPTION 2 VOUT LDAC OPTION 3 OPTION 4 VOUT BUSY (USED AS INPUT) BUSY PULLED LOW EXTERNALLY 50ns LDAC VOUT Figure 4. BUSY and LDAC Timing Serial Interface Overview The SPI interface supports speeds up to 50MHz. When CS is high, the remaining interface inputs are disabled to reduce transient currents. The interface supports daisy chaining to enable multiple device to be controlled on the same SPI bus. The device has a double-buffered interface consisting of two register banks: the input register and the DAC register. The input register for DIN is connected directly to the 24-bit SPI input shift register. The DAC latch contains the DAC code and is loaded as defined in the LDAC and BUSY Interaction section. A valid SPI frame is 24-bit wide with 4-bit command R3 to R0, 16-bit data D15 to D0, and 4 unused LSBs. A full 24-bit SPI command sequence is required for all SPI command operations, regardless of the number of data bits actually used for the command. Any commands terminating with less than a full 24-bit sequence will be aborted without impacting the operation of the part (subject to tCSA timing requirements). Data is not written into the SPI input register or DAC and it continues to hold the preceding valid data. If a command sequence with more than 24 bits is provided, the command will be executed on the 24th SCLK falling edge and the remainder of the command will be ignored. All SPI commands result in the device assuming control of the DOUT line from the first SCLK edge through the 24th SCLK edge. After relinquishing the DOUT line, the MAX5316 will return to a high-impedance state. An optional bus hold circuit can be engaged to hold DOUT at its last bit value while not interfering with other devices on the bus. DOUT is disabled at power-up and must be enabled through the SPI interface. When enabled, DOUT echoes the 4-bit command plus 16-bit data, which is being programmed. During readback, DOUT echoes the 4-bit command followed by the true readback data depending upon the type of read command. Table 11 shows the bit positions for DOUT and DIN within the 24-bit SPI frame. The device is designed such that SCLK idles low, and DIN and DOUT change on the rising clock edge and get latched on the falling clock edge. The SPI host controller should be set accordingly. ���������������������������������������������������������������� Maxim Integrated Products 23 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface chain, each individual command in the chain is executed on the 24th falling clock edge following the falling edge of the respective CS input. To update just one device in a daisy chain, send the no-op command to the other device in the chain. To update the first device in the chain, raise the CS input after writing to that device. Daisy-Chain SPI Operation Using READY Output The READY pulse appears 24 clock cycles after the negative edge of CS as shown in Figure 5 and can therefore be used as the CS line for the next device in the daisy chain. Since the device looks at the first 24 bits of the transmission following the falling edge of CS, it is possible to daisy-chain the device with different command word lengths. READY goes high after CS is driven high. Because daisy-chain operation requires paralleling the DOUTs of all the MAX5316 in the chain, the NO_HOLDEN bit in register 0x4 or 0xC should be set to 1 for all devices. Doing so ensures that DOUT goes into high-impedance after the SPI frame is complete (i.e. after the 24th clock cycle) as shown in Figure 6. To perform a daisy-chain write operation, drive CS low and output the data serially to DIN. The propagation of the READY signal then controls how the data is read by the device. As the data propagates through the daisy Table 5. SPI Command and Data Mapping with Clock Falling Edges CLOCK EDGE DIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 R3 R2 R1 R0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 0 R3 R2 R1 R0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X Note that ‘X’ is don’t care. µC MISO MOSI SCK SLAVE 1 CS READY CS SLAVE 3 POUT DIN SCLK DOUT DIN SCLK DOUT DIN SCLK I/O SLAVE 2 READY CS READY Figure 5. Daisy-Chain SPI Connection Terminating with a Standard SPI Device ���������������������������������������������������������������� Maxim Integrated Products 24 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Command and Register Map Stand-Alone Operation The diagram in Figure 7 shows a stand-alone connection of the MAX5316 in a typical SPI application. If more than one peripheral device shares the DOUT bus, the NO_HOLDEN bit in register 0x4 or 0xC should be set to 1 for the MAX5316. Doing so ensures that DOUT goes into high-impedance after the SPI frame is complete (i.e. after the 24th clock cycle). All command and data registers have read and write functionality. The register selected depends on the command select bits R[3:0]. Each write to the device consists of 4 command select bits (R[3:0]), 16 data bits (which are detailed in Tables 7–11), and 4 don’t care LSBs. A summary of the commands is shown in Table 6. CS DIN SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA SCLK READY 1 1 2 3 4 20 21 22 23 24 1 2 3 4 5 21 22 23 24 1 2 3 4 5 21 22 23 24 READY 2 READY 3 HI-Z DOUT1 HI-Z DOUT2 HI-Z HI-Z DOUT3 Figure 6. Daisy-Chain SPI Connection Timing TO OTHER DEVICES/CHAINS µC CSm MAX5316 CS1 CS SCLK DWRITE DREAD CS SCLK DIN DOUT Figure 7. Stand-Alone Operation ���������������������������������������������������������������� Maxim Integrated Products 25 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Table 6. Register Map Summary HEX R3 R2 R1 R0 FUNCTION 0 0 0 0 0 No-op. Used mainly in daisy-chain communications. 1 0 0 0 1 DIN register write 2, 3, 5–8, A, B, D–F — — — — Reserved 4 0 1 0 0 Configuration register write 9 1 0 0 1 DIN register read C 1 1 0 0 Configuration and status register read. Register Details Table 7. No-Op Command (0x0) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME X X X X X X X X X X X X X X X X DEFAULT X X X X X X X X X X X X X X X X BIT NAME 15:0 Don’t care DESCRIPTION No action on SPI shift register and DAC input registers. Use for daisy-chain purposes when R[3:0] = 0000. Table 8a. Straight Binary DIN Write Register (TC/SB) = 0) (0x1) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 0x0000 when MZ = DGND (zero scale) 0x8000 when MZ = VDDIO (midscale) BIT 15:0 NAME B[15:0] DESCRIPTION 16-bit DAC input code in straight binary format. For clarity, a few examples are shown below. 0000 0000 0000 0000 0x0000 zero scale 0100 0000 0000 0000 0x4000 quarter scale 1000 0000 0000 0000 0x8000 midscale 1100 0000 0000 0000 0xC000 three-quarter scale 1111 1111 1111 1111 0xFFFF full scale - 1 LSB ���������������������������������������������������������������� Maxim Integrated Products 26 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Table 8b. Two’s Complement DIN Write Register (TC/SB) = 1) (0x1) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 0x8000 when MZ = DGND (zero scale) 0x0000 when MZ = VDDIO (midscale) BIT 15:0 NAME DESCRIPTION B[15:0] 16-bit DAC input code in two’s complement format. For clarity, a few examples are shown below. 1000 0000 0000 0000 0x8000 zero scale 1100 0000 0000 0000 0xC000 quarter scale 1111 1111 1111 1111 0xFFFF midscale – 1 LSB 0000 0000 0000 0000 0x0000 midscale 0000 0000 0000 0001 0x0001 midscale + 1 LSB 0100 0000 0000 0000 0x4000 three-quarter scale 0111 1111 1111 1111 0x7FFF full scale – 1 LSB Table 9. General Configuration Write Register (0x4) BIT NAME DEFAULT 15 14 PD_SW NO_HOLDEN 0 0 BIT NAME 15 PD_SW 14 13 13 RST_SW 1 12 11 10 9 8 7 6 5 4 3 2 1 0 NO_BUSY 0 DOUT_ON X X X X X X X X X X X 0 X X X X X X X X X X X DESCRIPTION Software PD (Power-Down). Equivalent to the PD input. 0: Normal mode 1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor. NO_HOLDEN SPI Bus Hold Enable. 0: Bus hold enabled for SPI DOUT output. DOUT stays at its last value after the SPI CS input rises at the end of the SPI frame (i.e. after the 24th clock cycle). 1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS input rises at the end of the SPI frame (i.e. after the 24th clock cycle). RST_SW Software Reset. Equivalent to the RST input. 0: Place device in reset 1: Normal operation Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low) NO_BUSY BUSY Input Disable. 0: BUSY input is active. 1: BUSY input is disabled. Note that this does not affect the BUSY bit in the General Configuration and Status Register. The BUSY pin is bidirectional. When enabled, it can be pulled down externally to delay DAC updates. 11 DOUT_ON SPI DOUT Output Disable. DOUT is disabled by default. 0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the duration of the SPI frame. 1: DOUT output enabled. 10:0 — 12 Don’t care. These bits are reserved for the corresponding read command. ���������������������������������������������������������������� Maxim Integrated Products 27 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Table 10. DIN Read Register (0x9) BIT NAME DEFAULT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NAME 15:0 B[15:0] DESCRIPTION 16-bit DIN readback value stored in the bits B[15:0]. Table 11. General Configuration and Status Read Register (0xC) BIT NAME DEFAULT 15 14 13 12 11 10 9 8 7 6 5 4 PD_SW NO_ HOLDEN RST_SW NO_BUSY DOUT_ON BUSY X X X X X X REV_ID[3:0] 0 0 1 0 0 0 0 0 0 0 0 0 0001 BIT NAME 15 PD_SW 14 NO_HOLDEN 3 2 1 0 DESCRIPTION Software PD (Power-Down). Equivalent to the PD input. 0: Normal mode. 1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor. SPI Bus Hold Enable. 0: Bus hold enabled for SPI DOUT output. DOUT stays at its final value after the SPI CS input rises at the end of the SPI frame. 1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS input rises at the end of the SPI frame. RST_SW Software Reset. Equivalent to the RST input. 0: Place device in reset. 1: Normal operation. Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low). NO_BUSY BUSY Input Disable. 0: BUSY input is active. 1: BUSY input is disabled. Note that this does not affect the BUSY bit in the General Configuration and Status Register. The BUSY pin is bidirectional. When enabled, it can be pulled down externally to delay DAC updates. 11 DOUT_ON SPI DOUT Output Disable. DOUT is disabled by default. 0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the duration of the SPI frame. 1: DOUT output enabled. 10 BUSY 9:4 — 3:0 REV_ID[3:0] 13 12 Global BUSY status readback. 0: Device is busy transferring DIN code to the DAC register. 1: Device is not busy. Reserved. Will read back 0. Device revision ���������������������������������������������������������������� Maxim Integrated Products 28 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Applications Information Power-On Reset (POR) Upon power-on, the output is set to either zero-scale (if M/Z is low) or midscale (if M/Z is high). The entire register map is set to their default values as shown in Tables 7–11. Power Supplies and Bypassing Considerations For best performance, use a separate supply for the MAX5316. Bypass VDDIO, AVDD_, and AVSS with highquality ceramic capacitors to a low-impedance ground as close as possible to the device. A typical high-quality X7R 10FF capacitor can become self resonant at 2MHz. Therefore, it is actually an inductor above 2MHz and is useless for decoupling signals above 2MHz. It is therefore recommended that several capacitors of different values are connected in parallel (e.g. 0.1µF || 10µF). Figure 8 shows the magnitude of impedance of typical 1FF, 100nF, and 10nF X7R capacitors. As the capacitance reduces, the self-resonant frequency increases. In addition, the parallel combination of all three is shown and exhibits a significant improvement over a single capacitor. These plots do not include any PCB trace inductance. Minimize lead lengths to reduce lead inductance. Adding just 2nH trace inductance to each of the typical capacitors above produces the effects shown in Figure 9. This shows significant reduction in the self-resonant frequencies of the capacitors. Internal Linear Regulator (BYPASS) BYPASS is the output of an internal linear regulator and is used to power digital circuitry. Connect BYPASS to DGND with a ceramic capacitor in the range of 1FF to 10FF with ESR in the range of 100mI to 20mI to ensure stability. Power-Supply Sequencing During power-up, ensure that AVDD_ comes up before the reference does. If this is not possible, connect a Schottky diode between the REF and AVDD_ such as the MBR0530T1G. If REF does come up before AVDD_, the diode conducts and clamps REF to AVDD_. Once AVDD_ has come up, the diode no longer conducts. REF should always be below AVDD_ as specified in the Electrical Characteristics. AVDD_ and AVDD_ should be connected together and powered from the same supply. VDDIO and AVSS can be sequenced in any order. Always perform a reset operation after all the supplies are brought up to place the device in a known operating state. Layout Considerations Digital and AC transient signals on AGND inputs can create noise at the outputs. Connect both AGND inputs to form the star ground for the DAC system. Refer remote DAC loads to this system ground for the best possible performance (see the Force/Sense section). Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to AGND. Do not use wire-wrapped boards and sockets. Use ground plane 3k 1k 3k 1k 100 IMPEDANCE (I) IMPEDANCE (I) 100 10nF 10nF 10 100nF 1 1µF 100m 10m 4m 100k 1M 10nF 10 100nF 1 1µF 100m 10M FREQUENCY (Hz) Figure 8. Typical X7R Capacitor Impedance 100M 10m 4m 100k 1M 10M 100M FREQUENCY (Hz) Figure 9. Typical X7R Capacitor Impedance with Additional 2nH PCB Trace Inductance ���������������������������������������������������������������� Maxim Integrated Products 29 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface shielding to improve noise immunity. Do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the device package. Connect the exposed pad to AGND (analog ground plane). For a recommended layout, consult the MAX5316/ MAX5318 Evaluation Kit datasheet. Voltage Reference Selection and Layout The voltage reference should be placed close to the DAC. The same power-supply decoupling and grounding rules as the DAC should be implemented. Many voltage references require an output capacitor for stability or noise reduction. Provided the trace between the reference device and the DAC is kept short and well shielded, a single capacitor may be used and placed close to the DAC. However, for improved noise immunity, additional capacitors may be used but be careful not to exceed the recommended capacitance range for the voltage reference. Refer to Applications Note AN4300: Calculating the Error Budget in Precision Digital-to-Analog Converter (DAC) Applications for detailed description of voltage reference parameters and trading off the error budget. The MAX6126 is recommended for 16-bit applications. Optimizing Data Throughput Rate The LDAC and BUSY Interaction section details the timing of data written to the device and how the DAC is updated. Data throughput speed can be increased by overlapping the data load time with the busy period and settling time as shown below in Figure 10. Following the 24th SCLK falling edge, the device holds BUSY low while transferring the value from the DIN register to the DAC register. Providing that the LDAC falling edge arrives before the 24th SCLK falling edge, and assuming the SPI clock frequency is high enough, the throughput period is therefore limited by tBUSY and settling times only. A slight further increase in throughput time can be gained by either toggling LDAC during the busy period or by pulling it low permanently. However, the exact point at which the DAC update occurs is then determined internally as indicated by the BUSY line rising edge. This is not an exact time. BUSY Line Pullup Resistor Selection The BUSY pin is an open-drain output. It therefore requires a pullup resistor. A 5.1kI value is recommended as a compromise between power and speed. Stray capacitance on this line can easily slow the rise time to an unacceptable level. The BUSY pin can sink up to 5mA. Therefore a resistor as low as VDDIO/0.005 may be used if faster rise times are required. 24TH SCLK 24TH SCLK DIN BUSY tBUSY LDAC LDAC FALLING EDGE BEFORE 24TH SCLK FALLING EDGE OUT Figure 10. Optimum Throughput with Stable Update Period ���������������������������������������������������������������� Maxim Integrated Products 30 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Producing Unipolar High-Voltage and Bipolar Outputs Figure 11 and Figure 12 show how external op amps can be used to produce a unipolar high-voltage output and a bipolar output Definitions Gain Error Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after removing the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time Integral Nonlinearity (INL) The settling time is the amount of time required from the start of a LDAC high-to-low transition or BUSY low-to-high transition (whichever occurs last), until the DAC output settles to within 0.003% around the final value. Differential Nonlinearity (DNL) Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled. INL is the deviation of the measured transfer function from a straight line drawn between two codes. This line is drawn between the zero and full-scale codes of the transfer function, once offset and gain errors have been nullified. DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the DNL is less than or equal to 1 LSB, the DAC guarantees no missing codes and is monotonic. Offset Error Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. Digital Feedthrough Digital-to-Analog Glitch Impulse The glitch impulse occurs at the major carry transitions along the segmented bit boundaries. It is specified as the net area of the glitch impulse which appears at the output when the digital input code changes by 1 LSB. The glitch impulse is specified in nanovolts-seconds (nV-s). Digital-to-Analog Power-Up Glitch Impulse The digital-to-analog power-up glitch is the net area of the glitch impulse which appears at the output when the device exits power-down mode. MAX44251 MAX5316 MAX9632 OUT OUT -VREF TO VREF 0V TO KVREF K = 1 + R2 /R1 MAX5316 R1 R2 R1 R2 REFO R1 = R2 Figure 11. Unipolar High-Voltage Output Figure 12. Bipolar Output ���������������������������������������������������������������� Maxim Integrated Products 31 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Typical Operating Circuit 2.4V TO (VAVDD -0.1V) 0.1µF 5.1kI BUSY M/Z TS/SB PD GPIO’s RSTSEL LDAC µC READY CS SCLK SPI INTERFACE DIN DOUT 2.7V TO 5V MBR0530T1G 1.8V TO 5V 0.01µF 1µF 0.1µF 10µF VDDIO REF BYPASS AVDD2 AVDD1 22 16 20 19 12 2 0.1µF LINEAR REGULATOR 23 8 100pF 1 24 15 REFO BUFFER 9 3 10µF MAX5316 INTERFACE AND CONTROL 7 14 RFB INPUT REGISTER 6 DAC REGISTER 16-BIT DAC OUTPUT BUFFER 13 OUT RL 5 4 11 21 DGND AGND 17 AGND_S 10 18 AVSS AGND_F 0.1µF *CONNECT THE EXPOSED PAD TO AGND. 0 TO -1.25V Ordering Information PART MAX5316GTG+ TEMP RANGE PIN-PACKAGE -40NC to +105NC 24 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Chip Information Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 TQFN-EP T2445+1 21-0201 90-0083 PROCESS: BiCMOS ���������������������������������������������������������������� Maxim Integrated Products 32 MAX5316 16-Bit, ±1 LSB Accuracy Voltage Output DAC with SPI Interface Revision History REVISION NUMBER REVISION DATE 0 1/12 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2012 Maxim Integrated Products 33 Maxim is a registered trademark of Maxim Integrated Products, Inc.