19-5916; Rev 1; 2/12 MAX14821 IO-Link Device Transceiver General Description Features The MAX14821 transceiver is suitable for IO-Link® devices and 24V binary sensors/actuators. All specified IO-Link data rates are supported. In IO-Link applications, the transceiver acts as the physical layer interface to a microcontroller running the data-link layer protocol. Additional 24V digital inputs and outputs are provided. Two internal linear regulators generate common sensor and actuator power requirements: 5V and 3.3V. On-board C/Q and DO drivers are independently configurable for push-pull, high-side (PNP), or low-side (NPN) operation. The device detects the IO-Link C/Q wake-up condition and generates a wake-up signal on the activelow WU output. The C/Q and DI inputs have selectable current loads for use in actuators. An SPI™ interface allows configuration and monitoring of the device. Extensive alarm conditions are detected and communicated through the IRQ output and the SPI interface. The device features reverse-polarity, short-circuit, and thermal protection. All power lines are monitored for undervoltage conditions. The C/Q and DO drivers are specified for sourcing/sinking up to 100mA. The device is available in a 2.5mm x 2.5mm, 25-pin WLP and a 4mm x 4mm, 24-pin TQFN package. Both are specified over the extended -40NC to +85NC temperature range. S IO-Link Specification v.1.0 and v.1.1 Physical LayerCompliant S Supports COM1, COM2, and COM3 Data Rates S IO-Link Device Wake-Up Detection S Push-Pull, High-Side, or Low-Side Outputs S 100mA Specified C/Q Output Drive S Auxiliary 24V, 100mA Digital Output S Auxiliary 24V Digital Input S Optional 6mA/7mA Current Loads at Both 24V Inputs S 5V and 3.3V Linear Regulators S Reverse-Polarity Protected 24V Supply Output S EMI Emission Control Through Slew-Controlled Driver S SPI Interface for Configuration and Monitoring S 2.5V to 5V Logic Interface Levels S Reverse-Polarity and Short-Circuit Protection on All 24V Inputs/Outputs S High-Temperature Warning and Thermal Shutdown S Extensive Fault Monitoring and Reporting S -40NC to +85NC Operating Temperature Range S 2.5mm x 2.5mm WLP and 4mm x 4mm TQFN Packages Applications Ordering Information appears at end of data sheet. IO-Link Sensors Industrial Sensors and Actuators IO-Link Actuators Typical Operating Circuit 5V 3.3V 1μF 0.1μF 0.1μF 10kΩ VCC GPIO2 UV VL TXQ LDO33 V5 LDOIN VP 0.8Ω VCC 1μF SPI IRQ MICROCONTROLLER GND WU RX RX TX TXC RTS TXEN GPIO1 LO L+ DO MAX14821 1 2 C/Q DI GND 4 3 L- IO-Link is a registered trademark of Profibus User Organization (PNO). SPI is a trademark of Motorola, Inc. For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX14821.related ����������������������������������������������������������������� Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX14821 IO-Link Device Transceiver Functional Diagram LDO33 V5 LDOIN VP UV UV MONITOR 3.3V LDO 5V LDO VCC VL CS SDI SDO SCLK IRQ STATUS AND CONFIGURATION RX FILTER C/Q C/Q LOAD WAKE-UP DETECT WU PROTECTION DRIVER TXQ TXC TXEN LI PROTECTION GND PROTECTION DI PROTECTION DO DI LOAD DRIVER LO MAX14821 DoEn ����������������������������������������������������������������� Maxim Integrated Products 2 MAX14821 IO-Link Device Transceiver ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND, unless otherwise noted.) VCC..........................................................................-40V to +40V VP (IVP < 50mA)...... the higher of -0.3V and (VCC - 1V) to +40V LDOIN.....................................................................-0.3V to +40V V5...................... -0.3V to the lesser of (VLDOIN + 0.3V) and +6V LDO33...................... -0.3V to the lesser of (V5 + 0.3V) and +6V VL..............................................................................-0.3V to +6V DI ............................................................................-40V to +40V C/Q, DO....................... MIN: the higher of -40V and (VCC - 40V) MAX: the lesser of +40V and (VCC + 40V) Logic Inputs TXC, TXQ, TXEN, LO, CS, SDI, SCLK...... -0.3V to (VL + 0.3V) Logic Outputs RX, WU, LI, SDO, IRQ.............................. -0.3V to (VL + 0.3V) UV.........................................................................-0.3V to +6V Continuous Current Into Any Logic Pin............................ Q50mA Continuous Power Dissipation TQFN (derate 27.8mW/NC above +70NC)..................2222mW WLP (derate 22.7mW/NC above +70NC)....................1816mW Operating Temperature Range........................... -40NC to +85NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (TQFN only; soldering, 10s)..............+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (BJA)...........36NC/W Junction-to-Case Thermal Resistance (BJC)..................3NC/W WLP Junction-to-Ambient Thermal Resistance (BJA)...........44NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. DC ELECTRICAL CHARACTERISTICS (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS VCC Supply Voltage VCC For driver operation VCC Supply Current ICC VCC = 24V, C/Q as input, no load on V5 or LDO33, LDOIN not connected to VP, VLDOIN = 24V VCC Undervoltage-Lockout Threshold VCCUVLO VCC Undervoltage-Lockout Threshold Hysteresis VCCUVLO_HYST V5 Supply Current I5_IN V5 Undervoltage-Lockout Threshold V5UVLO VL Logic-Level Supply Voltage VL VL Logic-Level Supply Current IL VL Undervoltage Threshold VLUVLO VCC falling MIN TYP MAX UNITS 36 V 1 2.5 mA 7.4 9 V 9 6 LDOIN shorted to V5, external 5V applied to V5, no switching, LDO33 disabled V5 falling 200 mV 3 mA 2.0 V 2.3 All logic inputs at VL or GND VL falling 0.65 0.95 5.5 V 5 FA 1.30 V 36 V 5 mA 5V LDO (V5) LDOIN Input Voltage Range VLDOIN LDOIN Supply Current ILDOIN 7 VLDOIN = 24V, C/Q is configured as an input, no load on V5 or LDO33 2.5 ����������������������������������������������������������������� Maxim Integrated Products 3 MAX14821 IO-Link Device Transceiver DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER V5 Output Voltage Range SYMBOL V5 V5 Load Regulation CONDITIONS No load on V5, 7V P VLDOIN P 36V 1mA < ILOAD < 10mA, VLDOIN = 7V, 0.1FF bypass capacitor on V5 MIN TYP MAX UNITS 4.75 5.00 5.25 V 0.8 % 1mA < ILOAD < 30mA, VLDOIN = 7V, 0.1FF bypass capacitor on V5, 10W–1FF compensation network added to V5 0.8 3.3V LDO (LDO33) LDO33 Output Voltage LDO33 Undervoltage-Lockout Threshold VLDO33 VLDO33UVLO LDO33 Load Regulation No load on LDO33 3.1 3.3 3.5 V VLDO33 falling 2.4 V 1mA < ILOAD < 20mA, VLDOIN = 7V 0.25 % VCC – 1.3 V 24V INTERFACE C/Q Driver Output-Voltage High VOH_C/Q C/Q high-side enabled, IC/Q = -100mA, 9V P VCC P 36V C/Q Driver Output-Voltage Low VOL_C/Q C/Q low-side enabled, IC/Q = +100mA, 9V P VCC P 36V C/Q Driver Source Current Limit IOH_C/Q C/Q high-side enabled, VC/Q < (VCC 3V), 9V P VCC P 36V C/Q Driver Sink Current Limit IOL_C/Q DO Driver Output-Voltage High VCC 1.3 1.4 3 V +100 +140 +190 mA C/Q low-side enabled, VC/Q > 3V, 9V P VCC P 36V -190 -140 -100 mA VOH_DO DO high-side enabled, IDO = +100mA, 9V P VCC P 36V VCC -3 VCC 1.6 DO Driver Output-Voltage Low VOL_DO DO low-side enabled, IDO = -100mA, 9V P VCC P 36V DO Driver Source Current Limit IOH_DO DO Driver Sink Current Limit IOL_DO C/Q, DI Input Voltage Range VIN DO high-side enabled, VDO < (VCC - 3V) DO high-side enabled, VDO > 3V V 1.6 3 V +100 +135 +190 mA -190 -135 -100 mA V For valid RX, LI -1.0 VCC + 1.0 C/Q Input Threshold High VIH_C/Q C/Q driver disabled 10.5 13.0 V C/Q Input Threshold Low VIL_C/Q C/Q driver disabled 8.0 11.5 V VHYS_C/Q C/Q driver disabled 1.0 C/Q Input Hysteresis V DI Input Threshold High VIH_DI 6.8 8 V DI Input Threshold Low VIL_DI 5.2 6.4 V 400 FA DI Input Hysteresis C/Q Weak Pulldown Current VHYS_DI IPDC/Q 1 C/Q driver disabled, VC/Q = (VCC - 1V) 100 V ����������������������������������������������������������������� Maxim Integrated Products 4 MAX14821 IO-Link Device Transceiver DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 40 120 FA 50 300 FA DO Weak Pulldown Current IPDDO DO driver disabled, VCC = 36V, VDO = (VCC - 1V) DI Weak Pulldown Current IPDDI DI load disabled, VCC = 36V, VDI = (VCC - 1V) C/Q Input Capacitance CC/Q C/Q driver disabled 40 pF DO Input Capacitance CDO DO driver disabled 40 pF DI Input Capacitance CDI 20 pF C/Q, DI CURRENT SINK C/Q Load Current ILLM_C/Q DI Load Current ILLM_DI C/Q load enabled (C/QLoad = 1) DI load enabled (DiLoad = 1) 0V P VC/Q P 5V 0 5V P VC/Q 0V P VDI P 5V 5 9V P VDI 6 9 6.6 0 9 9 7.5 9 mA mA LOGIC INPUTS (TXC, TXQ, TXEN, LO, CS, SDI, SCLK) Logic-Input Voltage Low VIL Logic -Input Voltage High VIH Logic-Input Leakage Current Logic-Input Capacitance ILEAK 0.3 x VL Logic input = GND or VL V -1 CIN 0.7 x VL V +1 FA 5 pF LOGIC OUTPUTS (RX, WU, LI, UV, SDO, IRQ) Logic-Output Voltage Low Logic-Output Voltage High SDO Leakage Current VOL IOUT = -5mA VOHRX, VOHWU, VOHLI, IOUT = 5mA (Note 3) VOHSDO, VOHIRQ, ILK_SDO SDO disabled, SDO = GND or VL 0.4 VL 0.6 V V -1 +1 FA THERMAL SHUTDOWN Thermal Warning Threshold Die temperature rising, OTemp bit is set Thermal Warning Threshold Hysteresis Die temperature falling, OTemp bit is cleared Thermal Shutdown Threshold Die temperature rising Thermal Shutdown Hysteresis +115 NC 20 NC +150 NC 20 NC ����������������������������������������������������������������� Maxim Integrated Products 5 MAX14821 IO-Link Device Transceiver AC ELECTRICAL CHARACTERISTICS (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS C/Q, DO, DI INTERFACES Data Rate DR HiSlew = 1 4.8 230.4 HiSlew = 0 4.8 38.4 kbps DRIVER (C/Q, DO) Driver Low-to-High Propagation Delay tPDLH Push-pull or high-side (PNP) configuration, Figure 1 HiSlew = 1 0.5 2 HiSlew = 0 1.6 5 Driver High-to-Low Propagation Delay tPDHL Push-pull or low-side (NPN) configuration, Figure 1 HiSlew = 1 0.5 2 HiSlew = 0 1.6 5 Driver Skew tSKEW |tPDLH - tPDHL| 0.1 2 0.4 1.7 Driver Rise Time tRISE Push-pull or high-side (PNP) configuration, Figure 1 HiSlew = 1 HiSlew = 0 1.5 4 Driver Fall Time tFALL Push-pull or low-side (NPN) configuration, Figure 1 HiSlew = 1 0.4 1.7 HiSlew = 0 1.4 4 Driver Enable Time High tENH Push-pull or high-side (PNP) configuration, Figure 3 HiSlew = 1 0.3 1 HiSlew = 0 0.8 7 Driver Enable Time Low tENL Push-pull or low-side (NPN) configuration, Figure 2 HiSlew = 1 0.3 1 HiSlew = 0 0.9 7 Driver Disable Time High tDISH Push-pull or high-side (PNP) configuration, Figure 2 (Note 4) HiSlew = 1 1.6 3 HiSlew = 0 1.6 3 Driver Disable Time Low tDISL Push-pull or low-side (NPN) configuration, Figure 3 (Note 4) HiSlew = 1 0.1 3 HiSlew = 0 0.1 3 RxFilter = 1 0.2 2 RxFilter = 0 0.4 2 RxFilter = 1 0.3 2 RxFilter = 0 0.5 2 Fs Fs Fs Fs Fs Fs Fs Fs Fs RECEIVER (C/Q, DI) (Figure 4) Receiver Low-to-High Propagation Delay tPRLH Receiver High-to-Low Propagation Delay tPRHL Fs Fs WAKE-UP DETECTION (Figure 5) Wake-Up Input Minimum Pulse Width tWUMIN 30 40 50 Fs Wake-Up Input Maximum Pulse Width tWUMAX 120 140 160 Fs 120 190 260 Fs WU Output Low Time tWUL Valid wake-up condition on C/Q ����������������������������������������������������������������� Maxim Integrated Products 6 MAX14821 IO-Link Device Transceiver AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI TIMING (CS, SCLK, SDI, SDO) (Figure 6) SCLK Clock Period tCH+CL 83.3 ns tCH 41.65 ns SCLK Pulse-Width Low tCL 41.65 ns CS Fall to SCLK Rise Time tCSS 20 ns SCLK Rise to CS Rise Hold Time tCSH 20 ns SDI Hold Time tDH 10 ns SDI Setup Time tDS 10 ns Output Data Propagation Delay tDO 32 ns SDO Rise and Fall Times tFT 20 ns SCLK Pulse-Width High Minimum CS Pulse tCSW 76.8 ns Note 2: All devices are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design. Note 3: UV is an open-drain output. Connect UV to a voltage less than 5.5V through an external pullup resistor. Note 4: Disable time measurements are load dependent. ����������������������������������������������������������������� Maxim Integrated Products 7 MAX14821 IO-Link Device Transceiver TXEN TXC C/Q OR DO MAX14821 TXQ 3.3nF 5kΩ LO GND VL TXEN 0V VL (TXC AND TXQ) OR LO 50% tPDHL 0V tPDLH C/Q OR DO tFALL VCC 90% 50% 10% 0V tRISE Figure 1. C/Q and LO Driver Propagation Delays and Rise/Fall Times VCC 5kΩ TXEN C/Q VL 3.3nF MAX14821 TXC TXQ GND VL TXEN tENL 0V tDISH VCC C/Q 10% 10% 0V Figure 2. C/Q Driver Enable Low and Disable High Timing with External Pullup Resistor ����������������������������������������������������������������� Maxim Integrated Products 8 MAX14821 IO-Link Device Transceiver TXEN C/Q MAX14821 TXC 3.3nF 5kΩ TXQ GND VL TXEN 0V tDISL tENH C/Q VCC 90% 90% 0V Figure 3. C/Q Driver Enable High and Disable Low Timing RX OR LI C/Q OR DI 15pF MAX14821 GND TXEN VCC C/Q OR DI 50% tPRLH 0V tPRHL VL RX OR LI 50% 0V Figure 4. C/Q and DI Receiver Propagation Delays ����������������������������������������������������������������� Maxim Integrated Products 9 MAX14821 IO-Link Device Transceiver TXEN WU TXC AND TXQ MAX14821 C/Q GND TXEN TXC AND TXQ < tWUMIN NO WAKE-UP C/Q tWUMIN < tWU < tWUMAX WU tWUL NOTE: THE MAX14821 RECOGNIZES A WAKE-UP PULSE WHEN C/Q IS SHORTED FROM HIGH-TO-LOW OR FROM LOW-TO-HIGH FOR tWUMIN < tWU < tWUMAX. Figure 5. Wake-Up Detection Timing CS tCSS tCSH tCH tCSH tCL SCLK tDS tDH SDI tDO SDO Figure 6. SPI Timing Diagram ���������������������������������������������������������������� Maxim Integrated Products 10 MAX14821 IO-Link Device Transceiver Typical Operating Characteristics (VCC = 24V, LDOIN = VP, VL = LDO33, C/Q and DO in push-pull configuration, TA = +25NC, unless otherwise noted.) C/Q DRIVER OUTPUT HIGH vs. LOAD CURRENT C/Q DRIVER OUTPUT LOW vs. SINK CURRENT 23 6 5 22 VOL_C/Q (V) TA = -40°C 0 25 50 75 100 125 150 0 175 25 50 75 100 125 LOAD CURRENT (mA) SINK CURRENT (mA) DO DRIVER OUTPUT HIGH vs. LOAD CURRENT DO DRIVER OUTPUT LOW vs. SINK CURRENT TA = +85°C 23 175 150 175 7 MAX14821 toc03 24 150 MAX14821 toc04 0 6 5 22 TA = -40°C 21 VOL_DO (V) VOH_DO (V) TA = -40°C 1 18 TA = +25°C 4 TA = +85°C TA = +25°C 3 TA = -40°C 20 2 19 1 0 18 0 25 50 75 100 125 150 0 175 25 50 75 100 125 LOAD CURRENT (mA) SINK CURRENT (mA) C/Q DRIVER PROPAGATION DELAY vs. TEMPERATURE (HiSlew = 0) C/Q DRIVER PROPAGATION DELAY vs. TEMPERATURE (HiSlew = 1) 0.46 MAX14821 toc05 1.30 1.28 1.26 0.45 0.44 1.24 1.22 tPDHL (µs) tPDHL (µs) TA = +25°C 2 19 1.20 1.18 0.43 0.42 0.41 1.16 0.40 1.14 1.10 TA = +85°C 3 TA = +25°C 20 1.12 4 MAX14821 toc06 VOH_C/Q (V) TA = +85°C 21 MAX14821 toc02 7 MAX14821 toc01 24 0.39 TXEN = VL TXC = TXQ -45 -30 -15 0.38 0 15 30 45 TEMPERATURE (°C) 60 75 90 TXEN = VL TXC = TXQ -45 -30 -15 0 15 30 45 60 75 90 TEMPERATURE (°C) ���������������������������������������������������������������� Maxim Integrated Products 11 MAX14821 IO-Link Device Transceiver Typical Operating Characteristics (continued) (VCC = 24V, LDOIN = VP, VL = LDO33, C/Q and DO in push-pull configuration, TA = +25NC, unless otherwise noted.) C/Q DRIVER OUTPUT SWITCHING (HiSlew = 0) C/Q DRIVER OUTPUT SWITCHING (HiSlew = 1) MAX14821 toc07 MAX14821 toc08 VTXC=TXQ 2V/div Ch1 Ch2 1.430µs 0V Ch1 Ch2 1.330µs VC/Q 5V/div Ch2 RISE 1.583µs VTXC=TXQ 2V/div Ch1 Ch2 357.1ns 0V Ch1 Ch2 335.4ns VC/Q 5V/div Ch2 RISE 343.5ns Ch2 FALL 1.455µs Ch2 FALL 331.7ns 0V 0V 2µs/div 2µs/div RECEIVER PROPAGATION DELAY vs. TEMPERATURE (RxFilter = 0) RECEIVER PROPAGATION DELAY vs. TEMPERATURE (RxFilter = 1) 400 DI TO LI 350 C/Q TO RX 350 300 tPRHL (ns) 450 300 250 200 150 250 200 100 150 50 100 MAX14821 toc10 500 tPRHL (ns) 400 MAX14821 toc09 550 DI TO LI C/Q TO RX 0 -45 -30 -15 0 15 30 45 60 75 -45 -30 -15 90 TEMPERATURE (°C) 0 15 30 WAKE-UP DETECTION 60 75 90 C/Q SHORT-CIRCUIT PROTECTION MAX14821 toc11 MAX14821 toc12 C/Q 10V/div VC/Q 10V/div 0V VWU 2V/div 0V 40µs/div 45 TEMPERATURE (°C) ISOURCE 100mA/div TXEN = VL TXC = TXQ = GND tSHORT = 200µs IRQ 2V/div 40µs ���������������������������������������������������������������� Maxim Integrated Products 12 MAX14821 IO-Link Device Transceiver Typical Operating Characteristics (continued) (VCC = 24V, LDOIN = VP, VL = LDO33, C/Q and DO in push-pull configuration, TA = +25NC, unless otherwise noted.) LDOIN SUPPLY CURRENT vs. LDOIN VOLTAGE C/Q SHORT-CIRCUIT PROTECTION MAX14821 toc13 3.5 C/Q 10V/div 3.0 ILDOIN (mA) ISINK 100mA/div MAX14821 toc14 4.0 2.5 2.0 1.5 VCC = 36V C/Q AND DO DRIVERS ENABLED V5, LDO33 ARE LOADED TXC = TXQ = LO = VL 1.0 TXEN = VL TXQ = TXC = VL tSHORT = 200µs IRQ 2V/div TA = +85°C TA = +25°C TA = -40°C 0.5 0 9 40µs 12 15 18 21 24 27 30 33 36 VLDOIN (V) V5 LOAD REGULATION TA = -40°C TA = +25°C -0.15 -0.20 TA = +85°C -0.25 -0.30 -0.35 -0.40 -0.2 -0.3 TA = +25°C -0.4 -0.5 TA = +85°C -0.6 -0.45 -0.7 -0.50 10 20 30 40 12 10 15 20 25 30 35 40 45 50 LOAD CURRENT (mA) VCC SUPPLY CURRENT vs. C/Q DATA RATE VCC SUPPLY CURRENT vs. VCC VOLTAGE 1.8 MAX14821 toc17 VLDOIN = V5 = 5V TXEN = VL HiSlew = 1 NO LOAD ON C/Q 14 5 LOAD CURRENT (mA) 18 16 0 50 TA = +25°C 1.6 1.4 ICC (mA) 1.2 10 VCC = 36V 8 VCC = 30V 6 4 TA = +85°C 1.0 VLDOIN = 7V C/Q AND DO DRIVERS ENABLED V5, VP UNLOADED C/Q AND DI CURRENT LOADS OFF TXC = TXQ = LO = VL 0.4 2 0.2 0 1 10 100 C/Q DATA RATE (kbps) 1k TA = -40°C 0.8 0.6 VCC = 24V MAX14821 toc18 0 ICC (mA) TA = -40°C -0.1 % VOLTAGE CHANGE % VOLTAGE CHANGE -0.10 MAX14821 toc16 -0.05 LDO33 LOAD REGULATION 0 MAX14821 toc15 0 0 9 12 15 18 21 24 27 30 33 36 VCC VOLTAGE (V) ���������������������������������������������������������������� Maxim Integrated Products 13 MAX14821 IO-Link Device Transceiver Pin/Bump Configurations TOP VIEW (BUMP SIDE DOWN) UV LI LO WU RX TXEN TOP VIEW 18 17 16 15 14 13 12 TXC GND 20 11 TXQ 10 I.C. MAX14821 DO 22 VCC 23 *EP + 1 2 3 4 5 6 LDOIN V5 LDO33 IRQ SCLK CS VP 24 1 2 3 4 5 A VCC LDOIN V5 LDO33 SCLK B C/Q VP IRQ CS SDO C GND GND I.C. SDI VL D DO UV WU TXC TXQ E DI LI LO RX TXEN + DI 19 C/Q 21 MAX14821 9 VL 8 SDI 7 SDO WLP TQFN *CONNECT EXPOSED PAD TO GND. Pin/Bump Descriptions PIN TQFN-EP WLP 1 A2 NAME LDOIN FUNCTION 5V Linear Regulator Input. Bypass LDOIN to GND with a 0.1FF ceramic capacitor. 5V Power-Supply Input and 5V Linear Regulator Output. Bypass V5 to GND with a 0.1FF ceramic capacitor for 10mA load capability. Add the recommended compensation network to increase the source capability to 30mA. See the 5V and 3.3V Linear Regulators section for more information. 2 A3 V5 3 A4 LDO33 4 B3 5 A5 IRQ SCLK Active-Low Interrupt Request Output. IRQ is a push-pull output referenced to VL. SPI Clock Input 6 B4 B5 CS SDO Active-Low SPI Chip-Select Input 7 8 C4 SDI SPI Serial-Data Input 9 C5 VL Logic-Level Supply Input. VL defines the logic levels on all the logic inputs and outputs. Bypass VL to GND with a 0.1FF ceramic capacitor. 10 C3 I.C. Internally Connected. Connect to VL or leave unconnected. 3.3V Linear Regulator Output. Bypass LDO33 to GND with a 1FF ceramic capacitor. SPI Serial-Data Output ���������������������������������������������������������������� Maxim Integrated Products 14 MAX14821 IO-Link Device Transceiver Pin/Bump Descriptions (continued) PIN NAME FUNCTION TQFN-EP WLP 11 D5 TXQ Transmit Level Input. The logic on the C/Q output is the inverse logic level of the signals on the TXC and TXQ inputs. TXQ is ANDed with TXC. Drive TXQ high if not in use. 12 D4 TXC Transmit Communication Input. The logic on the C/Q output is the inverse logic level of the signals on the TXC and TXQ inputs. TXC is ANDed with TXQ. Drive TXC high if not in use. 13 E5 TXEN Transmitter Enable. Drive TXEN high to enable the C/Q transmitter. TXEN is referenced to VL. 14 E4 RX Receiver Output. RX is the inverse logic level of C/Q. RX is always high when the RxDis bit in the CQConfig register is set to 1. 15 D3 WU Active-Low Wake-Up Output. WU is a push-pull output referenced to VL. WU pulses low for 190Fs (typ) when a valid wake-up pulse is detected on the C/Q line. 16 E3 LO 17 E2 LI 18 D2 UV Open-Drain Undervoltage Indicator Output. In case of an undervoltage, the UV open-drain transistor is off. 24V Logic-Level Digital Input Logic Input of the DO Output. LO is the logic input that drives DO. LO is referenced to VL. Logic Output of the 24V DI Logic Input. LI is the inverse logic of DI. LI is referenced to VL. 19 E1 DI 20 C1, C2 GND Ground 21 B1 C/Q SIO/IO-Link Data Input/Output. Drive TXEN high to enable the C/Q driver. The logic on the C/Q output is the inverse logic level of the signals on the TXC and TXQ inputs. RX is the logic inverse of C/Q. The C/Q driver output level can be set by the TXC/TXQ inputs or programmed by the Q bit. The level on C/Q can be read by the RX ouput or the QLvl bit. 22 D1 DO 24V Logic-Level Digital Output. DO is the inverse logic level of the LO input and can be digitally controlled through the DIOConfig register. 23 A1 VCC Power-Supply Input. Bypass VCC to GND with a 1FF ceramic capacitor. 24 B2 VP Protected 24V Supply Output. VP is one diode drop below VCC. VP is reverse-polarity protected and can be used as a 24V protected supply to the sensor or actuator electronics. — — EP Exposed Pad (TQFN Only). Connect EP to GND. ���������������������������������������������������������������� Maxim Integrated Products 15 MAX14821 IO-Link Device Transceiver Detailed Description The MAX14821 is a sensor/actuator transceiver designed for IO-Link device applications supporting all the specified IO-Link data rates. In IO-Link applications, the device acts as the physical layer interface to a microcontroller running the data-link layer protocol. The device contains an additional 24V digital input and an additional 24V digital output. Two internal linear regulators generate common sensor and actuator power requirements: 5V and 3.3V. The device detects IO-Link wake-up conditions on the C/Q line and generates a wake-up signal on the WU output. The C/Q and DO drivers are independently configurable to any one of three driver output types: push-pull, high-side (PNP), or low-side (NPN). The C/Q and DI inputs have selectable current sinks that can be enabled for use in actuators where the master requires a Type 2 load. The device is configured and monitored through an SPI interface. Extensive alarms are available through SPI. 24V Interface The device features an IO-transceiver interface capable of operating with voltages up to 36V. This is the 24V interface and includes the C/Q input/output, the logic-level digital output (DO), and the logic-level digital input (DI). Configurable Drivers The device features selectable push-pull, high-side (PNP), or low-side (NPN) switching drivers at C/Q and DO. Set the C/Q_N/P and C/Q_PP bits in the CQConfig register to select the driver mode for the C/Q driver. When configured as a push-pull output, C/Q switches between VP and ground. Set the C/Q_PP bit to 1 to select pushpull operation at C/Q. Set the C/Q_PP bit to 0 to configure the C/Q output for open-drain operation. The C/Q_N/P bit selects NPN or PNP operation when C/Q is configured as an open-drain output. Set the DoN/P and DoPP bits in the DIOConfig register to select the driver mode for the DO output. When configured as a push-pull output, DO switches between VCC and ground. Set the DoPP bit to 1 for push-pull operation. The DoN/P bit selects NPN or PNP operation when DO is configured as an open-drain output. Set the DoPP bit to 0 to select high-side or low-side operation at DO. C/Q Driver and Receiver The TXEN input enables the C/Q driver. Drive TXEN high to enable the C/Q driver. Drive TXEN low to disable the driver. The C/Q driver is specified to supply up to 100mA DC load current. The HiSlew bit increases the slew rate of the C/Q and DO driver outputs. Set HiSlew to 1 for data rates of 230kbps or higher. Set HiSlew to 0 to reduce both the C/Q and DO driver slew rates to reduce EMI emission and reflections. The C/Q receiver is always on. Disable the RX output through the RxDis bit in the CQConfig register. Set the RxDis bit to 1 to set the RX output high. Set the RxDis bit to 0 for normal receive operation. The C/Q receiver has an analog lowpass filter to reduce high-frequency noise present on the line. Set the RxFilter bit in the CQConfig register to 0 to set the filter corner frequency to 500kHz (typ). Set the RxFilter bit to 1 to set the corner frequency of the filter to 1MHz (typ). Noise filters are present on both the C/Q and DI receivers and are controlled simultaneously by the RxFilter bit. C/Q Fault Detection The device registers a C/QFault condition under either of two conditions: 1) When it detects a short circuit for longer than 160µs (typ). A short condition exists when the C/Q driver’s load current exceeds the 140mA (typ) current limit. 2) When it detects a voltage level error at the C/Q output. A voltage level error occurs when the C/Q driver is configured for open-drain operation (NPN or PNP), the driver is turned off, and the C/Q voltage is not pulled to exceed the C/Q receiver’s threshold levels (< 8V or > 13V) by the external supply. When a C/QFault error occurs, the C/QFault and C/QFaultInt bits are set, IRQ asserts, and the driver is turned off 240µs (typ) after the start of the fault condition. When a short-circuit event occurs on C/Q, the driver enters autoretry mode. In autoretry mode the device periodically checks whether the short is still present and attempts to correct the driver output. Autoretry attempts last for 350µs (typ) and occur every 26ms (typ). ���������������������������������������������������������������� Maxim Integrated Products 16 MAX14821 IO-Link Device Transceiver DO Fault Detection The device registers a DoFault event when a short circuit is present at the DO output for 440Fs. A short condition exists when the load current on the DO driver exceeds the 135mA (typ) DO current limit. When a short-circuit condition is detected, the DO driver enters autoretry mode. In autoretry mode the device periodically checks whether the error is still present. Autoretry attempts last for 440µs (typ) and occur every 26ms (typ). When a DoFault error is detected, the DoFault and DoFaultInt bits are set, IRQ asserts, and the driver is turned off 440µs (typ) after the start of the DO faults. Reverse-Polarity Protection The device is protected against reverse-polarity connections on VCC, C/Q, DO, DI, and GND. Any combination of these pins can be connected to DC voltages up to 40V (max). A short to 40V results in a current flow of less than 500FA. Ensure that the maximum voltage between any of these pins does not exceed 40V. 5V and 3.3V Linear Regulators The device includes two internal current-limited regulators to generate 5V (V5) and 3.3V (LDO33). V5 is specified at 10mA when bypassed with a 0.1µF capacitor to ground. Add the compensation network shown in Figure 7 to draw up to 30mA from V5. LDO33 is specified at 20mA. The input of V5, LDOIN, can be connected to VP, the protected 24V supply output, or to another voltage in the 7V to 36V range. V5 constitutes the supply for the logic block. The 5V LDO can be disabled by connecting LDOIN to V5. Apply an external voltage from 4.75V to 5.25V to V5 when the LDO is disabled. V5 5V 0.1µF 10Ω MAX14821 1µF LDO33 VL Figure 7. V5 Compensation Network 3.3V 1 µF Use the LDO33Dis bit in the Mode register to enable/ disable LDO33. See the Mode Register [R1, R0] = [1,1] section for more information. V5 and LDO33 are not protected against short circuits. Power-Up The C/Q and DO driver outputs and the UV output are high impedance when VCC, V5, VL, and/or LDO33 voltages are below their respective undervoltage thresholds during power-up. UV goes low and the drivers are enabled when all these voltages exceed their respective undervoltage-lockout thresholds. The drivers are automatically disabled if VCC, V5, or VL falls below its threshold. Undervoltage Detection The device monitors VCC, V5, VL, and optionally LDO33 for undervoltage conditions. UV is high impedance when any monitored voltage falls below its UVLO threshold. VCC, V5, and VL undervoltage detection cannot be disabled. When VCC falls below the VCCUVLO threshold, the UV24 and UV24Int bits are set, UV asserts high, and IRQ asserts low. The SPI register contents are unchanged while V5 is present, regardless of the state of VCC and LDO33. The SPI interface is not accessible and IRQ is not available when UV is asserted due to a V5 or VL undervoltage event. When the internal 3.3V LDO regulator voltage (VLDO33) falls below the LDO33 undervoltage-lockout threshold, the UV33Int bit in the Status register is set and IRQ asserts. UV asserts if the UV33En bit in the Mode register is set to 1. The UV output deasserts once the undervoltage condition is removed; however, bits in the Status register and the IRQ output are not cleared until the Status register has been read. Wake-Up Detection The device detects an IO-Link wake-up condition on the C/Q line in push-pull, high-side (PNP), or low-side (NPN) operation modes. A wake-up condition is detected when the C/Q output is shorted for 80Fs (typ). WU pulses low for 190Fs (typ) when the device detects a wake-up pulse on C/Q (Figure 5). Set the WuIntEn bit in the Mode register to set the WuInt bit in the Status register and generate an interrupt on IRQ when a wake-up pulse is detected. WuInt is set and IRQ asserts immediately after C/Q is released when WuIntEn = 1. ���������������������������������������������������������������� Maxim Integrated Products 17 MAX14821 IO-Link Device Transceiver Thermal Protection and Considerations The internal LDOs and drivers can generate more power than the package for the device can safely dissipate. Ensure that the driver LDO loading is less than the package can dissipate. Total power dissipation for the device is calculated using the following equation: PTOTAL = PC/Q + PDO + P5 + PLDO33 + PQ + PCLCQ + PCLDI Calculate the quiescent power dissipation in the device using the following equation: PQ = 5mA × VCC(max) If the current sinks are enabled, calculate their associated power dissipation as: PCLCQ = 7mA × VC/Q(max) PCLDI = 7mA × VDI(max) where PC/Q is the power generated in the C/Q driver, PDO is the power dissipated by the DO driver, P5 and PLDO33 are the power generated by the LDOs, PQ is the quiescent power generated by the device, and PCLCQ and PCLDI are the power generated in the C/Q and DI current sinks. Overtemperature Warning Bits in the Status and Mode registers are set when the temperature of the device exceeds +115NC (typ). The OTempInt bit in the Status register is set and IRQ asserts when the OTemp bit in the Mode register is set. Read the Status register to clear the OTempInt bit and IRQ. Ensure that the total power dissipation is less than the limits listed in the Absolute Maximum Ratings section. The OTemp bit is cleared when the die temperature falls to +95NC. Use the following to calculate the power dissipation (in mW) due to the C/Q driver: The device continues to operate normally unless the die temperature reaches the +150NC thermal shutdown threshold, when the device enters thermal shutdown. PC/Q = [IC/Q(max)] × [0.5 + 7 × IC/Q(max)] Calculate the internal power dissipation of the DO driver using the following equation: PDO = [IDO(max)] × [0.5 + 7 × IDO(max)] Calculate the power dissipation in the 5V LDO, V5, using the following equation: P5 = (VLDOIN - V5) × I5 where I5 includes the ILDO33 current sourced from LDO33. Calculate the power dissipated in the 3.3V LDO, LDO33, using the following equation: PLDO33 = 1.7V × ILDO33 Thermal Shutdown When the die temperature rises above the +150°C (typ) thermal shutdown threshold, the C/Q and DO drivers and the C/Q and DI current loads are automatically turned off. The internal 3.3V and 5V LDOs remain on during thermal shutdown, if enabled. If the internal or external V5 supply remains on during thermal shutdown (which is always true in case of the internal V5 regulator), the register contents are maintained and SPI communication is available. When the die temperature falls below the thermal shutdown threshold plus hysteresis, the C/Q and DO drivers and C/Q and DI current sinks turn on automatically. ���������������������������������������������������������������� Maxim Integrated Products 18 MAX14821 IO-Link Device Transceiver Register Functionality The device has four 8-bit-wide registers for configuration and monitoring (Table 1). Table 1. Register Summary REGISTER R1 R0 D7 D6 D5 D4 D3 D2 D1 D0 Status 0 0 WuInt DoFaultInt DiLvl C/QFaultInt UV33Int UV24Int OTempInt CQConfig 0 1 RxFilter HiSlew C/Q_N/P QLvl C/Q_PP C/QDEn Q RxDis C/QLoad DIOConfig 1 0 DoInv DoAv DoN/P DoPP DoEn DoBit LiDis DiLoad Mode 1 1 RST WuIntEn DoFault C/QFault UV24 OTemp UV33En LDO33Dis R1/R0 = Register address. Status Register [R1, R0] = [0,0] Bit Bit Name Read/Write POR State Reset Upon Read D7 D6 D5 D4 D3 D2 D1 D0 WuInt DoFaultInt DiLvl C/QFaultInt UV33Int UV24Int OTempInt R R R QLvl R R R R R 0 0 X X 0 0 0 0 Yes Yes No No Yes Yes Yes Yes X = Unknown. These bits are dependent on the DI logic and C/Q inputs. The Status register reflects the logic levels of C/Q and DI and shows the source of interrupts that cause an IRQ hardware interrupt. The IRQ interrupt is asserted when an alarm condition (OTemp, UV33Int, UV24, C/QFault, DoFault, WuInt) is detected. All bits in the Status register are read-only. The interrupt bits return to the default state after the Status register is read. If a C/Q or DO fault condition persists, the associated interrupt bits are immediately set after the Status register is read. BIT NAME DESCRIPTION D7 Wulnt Wake-Up Interrupt Request. WuInt is set when an IO-Link wake-up request pulse is detected on C/Q and the WuIntEn bit in the Mode register is set. IRQ asserts when WuInt is set to 1. Read the Status register to clear the WuInt bit and deassert IRQ. D6 DoFaultInt DO Fault Interrupt. DoFaultInt interrupt bit and DoFault bit (in the Mode register) are set when a fault condition occurs on the DO driver output. The device registers a fault condition when a short circuit or voltage fault is detected on DO (see the DO Fault Detection section for more information). IRQ asserts when DoFaultInt is 1. Read the Status register to clear the DoFaultInt bit and deassert IRQ. D5 DiLvl DI Logic Level. The DiLvl bit mirrors the current logic level at the DI input. It is the inverse of the LI output and is always active regardless of the state of the LiDis bit (Table 2). DiLvl does not affect IRQ. DiLvl is not changed when the Status register is read. ���������������������������������������������������������������� Maxim Integrated Products 19 MAX14821 IO-Link Device Transceiver BIT NAME DESCRIPTION D4 QLvl C/Q Logic Level. The QLvl bit is the inverse of the logic level at C/Q. QLvl is 1 when the C/Q input level is low (< 8V) and is 0 when the C/Q logic level is high (> 13V) (Table 3). QLvl remains active when the C/Q receiver is disabled (RxDis = 1). QLvl does not affect IRQ. QLvl is not changed when the Status register is read. D3 C/QFaultInt C/Q Fault Interrupt. The C/QFaultInt interrupt bit and C/QFault bit (in the Mode register) are set when a short circuit or voltage fault occurs on the C/Q driver output (see the C/Q Fault Detection section for more information). IRQ asserts when C/QFault is 1. Read the Status register to clear the C/QFaultInt bit and deassert IRQ. D2 UV33Int Internal 3.3V LDO (LDO33) Undervoltage Warning. Both the UV33Int interrupt bit and the UV33En bit (in the Mode register) are set when VLDO33 falls below the 2.4V LDO33 undervoltage threshold. If UV33En is set in the Mode register, IRQ asserts low when the UV33Int bit is 1. Read the Status register to clear the UV33Int bit and deassert IRQ. Set the UV33En bit to 1 in the Mode register to enable undervoltage monitoring for UV33Int. When enabled, UV asserts high when the UV33Int bit is 1. UV deasserts when VLDO33 rises above the LDO33 undervoltage threshold. D1 UV24Int VCC Undervoltage Interrupt. The UV24Int interrupt bit and the UV24 bit (in the Mode register) are set when the VCC voltage falls below the 7.4V undervoltage threshold. IRQ asserts low when the UV24Int bit is 1. Read the Status register to clear the UV24Int bit and deassert IRQ. VCC undervoltage detection cannot be disabled. D0 OTempInt Overtemperature Warning. The OTempInt interrupt bit and the OTemp bit (in the Mode register) are set when a high-temperature condition is detected by the device. OTemp is set when the temperature of the die exceeds +115NC (typ). OTempInt is set and IRQ asserts when the OTemp bit is 1. The OTempInt bit is cleared and IRQ deasserts when the Status register is read. Once cleared, OTempInt is not reset if the die temperature remains above the thermal warning threshold and does not fall below +95°C. Table 2. DiLvl and LI Output Table 3. QLvl and RX Output VDI (V) DiLvl BIT LI OUTPUT VC/Q (V) QLvl BIT RX OUTPUT < 5.2 0 High <8 1 High >8 1 Low >13 0 Low ���������������������������������������������������������������� Maxim Integrated Products 20 MAX14821 IO-Link Device Transceiver CQConfig Register [R1, R0] = [0,1] Bit D7 D6 D5 D4 D3 D2 D1 D0 RxFilter HiSlew C/Q_N/P C/Q_PP C/QDEn Q RxDis C/QLoad Read/Write R/W R/W R/W R/W R/W R/W R/W R/W POR State 0 0 0 0 0 0 0 0 Bit Name Use the CQConfig register to control the C/Q receiver and driver parameters. All bits in the CQConfig register are read-write and are set to 0 at power-up. BIT NAME D7 RxFilter DESCRIPTION C/Q and DI Receiver Filter Control. The C/Q and DI receivers have analog lowpass filters to reduce high-frequency noise on the receiver inputs. Set the RxFilter bit to 0 to set the filter corner frequency to 500kHz. Set the RxFilter bit to 1 to set the filter corner frequency to 1MHz (this setting is used for highspeed COM3 operation). Noise filters on C/Q and DI are controlled simultaneously by the RxFilter bit. D6 HiSlew Slew-Rate Control. The HiSlew bit increases the slew rate for the C/Q and DO drivers and is used for high-speed COM3 (230kbps) data rates. Set HiSlew to 0 for COM1 and COM2 operation. D5 C/Q_N/P C/Q Driver NPN/PNP Mode. The C/Q_N/P bit selects between low-side (NPN) and high-side (PNP) modes when the C/Q driver is configured as an opendrain output (C/Q_PP = 0). Set C/Q_N/P to 1 to configure the driver for low-side (NPN) operation. Set C/Q_N/P to 0 for high-side (PNP) operation. D4 C/Q_PP C/Q Driver Push-Pull Operation. Set C/Q_PP to 1 to enable push-pull operation on the C/Q driver. The C/Q output is open-drain when C/Q_PP is 0. D3 C/QDEn C/Q Driver Enable/Disable. Set the C/QDEn bit to 1 to enable the C/Q driver. Set C/QDEn to 0 for hardware (TXEN) control. See Table 4. D2 Q C/Q Driver Output Logic. The Q bit can be used to program the C/Q output driver through software. The C/Q driver must be enabled and TXC = TXQ must be high to control the C/Q driver through the Q bit (Figure 8). C/Q has the same logic polarity as the Q bit. Set the Q bit to 0 to control the C/Q driver with TXC and TXQ. The C/Q driver output state depends on the C/Q_PP and C/Q_N/P bits as shown in Table 5. Note that Table 5 assumes that the C/Q driver is enabled (TXEN = VL or C/QDEn = 1). D1 RxDis D0 C/QLoad C/Q Receiver Enable/Disable. Set the RxDis bit to 1 to disable the C/Q receiver. The RX output is high when RxDis is 1. C/Q Current Sink Enable. Set the C/QLoad bit to 1 to enable the internal current sink at C/Q. ���������������������������������������������������������������� Maxim Integrated Products 21 MAX14821 IO-Link Device Transceiver Table 4. C/QDEn and TXEN C/Q Driver Control C/QDEn TXEN C/Q DRIVER 0 Low Disabled X High Enabled 1 X Enabled X = Don’t care. TXQ TXC C/Q Q Figure 8. Equivalent C/Q Logic Table 5. C/Q Driver Output State TXC AND TXQ (SEE NOTE) Q C/Q_PP C/Q_N/P C/Q CONFIGURATION High 1 0 0 PNP, open drain On, C/Q is high High 0 0 0 PNP, open drain Off, C/Q is high impedance High 1 0 1 NPN, open drain Off, C/Q is high impedance High 0 0 1 NPN, open drain On, C/Q is low High 1 1 X Push-pull High High 0 1 X Push-pull Low C/Q STATE Note: TXC and TXQ = VL. X = Don’t care. ���������������������������������������������������������������� Maxim Integrated Products 22 MAX14821 IO-Link Device Transceiver DIOConfig Register [R1, R0] = [1,0] Bit D7 D6 D5 D4 D3 D2 D1 D0 DoInv DoAv DoN/P DoPP DoEn DoBit LiDis DiLoad Read/Write R/W R/W R/W R/W R/W R/W R/W R/W POR State 0 0 0 0 0 0 0 0 Bit Name Use the DIOConfig register to control the DI and DO interfaces. All bits in the DIOConfig register are read-write and are set to 0 at power-up. BIT NAME DESCRIPTION D7 DoInv DO Output Polarity. Set the DoInv bit to 1 to invert the logic of the DO output. This bit also works in conjunction with the DoAv (Table 6). DO tracks the TXC and TXQ inputs with the opposite polarity when both the DoAv and DoInv bits are set. D6 DoAv DO Antivalent Operation. Set the DoAv bit to 1 to enable antivalent output operation on DO. DO tracks the TXC and TXQ inputs (and the Q bit) when DoAv is 1 (Table 6). D5 DoN/P DO Driver NPN/PNP Operation. The DoN/P bit selects between lowside (NPN) and high-side (PNP) modes when the DO driver is configured as an open-drain output (DoPP = 0). Set DoN/P to 1 to configure the driver for low-side (NPN) operation. Set DoN/P to 0 for high-side (PNP) operation. D4 DoPP DO Driver Push-Pull Operation. Set the DoPP bit to 1 to configure the DO driver output for push-pull operation. DO is an open-drain output when DoPP is 0. D3 DoEn DO Driver Enable/Disable. Set the DoEn bit to 1 to enable the DO driver. The DO driver is high impedance with a weak pulldown when DoEn is 0. D2 DoBit DO Driver Output Logic. The DoBit bit can be used to program the DO output driver through software. Drive LO high to activate DoBit programming (Figure 9). The DO output state is given in Table 7. Note that Table 7 assumes that the DoInv bit is 0. D1 LiDis LI Output Enable/Disable. Set the LiDis bit to 1 to disable the LI output. The LI output is low when LiDis is 1. D0 DiLoad The LO input and the DoBit are ignored when the DoAv bit is 1. DI Current Sink Enable. Set the DiLoad bit to 1 to enable the internal current sink at the DI input. ���������������������������������������������������������������� Maxim Integrated Products 23 MAX14821 IO-Link Device Transceiver Table 6. DoAv and DoInv Operation DoAv DoInv TXC AND TXQ (NOTE 1) LO (NOTE 1) DO (NOTE 2) C/Q (NOTE 2) 0 0 0 0 Low Low High High Low High Low 0 High 0 High Low High Low 0 0 High High Low Low 0 1 Low Low Low High 0 1 Low High High High 0 1 High Low Low Low 0 1 High High High Low 1 0 Low Low Low High 1 0 Low High Low High 1 0 High Low High Low 1 0 High High High Low 1 1 Low Low High High 1 1 Low High High High 1 1 High Low Low Low 1 1 High High Low Low Note 1: Low is when VTXC, VTXQ, OR VLO = 0V; high is when VTXC, VTXQ, or VLO = VL. Note 2: Low is when C/Q or DO < 8V; high is when C/Q or DO >13V. Table 7. DO Output Programmed by DoBit LO DoBit DoPP DoN/P DO CONFIGURATION High 0 1 X Push-pull DO STATE Low High 1 1 X Push-pull High High 0 0 0 PNP Off, DO is high impedance High 1 0 0 PNP On, DO is high High 0 0 1 NPN On, DO is low High 1 0 1 NPN Off, DO is high impedance Low X X X See Table 6 See Table 6 X = Don’t care. LO DoBit DoInv DO Figure 9. Equivalent DO Logic ���������������������������������������������������������������� Maxim Integrated Products 24 MAX14821 IO-Link Device Transceiver Mode Register [R1, R0] = [1,1] Bit D7 D6 D5 D4 D3 D2 D1 D0 Bit Name RST WuIntEn DoFault C/QFault UV24 OTemp UV33En LDO33Dis Read/Write R/W R/W R R R R R R/W POR State 0 0 0 0 0 0 0 0 Use the Mode register to reset the MAX14821 and manage the 3.3V LDO. The Mode register has bits that represent the current status of fault conditions. When writing to the Mode register, the contents of the fault indication bits (bits 2 to 5) do not change. BIT NAME DESCRIPTION D7 RST Register Reset. Set RST to 1 to reset all registers to their default power-up state. Then set RST to 0 for normal operation. The Status register is cleared and IRQ deasserts (if asserted) when RST = 1. Interrupts are not generated while RST = 1. D6 WuIntEn Wake-Up Interrupt Enable. Set WuIntEn to 1 to enable wake-up interrupt generation. When WuIntEn is set, the WuInt bit in the Status register is set and IRQ asserts when a valid wake-up condition is detected. The C/Q driver must be enabled for wake-up detection. The state of WuIntEn does not affect the WU output. See the Wake-Up Detection section for more information. D5 DoFault DO Fault Status. The DoFault bit is set when a short circuit or voltage fault occurs at the DO driver output (see the DO Fault Detection section for more information). The DoFault and DoFaultInt bits are both set when a fault occurs on DO. DoFault is cleared when the fault is removed. D4 C/QFault C/Q Fault Status. The C/QFault bit is set when a short circuit or voltage fault occurs at the C/Q driver output (see the C/Q Fault Detection section for more information). The C/QFault and C/QFaultInt bits are both set when a fault occurs on C/Q. C/QFault is cleared when the fault is removed. D3 UV24 VCC Undervoltage Condition. Both the UV24 and the UV24Int bits are set when VCC falls below VCCUVLO. UV24 is cleared when VCC rises above the VCC threshold. V5 must be present for VCC undervoltage monitoring. D2 OTemp Temperature Warning. The OTemp bit is set when a high-temperature condition occurs on the device. Both the OTempInt interrupt in the Status register and the OTemp bit are set when the junction temperature of the die rises to above +115NC (typ). The OTemp bit is cleared when the junction temperature falls below +95NC (typ). D1 UV33En LDO33 UV Enable. Set the UV33En bit to 1 to assert the UV output when LDO33 voltage falls below the 2.4V (typ) undervoltage-lockout threshold. The UV33En bit does not affect the UV33Int bit in the Status register; IRQ asserts when VLDO33 falls below VLDO33UVLO regardless of the state of UV33En. D0 LDO33Dis LDO33 Enable/Disable. Set LDO33Dis to 1 to disable the 3.3V linear regulator (LDO33). ���������������������������������������������������������������� Maxim Integrated Products 25 MAX14821 IO-Link Device Transceiver SPI Interface for the device is 12MHz. The SPI interface complies with clock polarity CPOL = 0 and clock phase CPHA = 0 (see Figure 10 and Figure 11). The device communicates through an SPI-compatible 4-wire serial interface. The interface has three inputs— clock (SCLK), chip select (CS), and data in (SDI)—and one output, data out (SDO). The maximum SPI clock rate The SPI interface is not available when V5 or VL are not present. CS SCLK SDI W 0 0 0 0 R1 0 R0 D7 D6 D5 D4 D3 D2 D1 D0 R_ = REGISTER ADDRESS D_ = DATA BIT = CLOCK EDGE WHEN LOGIC IS LATCHED Figure 10. SPI Write Cycle CS SCLK SDI X R 0 0 0 0 0 R1 R0 X D7 SDO D6 D5 D4 D3 D2 D1 D0 R_ = REGISTER ADDRESS D_ = DATA BIT = CLOCK EDGE WHEN LOGIC IS LATCHED = CLOCK EDGE AT WHICH LOGIC IS WRITTEN Figure 11. SPI Read Cycle ���������������������������������������������������������������� Maxim Integrated Products 26 MAX14821 IO-Link Device Transceiver Applications Information UART Interfacing MICROCONTROLLER The logic levels of the microcontroller interface I/Os (TXC, TXQ, TXEN, and RX) are defined by VL. GPO TXQ TX TXC RTS TXEN RX Transient Protection MAX14821 RX Figure 12. UART Interface 1/2 SDC36C 1μF LDOIN VP 0.8Ω VCC 1/2 SDC36C MAX14821 The device can be interfaced to microcontrollers where the on-board UART TX output cannot be programmed as a logic output (GPO). In this case, connect the TX output of the UART to the TXC input for IO-Link communication and connect a separate GPO output on the microcontroller to TXQ for standard IO (SIO) mode operation (Figure 12). As the TXQ and TXC inputs are internally logically ANDed, the unused input (TXC or TXQ) must be held high while the other is in operation. 1μF DO 1/2 SDC36C C/Q DI SDC36C GND Figure 13. MAX14821 Operating Circuit with TVS Protection Inductive load switching, surges, and bursts create high transient voltages. C/Q, DO, and DI should be protected against high overvoltage and undervoltage transients. Positive voltage transients on C/Q, DO, and DI must be limited to +55V relative to GND and negative voltage transients must be limited to -55V (relative to VCC) on DO and C/Q and to -55V (relative to GND) on DI. Figure 12 shows suitable protection using TVS diodes to meet both the IEC 61000-4-2 ESD and IEC 61000-4-5 surge testing. Other protection schemes may also be suitable. To protect against large transients at VCC, insert a lowpass filter on VCC (see Figure 13 and the Typical Operating Circuit). External Power The device is powered by VCC and the 5V regulator, V5. VL is a reference voltage input to set the logic levels of the microcontroller interface. The logic and SPI interface are operational when V5 and VL are present even if VCC is not present. The VP output provides a reverse-polarity-protected voltage one diode drop below VCC and can be used for supplying external circuitry, like power supplies. Connect LDOIN to V5 to power the V5 input with an external supply (Figure 14). This configuration disables operation of the internal 5V regulator and reduces power consumption. ���������������������������������������������������������������� Maxim Integrated Products 27 MAX14821 IO-Link Device Transceiver EN IN MAX15062 5V STEP-DOWN REGULATOR LX GND FB 3.3V 1μF 0.1μF 10kΩ VCC GPIO2 UV VL TXQ LDO33 V5 LDOIN VP 0.8Ω VCC 1μF SPI MICROCONTROLLER GND IRQ WU RX RX TX TXC RTS TXEN GPIO1 LO DO MAX14821 L+ 1 2 C/Q DI 4 3 L- GND Figure 14. Use an External Supply to Power the MAX14821 Ordering Information PART TEMP RANGE PIN-PACKAGE MAX14821ETG+ -40°C to +85°C 24 TQFN-EP* MAX14821EWA+** -40°C to +85°C 25 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. **Future product—contact factory for availability. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 TQFN-EP T2444+4 21-0139 90-0022 25 WLP W252A2+1 21-0191 Application Note 1891 ���������������������������������������������������������������� Maxim Integrated Products 28 MAX14821 IO-Link Device Transceiver Revision History REVISION NUMBER REVISION DATE 0 8/11 Initial release 12/11 Corrected data line direction for Typical Operating Circuit, removed TOC 14 and added new TOC 17, corrected DO Fault Detection section, corrected Thermal Shutdown section, corrected IEC number in Transient Protection section, corrected Figures 11 and 14 1 DESCRIPTION PAGES CHANGED — 1, 13, 17, 18, 26, 28 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2012 Maxim Integrated Products 29 Maxim is a registered trademark of Maxim Integrated Products, Inc.