JBT6K49-AS TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic JBT6K49-AS Power supply IC for TFT LCD Panels The JBT6K49-AS chip is an integrated circuit (IC) for generating the supply voltages necessary for a TFT LCD panel driver. When used in combination with the T6K47 source driver and the T6K48 gate driver for TFT LCD panels, the JBT6K49-AS enables the module set to operate with low power consumption. A high-speed CMOS process is employed to achieve low power consumption and high-speed operation for the JBT6K49-AS. Features · Built-in circuits : DC-DC converters and oscillation circuit for DC-DC converters High-precision regulator Binary buffer for γ-correction Level shifter circuit for Vcom · Supply voltage (VDD) : 2.7 V to 3.3 V · Supply voltage (VBAT) : 2.7 V to 4.2 V · Low power consumption · Operating temperature : −20°C to 75°C · CMOS process · Recommended drivers : T6K47 source driver for TFT LCD T6K48 gate driver for TFT LCD · Package : Product Name Description JBT6K49-AS (PI) Gold bump chip 1 2002-03-12 JBT6K49-AS Block Diagram VSIN VSOUT1 VBAT FSEL1 FSEL2 CKSEL EXTCK 2 CA1+ CA1CA2+ CA2- CB1+ CB1CB2+ CB2CB3+ CB3CB4+ CB4CB5+ CB5- Test Circuit REF Circuit 22 DC-DC Converter 2 TEST SDA SCK FUSE** VREF VREFIN VSOUT2 VTOUT VTIN CC1+ CC1- VDD /STB /RST /EXP Oscillation Circuit DC-DC Converter 1 Vcom DC-DC Converter 3 Gamma Power Supply GND (2) VBOUT VEE GND (1) TEG** 2 COMOUT VLC /VLC POL 2002-03-12 JBT6K49-AS PAD Specifications Characteristics Chip Size Size Unit 4600 ´ 3050 mm (1) -2300, 1525 (2) -2300, -1525 (3) 2300, -1525 (4) 2300, 1525 Chip End Coordinates mm Bump Pitch 140 mm Bump Height 15 mm Characteristics Number of Pins TEG pin 9 FUSE pin 22 Note 1: The TEG1 to TEG9 pins and the FUSE** pins are reserved for testing by Toshiba. They are not intended to for use in the operation of the JBT6K49-AS. They must always be left open during normal operation. Alignment Mark Specifications Non-designed area X and Y coordinates 90 mm AI 100 mm 90 mm 90 mm 100 mm 90 mm 3 2002-03-12 JBT6K49-AS CC1GND2 GND2 GND2 CC1+ VTIN VCC VCC VTOUT CB5CB5+ CB4CB4+ CB3CB3+ CB2CB2+ CB1CB1+ DUMMY CA2CA2+ CA1CA1+ VSOUT1 VSIN VBAT PAD Layout VBOUT VBOUT POL DUMMY CKSEL EXTCK FSEL1 FSEL2 VEE 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 JBT6K49-AS Chip size: 4.60 ´ 3.05 mm FUSE11 FUSE12 FUSE1G FUSE13 FUSE14 FUSE21 FUSE22 FUSE2G FUSE23 FUSE24 FUSE31 FUSE32 FUSE33 FUSE3G FUSE34 FUSE35 FUSE36 FUSE41 FUSE42 FUSE4G FUSE43 FUSE44 DUMMY DUMMY DUMMY DUMMY DUMMY /STB TEST EXP SDA SCK /RST VDD VDD TEG9 TEG8 TEG7 TEG6 DUMMY GND1 VSOUT2 VREFIN VREF /VLC VLC COMOUT TEG5 TEG4 TEG3 TEG2 TEG1 Input/Output Pins Unit: mm 140 58 58 82 82 58 58 82 58 58 58 98 40 58 98 140 58 58 4 2002-03-12 JBT6K49-AS [Unit: mm] Pad Coordinates No. Pin Name XYCoordinate Coordinate No. Pin Name XYCoordinate Coordinate No. Pin Name XYCoordinate Coordinate 1 FUSE11 -1890 -1340 44 VSOUT2 2015 160 87 VBOUT -2115 860 2 FUSE12 -1750 -1340 45 GND1 2115 300 88 POL -2115 720 3 FUSE1G -1610 -1340 46 GND1 2015 300 89 DUMMY -2115 580 4 FUSE13 -1470 -1340 47 DUMMY 2115 440 90 CKSEL -2115 440 5 FUSE14 -1330 -1340 48 TEG6 2115 580 91 EXTCK -2115 300 6 FUSE21 -1190 -1340 49 TEG7 2115 720 92 FSEL1 -2115 160 7 FUSE22 -1050 -1340 50 TEG8 2115 860 93 FSEL2 -2115 20 8 FUSE2G -910 -1340 51 TEG9 2115 1000 94 VEE -2115 -120 9 FUSE23 -770 -1340 52 VBAT 1750 1340 95 /STB -2115 -260 10 FUSE24 -630 -1340 53 VBAT 1750 1240 96 TEST -2115 -400 11 FUSE31 -490 -1340 54 VSIN 1610 1340 97 EXP -2115 -540 12 FUSE32 -350 -1340 55 VSIN 1610 1240 98 SDA -2115 -680 13 FUSE33 -210 -1340 56 VSOUT1 1470 1340 99 SCK -2115 -820 14 FUSE3G -70 -1340 57 VSOUT1 1470 1240 100 /RST -2115 -960 15 FUSE34 70 -1340 58 CA1+ 1330 1340 101 VDD -2115 -1100 16 FUSE35 210 -1340 59 CA1- 1190 1340 102 VDD -2115 -1240 17 FUSE36 350 -1340 60 CA2+ 1050 1340 103 A/M_1 2110 1335 18 FUSE41 490 -1340 61 CA2- 910 1340 104 A/M_2 -2110 1335 19 FUSE42 630 -1340 62 DUMMY 770 1340 20 FUSE4G 770 -1340 63 CB1+ 630 1340 21 FUSE43 910 -1340 64 CB1- 490 1340 22 FUSE44 1050 -1340 65 CB2+ 350 1340 23 DUMMY 1190 -1340 66 CB2- 210 1340 24 DUMMY 1330 -1340 67 CB3+ 70 1340 25 DUMMY 1470 -1340 68 CB3- -70 1340 26 DUMMY 1610 -1340 69 CB4+ -210 1340 27 DUMMY 1750 -1340 70 CB4- -350 1340 28 TEG1 2115 -1240 71 CB5+ -490 1340 29 TEG2 2115 -1100 72 CB5- -630 1340 30 TEG3 2115 -960 73 VTOUT -770 1340 31 TEG4 2115 -820 74 VTOUT -770 1240 32 TEG5 2115 -680 75 VCC -910 1340 33 COMOUT 2115 -540 76 VCC -910 1240 34 COMOUT 2015 -540 77 VCC -1050 1340 35 VLC 2115 -400 78 VTIN -1190 1340 36 VLC 2015 -400 79 VTIN -1190 1240 37 /VLC 2115 -260 80 CC1+ -1330 1340 38 /VLC 2015 -260 81 GND2 -1470 1340 39 VREF 2115 -120 82 GND2 -1610 1340 40 VREF 2015 -120 83 GND2 -1610 1240 41 VREFIN 2115 20 84 GND2 -1750 1340 42 VREFIN 2015 20 85 CC1- -1890 1340 43 VSOUT2 2115 160 86 VBOUT -2115 1000 5 2002-03-12 JBT6K49-AS Pin Function Description (1) Pin Name I/O CKSEL I EXTCK I/O FSEL1 FSEL2 I Function External clock pulse selection pin CKSEL = “L”・・・the built-in oscillator is used. CKSEL = “H”・・・an external clock pulse is accepted. It must be input on the EXTCK pin. External clock pulse input pin Input an external clock pulse on this pin if External Clock Pulse Supply Mode has been selected. If the built-in oscillator is selected (Self-Oscillation Mode), this pin must be fixed Low. Oscillation frequency switching input pins These pins can be used to select the oscillation frequency for the DC-DC converters. FSEL2 FSEL1 DC-DC converter clock frequency (typ.) 0 0 3.5 kHz 0 1 5.0 kHz 1 0 7.5 kHz 1 1 10.0 kHz CA1+､CA1CA2+､CA2- I/O DC-DC converter 1 capacitor connection pins These pins can be connected to voltage booster capacitors. The recommended capacitance for the DC-DC converter capacitors is 1 mF. VSOUT1 VSOUT2 O DC-DC converter 1 output pins These pins output the supply voltage (AVDD) for the T6K47. They are electrically connected via an aluminum wire inside the IC chip. Normally a capacitor with a capacitance of approximately 10 mF is connected across the VSS pins in order to maintain the voltage level. VSIN I DC-DC converter 1 power supply input pin This is the power supply feedback pin for DC-DC converter 1. It is normally connected to the VSOUT1 pin. VREFIN I Reference voltage input pin An operational-amplifier output feedback voltage is input on this pin to generate the VS voltage. It should normally be connected to the VREF pin. VREF O Reference power supply output pin This is an operational-amplifier output pin which generates the VS voltage. It is normally connected to a capacitor with a capacitance of 0.1 mF to 0.47 mF. The capacitance should be adjusted as necessary to suit the conditions in which the device is used. 6 2002-03-12 JBT6K49-AS Pin Function Description (2) Pin Name I/O Function CB1+、CB1CB2+、CB2CB3+、CB3CB4+、CB4CB5+、CB5- I/O DC-DC converter 2 capacitor connection pins Connect these pins to external voltage booster capacitors in order to generate negative voltages for the T6K48. The recommended capacitance for the capacitors is 1 mF. VTOUT O DC-DC converter 2 output pin This pin outputs the supply high-level voltage (+13 V) used for the T6K48. VTIN I DC-DC converter 3 supply voltage input pin The voltage for DC-DC converter 3 used to generate a voltage on the VBOUT pin is input on this pin. It must be connected to the VTOUT pin. CC1+、CC1- I/O DC-DC converter 3 capacitor connection pins Connect these pins to an external voltage booster capacitor in order to generate negative voltages for the T6K48. The recommended capacitance for the DC-DC converter capacitor is 1 mF. VBOUT O DC-DC converter 3 output pin This pin outputs the supply low-level voltage (-13 V) used for the T6K48. /STB I Standby signal input pin The chip stays in standby state while /STB = L. Enabling the /STB pin halts all the built-in circuits. /RST I Reset signal input pin A reset signal must be input on this pin after the power is turned on. POL I Alternating signal input pin This POL signal inverts the phase of the COMOUT, VLC and /VLC signals. See Fig. 2 for an explanation of how to invert the phase. VLC /VLC ¾ g-correction power supply voltage pin This pin outputs a voltage whose phase is under the control of the POL signal. The following table lists the output voltages and their phases. POL VLC BVLC H VSO 0V L 0V VSO COMOUT O Common signal output pin This pin outputs, in phase with the POL signal, a signal whose level has been converted to the board level necessary for the LCD. EXP I DC-DC converter ON/OFF switching pin This pin is used to turn the DC-DC converters ON/OFF. Normally it should be connected to GND. 7 2002-03-12 JBT6K49-AS Pin Function Description (3) Pin Name I/O Function VBAT ¾ Analog circuit supply voltage VDD ¾ Logic circuit supply voltage VCC ¾ DC-DC converter 2 supply voltage VEE ¾ DC-DC converter 3 supply voltage GND1、GND2 ¾ Ground pins Note 2: The GND1 and GND2 pins serve different circuit blocks. Connect both pins to ground. Pin Function Description (4) Pin Name I/O Function TEST I Test mode switching pin This is an enable pin for Toshiba Test Mode. Normally it should be grounded. SCK I Test mode clock pin A clock pulse for serial data transfer used in Toshiba Test Mode is input on this pin. Normally it should be grounded. SDA I Test mode data pin Serial data used in Toshiba Test Mode is input on this pin. Normally it should be grounded. FUSE** I Toshiba test pin (1) This pin is a dedicated pin used only in Toshiba Test Mode. Normally it should be left open. FUSE*G I Toshiba test pin (2) This pin is a dedicated pin used only in Toshiba Test Mode. Normally it should be left open. TEG** I Toshiba test pin (3) This pin is a dedicated pin used only in Toshiba Test Mode. Normally it should be left open. 8 2002-03-12 JBT6K49-AS Description of Functions and Operation DC-DC converter The JBT6K49-AS generates an analog supply voltage for the source driver (T6K47) and an LCD-driving voltage for the gate driver (T6K48). The DC-DC converter consists of three circuit blocks which output +4.8 V, +13.0 V and -13.0 V. The ways in which the DC-DC converter can be used are shown below. DC-DC converter (1): Generates +4.8 V. DC-DC converter (1): Generates +13.0 V. CA1 + CA1 - CB1 + CB1 - CA2 + CA2 - CB5 + CB5 - DC-DC converter (1): Generates -13.0 V. CC1 + CC1 - Note 2: Connect a voltage boosting kick capacitor or capacitors to each circuit block. Normally the capacitance of the kick capacitor should be 1.0 mF. Connect a 10 mF capacitor across the boosted-voltage output pin and the VSS pin of DC-DC converter (1), since the voltage generated in the DC-DC converter is unstable. In addition, connect a 1 mF capacitor across the boosted-voltage output pin and the VSS pin of DC-DC converter (1). Oscillation Circuit The JBT6K49-AS generates the clock pulse used by the DC-DC converter. The FSEL1 and FSEL2 pins can be used to select the clock oscillation frequency. The following table lists the correspondence between the pin settings and the selected frequency. FSEL2 FSEL1 Oscillation Frequency (initial value) 0 0 3.5 kHz 0 1 5.0 kHz 1 0 7.0 kHz 1 1 10.0 kHz Note 3: The relationship of the oscillation frequency and the oscillation resistance depends on assembly and measuring conditions. Therefore, select the oscillation resistance after enough evaluating. 9 2002-03-12 JBT6K49-AS g-Correction Reference Voltage The +4.8 V generated by DC-DC converter (1) is used to generate g-correction reference voltages used by the source driver (T6K47). The voltages generated serve as the maximum and minimum g-correction voltages. These two voltage levels are switched by the signal input on the POL pin, allowing the g-correction voltage circuit to be configured easily. Fig.1 is an example of a g-correction voltage circuit. /VLC V0 V1 Source driver V2 JBT6K49-AS V3 T6K47 V4 VLC V5 Fig.1 Example of a C-correction voltage circuit The following table lists the voltages output from the VLC and /VLC pins and the corresponding levels on the POL pin. POL VLC /VLC COMOUT 0 0 VSO 0 1 VSO 0 VSO Power-on The JBT6K49-AS incorporates a trimming circuit designed to increase the precision of the LCD-driving output voltage. After the power is turned on, the trimming circuit is reset on the leading edge of the signal input on the reset pin. Use the following /RST pin processing sequence after power-on. VDD/VBAT /RST 1 ms < =t t /STB 10 2002-03-12 JBT6K49-AS Absolute Maximum Ratings (unless otherwise specified, VSS = 0 V and Ta = 25°C) Characteristics Symbol Supply Voltage (1) Rating Unit VDD -0.3 to 6.0 V Supply Voltage (2) (Note 5) VBAT -0.3 to 6.5 V Supply Voltage (3) (Note 5) VCC -0.3 to 20 V Supply Voltage (4) VEE -20 to 0.3 V Input Voltage VIN -0.3 to VDD + 0.3 V 0 to 6.0 V Output Voltage VOUT Operating Temperature Topr -20 to 75 °C Storage Temperature Tstg -55 to 125 °C Note 4: The voltages listed in the table are referenced to ground (0 V). Note 5: VBAT < = VCC Electrical Characteristics DC Characteristics (1) (unless otherwise specified, VDD = 2.7 V to 3.3 V, VBAT = 2.7 V to 4.2 V and Ta = -20°C to 75°C) Symbol Test Circuit Test Condition Min Typ. Max Unit Related Pins Operating Supply Voltage (1) VDD ¾ ¾ 2.7 ¾ 3.3 V VDD Operating Supply Voltage (2) VBAT ¾ ¾ 2.7 ¾ 4.2 V VBAT VIL ¾ ¾ 0 ¾ 0.2 VDD V CKSEL, POL, /STB, EXTCK, FSEL1/2, /RST Characteristics Input Voltage VIH ¾ ¾ 0.8 VDD ¾ VDD Input Leakage Current IIL ¾ Vinp = VDD to GND -1.0 ¾ 1.0 mA CKSEL, POL, /STB, EXTCK, FSEL1/2, /RST External Clock Frequency fex ¾ 2 ¾ 8 kHz EXTCK External Clock Pulse Duty Ratio fduty ¾ 45 50 55 % EXTCK External Clock Pulse Rise/Fall Time tr/tf ¾ ¾ ¾ 50 ns EXTCK CKSEL = “H” DC Characteristics (2) (unless otherwise specified, VDD = 2.7 V to 3.3 V, VBAT = 2.7 V to 4.2 V and Ta = -20°C to 75°C, For typical ratings the conditions are: VDD = 3.0V, VBAT = 3.0V and Ta = 25°C) Symbol Test Circuit IDDSTB ¾ Dynamic Drain (1) IDD1 ¾ Dynamic Drain (2) IDD2 ¾ Dynamic Drain (3) IBAT ¾ Characteristics Static Drain Test Condition Min Typ. Max Unit Related Pins /STB = “L” ¾ 1 5 mA GND With no load ¾ 0.2 2 mA VDD ¾ 0.2 2 mA VDD ¾ 350 500 mA VBAT With typical load Fosc = 3.5 kHz 11 2002-03-12 JBT6K49-AS DC Characteristics (3) (unless otherwise specified, VDD = 2.7 V to 3.3 V, VBAT = 2.7 V to 4.2 V and Ta = -20°C to 75°C) Characteristics DC-DC Converter Characteristic (1) Symbol Test Circuit VSO1 ¾ Test Condition Iload = 42 mA Ta = 25°C Min Typ. Max 4.75 4.80 4.85 4.75 4.80 4.90 4.70 ¾ ¾ ¾ 13.0 13.7 Iload = 42 mA VSO2 ¾ Ta = -20°C Unit Related Pins V VSOUT V VTOUT V VBOUT Ta = 75°C DC-DC Converter Characteristic (2) DC-DC Converter Characteristic (3) VSO3 ¾ Iload = 2.5mA VTO1 ¾ Iload = 0 mA VTO2 ¾ Iload = 100 mA 12.3 ¾ ¾ VBO1 ¾ Iload = 0 mA -13.7 -13.0 ¾ VBO2 ¾ Iload = 100 mA ¾ ¾ -12.3 DC Characteristics (4) (unless otherwise specified, VDD = 2.7 V to 3.3 V, VBAT = 2.7 V to 4.2 V and Ta = -20°C to 75°C) Characteristics g-Output Voltage Characteristic (1) g-Output Voltage Characteristic (2) COM Output Voltage Characteristic Symbol Test Circuit VLC1H ¾ VLC2H ¾ VLC1L ¾ Test Condition POL = “H” POL = “L” Min Typ. Max Unit Related Pins VSO1 - 0.05 VSO1 VSO1 + 0.05 V VLC - 0.05 0 0.05 V /VLC - 0.05 0 0.05 V VLC VSO1 - 0.05 VSO1 VSO1 + 0.05 V /VLC VLC2L ¾ VcomL ¾ POL = “L” - 0.05 0 0.05 V VcomH ¾ POL = “H” VSO1 - 0.05 VSO1 VSO1 + 0.05 V 12 COMOUT 2002-03-12 VDD /RST /STB POL 1 mF 1 mF 61 VDD 60 VDD 59 /RST 58 SCK 57 SDA 56 EXP 55 TEST 54 /STB 53 VEE 52 FSEL2 51 FSEL1 50 EXTCK 49 CKSEL 48 DUMMY 47 POL 46 VBOUT 45 VBOUT CC1- 1 mF 1 mF 1 mF 1 mF 1 mF 1 mF 1 mF CB1+ FUSE42 CB1FUSE41 CB2+ FUSE36 CB2FUSE35 CB3+ FUSE34 T6K49 DUMMY FUSE4G CB4FUSE32 CB5+ FUSE31 CB5FUSE24 VTOUT FUSE23 VCC FUSE2G VCC FUSE22 VTIN FUSE21 CC1+ FUSE14 GND2 FUSE13 GND2 FUSE1G 13 1 mF TEG1 1 TEG2 2 TEG3 3 TEG4 4 TEG5 5 COMOUT 6 VLC 7 /VLC 8 VREF 9 VREFIN 10 VSOUT2 11 GND1 12 DUMMY 13 TEG6 14 TEG7 15 TEG8 16 1 mF 10 mF 1 mF TEG9 17 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 FUSE11 Connect to T6K48 (-13.0 V) 1 mF CA2FUSE43 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1SS357 1 mF 1SS357 CA2+ FUSE44 Connect to T6K48 (13.0 V) CA1DUMMY Internal CR oscillator used (5 kHz) Using DC-DC converter CA1+ DUMMY Application circuit GND2 FUSE12 VSOUT1 DUMMY CB4+ FUSE33 VSIN DUMMY CB3FUSE3G VBAT DUMMY LCD ヘ Connect to T6K47 1 mF GND Connect to T6K47 (4.8 V) VBAT 2002-03-12 JBT6K49-AS JBT6K49-AS RESTRICTIONS ON PRODUCT USE 000707EBE · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. · Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 14 2002-03-12