19-4112; Rev 0; 5/08 KIT ATION EVALU E L B A IL AVA Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection The MAX5099 offers a dual-output, high-switching-frequency DC-DC buck converter with an integrated highside switch. The MAX5099 integrates two low-side MOSFET drivers to allow each converter to drive an external synchronous-rectifier MOSFET. Converter 1 delivers up to 2A output current, and converter 2 can deliver up to 1A of output current. The MAX5099 integrates load-dump protection circuitry that is capable of handling load-dump transients up to 80V for automotive applications. The load-dump protection circuit utilizes an internal charge pump to drive the gate of an external n-channel MOSFET. When an overvoltage or loaddump condition occurs, the series protection MOSFET absorbs the high voltage transient to prevent damage to lower voltage components. The DC-DC converter operates over a wide 4.5V to 19V operating voltage range. The MAX5099 operates 180° out-of-phase with an adjustable switching frequency to minimize external components while allowing the ability to make trade-offs between the size, efficiency, and cost. The high switching frequency also allows these devices to operate outside the AM band for automotive applications. These regulators can be protected against high voltage transients such as a load-dump condition by using the integrated overvoltage controller. This device utilizes voltage-mode control for stable operation and external compensation, so that the loop gain is tailored to optimize component selection and transient response. The MAX5099 has a maximum duty cycle of 92.5% and is synchronized to an external clock fed at the SYNC input. Additional features include internal digital soft-start, individual enable for each DC-DC regulator (EN1 and EN2), open-drain power-good outputs (PGOOD1 and PGOOD2), and shutdown input (ON/OFF). Other features of the MAX5099 include overvoltage protection and short-circuit (hiccup current limit) and thermal protection. The MAX5099 is available in a thermally enhanced, exposed pad 5mm x 5mm, 32-pin TQFN package and operates over the automotive -40°C to +125°C temperature range. Features ♦ Wide 4.5V to 5.5V or 5.2V to 19V Input Voltage Range with 80V Load-Dump Protection ♦ Dual-Output DC-DC Converter with Integrated Power MOSFETs ♦ Adjustable Outputs from 0.8V to 0.9VIN ♦ Output Current Capability Up to 2A and 1A ♦ Switching Frequency Programmable from 200kHz to 2.2MHz ♦ Synchronization Input (SYNC) ♦ Individual Converter Enable Input and PowerGood Output ♦ Low-IQ (7µA) Standby Current (ON/OFF) ♦ Internal Digital Soft-Start and Soft-Stop ♦ Short-Circuit Protection on Outputs and Maximum Duty-Cycle Limit ♦ Overvoltage Protection on Outputs with Auto Restart ♦ Thermal Shutdown ♦ Thermally Enhanced 32-Pin TQFN Package Dissipates Up to 2.7W at +70°C Ordering Information PART TEMP RANGE MAX5099ATJ+ -40°C to +125°C PIN-PACKAGE 32 TQFN-EP* +Denotes a lead-free package. *EP = Exposed pad. Applications Automotive AM/FM Radio Power Supply Pin Configuration appears at end of data sheet. Automotive Instrument Cluster Display ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5099 General Description MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection ABSOLUTE MAXIMUM RATINGS V+ to SGND............................................................-0.3V to +25V V+ to IN_HIGH...........................................................-19V to +6V IN_HIGH to SGND ..................................................-0.3V to +19V IN_HIGH Maximum Input Current .......................................60mA BYPASS to SGND..................................................-0.3V to +2.5V GATE to V+.............................................................-0.3V to +12V GATE to SGND .......................................................-0.3V to +36V SGND to PGND .....................................................-0.3V to +0.3V VL to SGND ..................-0.3V to the Lower of +6V or (V+ + 0.3V) VDRV to SGND .........................................................-0.3V to +6V BST1/VDD1, BST2/VDD2, DRAIN_, PGOOD_ to SGND ..............................................-0.3V to +30V ON/OFF to SGND ...............................-0.3V to (IN_HIGH + 0.3V) BST1/VDD1 to SOURCE1, BST2/VDD2 to SOURCE2......................................-0.3V to +6V SOURCE_ to SGND................................................-0.6V to +25V EN_ to SGND............................................................-0.3V to +6V OSC, FSEL_1, COMP_, SYNC, FB_ to SGND..............................................-0.3V to (VL + 0.3V) DL_ to PGND ...........................................-0.3V to (VDRV + 0.3V) SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms VL, BYPASS to SGND Short Circuit ................... Continuous, Internally Limited Continuous Power Dissipation (TA = +70°C) 32-Pin TQFN-EP (derate 34.5mW/°C above +70°C)..2759mW Package Junction-to-Ambient Thermal Resistance (θJA) (Note 1).............................29.0°C/W Package Junction-to-Case Thermal Resistance (θJC) (Note 1) ..............................1.7°C/W Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range ............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) ................................+300°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specifications. For detailed information on package thermal considerations refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22μF (low ESR), CVL = 4.7μF (ceramic), CV+ = 1μF (low ESR), CIN_HIGH = 1μF (ceramic), RIN_HIGH = 3.9kΩ, ROSC = 10kΩ, TJ = -40°C to +125°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SYSTEM SPECIFICATIONS Input Voltage Range V+ V+ Operating Supply Current IQ V+ Standby Supply Current Efficiency IV+STBY η V+ = IN_HIGH 5.2 19 VL = V+ = IN_HIGH, Figure 6 (Note 3) 4.5 5.5 V VL unloaded, no switching, VFB_ = 1V 4.2 6.0 mA VEN_ = 0V, PGOOD_ unconnected, V+ = VIN_HIGH = 14V 0.75 1.1 mA VOUT1 = 5V at 1.5A, VOUT2 = 3.3V at 0.75A, fSW = 300kHz V+ = VL = 5.2V 86 V+ = 12V 85 V+ = 16V 85 % OVERVOLTAGE PROTECTOR IN_HIGH Clamp Voltage IN_HIGH IN_HIGH Clamp Load Regulation ISINK = 10mA 19 20 1mA < ISINK < 50mA 160 21 V mV IN_HIGH Supply Current IIN_HIGH VEN_ = VPGOOD_ = VGATE = 0V, VIN_HIGH = VON/OFF = 14V 270 600 μA IN_HIGH Standby Supply Current IIN_HIGHSTBY VON/OFF = 0V, VPGOOD_ = V+ = unconnected, VIN_HIGH = 14V 7 9 μA 1.85 2.50 V V+ to IN_HIGH Overvoltage Clamp 2 VOV VOV = V+ - VIN_HIGH, IGATE = -1mA 1.20 _______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection (VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22μF (low ESR), CVL = 4.7μF (ceramic), CV+ = 1μF (low ESR), CIN_HIGH = 1μF (ceramic), RIN_HIGH = 3.9kΩ, ROSC = 10kΩ, TJ = -40°C to +125°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL IN_HIGH Startup Voltage IN_HIGH UVLO GATE Charge Current IGATE_CH GATE Output Voltage VGATE VIN_HIGH GATE Turn-Off Pulldown Current IGATE_PD TYP MAX Rising, ON/OFF = IN_HIGH, GATE rising CONDITIONS MIN 3.6 4.1 Falling, ON/OFF = IN_HIGH, GATE falling 3.45 VIN_HIGH = VON/OFF = 14V, VGATE = V+ = 0V 20 45 80 V+ = VIN_HIGH = VON/OFF = 4.5V, IGATE = 1μA 4.0 5.3 7.5 UNITS V μA V V+ = VIN_HIGH = VON/OFF = 14V, IGATE = 1μA 9 VIN_HIGH = 14V, VON/OFF = 0V, V+ = 0V, VGATE = 5V 3.6 mA STARTUP/VL REGULATOR VL Undervoltage-Lockout Trip Level UVLO VL falling 3.9 VL Undervoltage-Lockout Hysteresis VL Output Voltage VL LDO Dropout Voltage 4.3 180 VL VL LDO Short-Circuit Current 4.1 IVL_SHORT VLDO ISOURCE_ = 0 to 40mA, 5.5V ≤ V+ ≤ 19V 5.0 5.2 V mV 5.5 V V+ = VIN_HIGH = 5.2V 130 mA ISOURCE_ = 40mA, V+ = VIN_HIGH = 4.5V 300 550 2.00 2.02 V 2 5 mV mV BYPASS OUTPUT BYPASS Voltage VBYPASS IBYPASS = 0μA BYPASS Load Regulation ΔVBYPASS 0 < IBYPASS < 100μA (sourcing) 1.98 SOFT-START/SOFT-STOP Digital Ramp Period SoftStart/Soft-Stop Internal 6-bit DAC Soft-Start/Soft-Stop Steps 2048 fSW Clock Cycles 64 Steps VOLTAGE-ERROR AMPLIFIER FB_ Input Bias Current FB_ Input-Voltage Set Point FB_ to COMP_ Transconductance IFB_ VFB_ 250 -40°C ≤ TA ≤ +85°C 0.783 -40°C ≤ TA ≤ +125°C 0.785 1.4 gM 0.8 0.809 0.814 2.4 3.4 nA V mS INTERNAL MOSFETS On-Resistance High-Side MOSFET Converter 1 RON1 ISWITCH = 100mA, BST1/VDD1 to VSOURCE1 = 5.2V 195 ISWITCH = 100mA, BST1/VDD1 to VSOURCE1 = 4.5V 208 mΩ 355 _______________________________________________________________________________________ 3 MAX5099 ELECTRICAL CHARACTERISTICS (continued) MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection ELECTRICAL CHARACTERISTICS (continued) (VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22μF (low ESR), CVL = 4.7μF (ceramic), CV+ = 1μF (low ESR), CIN_HIGH = 1μF (ceramic), RIN_HIGH = 3.9kΩ, ROSC = 10kΩ, TJ = -40°C to +125°C, unless otherwise noted.) (Note 2) PARAMETER On-Resistance High-Side MOSFET Converter 2 SYMBOL RON2 CONDITIONS MIN TYP ISWITCH = 100mA, BST2/VDD2 to VSOURCE2 = 5.2V 280 ISWITCH = 100mA, BST2/VDD2 to VSOURCE2 = 4.5V 300 MAX UNITS mΩ 520 Minimum Converter 1 Output Current IOUT1 VOUT1 = 5V, V+ = 12V (Note 4) 2 A Minimum Converter 2 Output Current IOUT2 VOUT2 = 3.3V, V+ = 12V (Note 4) 1 A Converter 1/Converter 2 MOSFET DRAIN_ Leakage Current ILK12 VEN1 = VEN2 = 0V, VDS = 19V, VDRAIN_ = 19V, VSOURCE_ = 0V Internal Weak Low-Side Switch On-Resistance RONLSSW_ 20 ILSSW = 30mA μA Ω 22 INTERNAL SWITCH CURRENT LIMIT Internal Switch Current-Limit Converter 1 ICL1 V+ = VIN_HIGH = 5.2V, VL = VDRV = VBST_/VDD_ = 5.2V 2.8 3.45 4.3 A Internal Switch Current-Limit Converter 2 ICL2 V+ = VIN_HIGH = 5.2V, VL = VDRV = VBST_/VDD_= 5.2V 1.75 2.10 2.60 A 90 92 100 % SWITCHING FREQUENCY PWM Maximum Duty Cycle DMAX Switching Frequency Range fSW Switching Frequency fSW Switching Frequency Accuracy SYNC Frequency Range SYNC High Threshold fSYNC SYNC = SGND, fSW = 1.25MHz 200 ROSC = 6.81kΩ, each converter 1.7 1.9 5.6kΩ < ROSC < 10kΩ, 1% 5 10kΩ < ROSC < 62.5kΩ, 1% 7 Each converter switching frequency is half of the SYNC input frequency, FSEL_1 = VL (see the Setting the Switching Frequency section) VSYNCH 400 2200 kHz 2.1 MHz % 4400 2 kHz V SYNC Low Threshold VSYNCL 0.8 V SYNC Input Leakage ISYNC_LEAK 2 μA SYNC Input Minimum Pulse Width Sync to Source 1 Phase Delay 4 tSYNCIN SYNCPHASE ROSC = 62.5kΩ 100 ns 90 Degrees _______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection (VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22μF (low ESR), CVL = 4.7μF (ceramic), CV+ = 1μF (low ESR), CIN_HIGH = 1μF (ceramic), RIN_HIGH = 3.9kΩ, ROSC = 10kΩ, TJ = -40°C to +125°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERNAL DL_ DRIVERS RDS(ON) DL_ Sink RONDLN RDS(ON) DL_ Source Break-Before-Make Time RONDLP Ω 1 ISINK = 200mA ISOURCE = 200mA 1.8 Ω 50 ns FSEL_1 FSEL_1 Input High Threshold VIH FSEL_1 Input Low Threshold VIL 0.8 V IFSEL_1_LEAK 2 μA FSEL_1 Input Leakage 2 V ON/OFF ON/OFF Input High Threshold ON/OFF Input Low Threshold ON/OFF Input Leakage Current VIH 2 V VIL ION/OFF_LEAK VON/OFF = 5V 0.8 V 0.35 2 μA 2.0 2.1 EN_ INPUTS EN_ Input High Threshold VIH EN_ Input Hysteresis VEN_HYS EN_ Input Leakage Current IEN_LEAK EN_ rising 1.9 0.5 -1 V V +1 μA 95 % VFB_ 0.4 V 2 μA POWER-GOOD OUTPUT (PGOOD1, PGOOD2) PGOOD_ Threshold VTPGOOD_ Falling PGOOD_ Output Voltage VPGOOD_ ISINK = 3mA PGOOD_ Output Leakage Current ILKPGOOD_ 90 92.5 V+ = VL = VIN_HIGH = VEN_ = 5.2V, VPGOOD_ = 23V, VFB_ = 1V OUTPUT OVERVOLTAGE PROTECTION FB_ OVP Threshold Rising VOVP_R FB_ OVP Threshold Falling VOVP_F 107 114 112.5 121 % VFB % VFB THERMAL PROTECTION Thermal Shutdown TSHDN Thermal Hysteresis THYST Rising +165 °C 20 °C Note 2: 100% tested at TA = +25°C and TA = +125°C. Specifications at TA = -40°C are guaranteed by design and not production tested. Note 3: Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to IN_HIGH and VL for 5V operation. Note 4: Output current is limited by the power dissipation of the package; see the Power Dissipation section in the Applications Information section. _______________________________________________________________________________________ 5 MAX5099 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.) OUTPUT2 EFFICIENCY vs. LOAD CURRENT VIN = 14V 50 40 VIN = 8V 20 60 40 VOUT = 5V fSW = 1.85MHz 30 40 30 VOUT = 3.3V fSW = 1.85MHz VOUT = 5V fSW = 300kHz L1 = 18μH 10 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT2 EFFICIENCY vs. LOAD CURRENT OUTPUT1 VOLTAGE vs. LOAD CURRENT OUTPUT2 VOLTAGE vs. LOAD CURRENT VIN = 14V 50 VIN = 8V 40 VIN = 5.5V 20 VOUT = 3.3V fSW = 300kHz L2 = 27μH VIN = 4.5V VIN = 14V VIN = 8V VIN = 16V 3.29 OUTPUT2 VOLTAGE (V) OUTPUT1 VOLTAGE (V) VIN = 16V 60 4.98 3.30 MAX5099 toc05 5.00 MAX5099 toc04 70 4.96 4.94 4.92 0.5 0.6 0.7 0.8 0.9 1.0 VIN = 8V 3.27 3.26 3.25 VOUT = 3.3V fSW = 1.85MHz 0.2 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 LOAD CURRENT (A) VL OUTPUT VOLTAGE vs. CONVERTER SWITCHING FREQUENCY EACH CONVERTER SWITCHING FREQUENCY vs. ROSC EACH CONVERTER SWITCHING FREQUENCY vs. TEMPERATURE VIN = 5.5V VIN = 8V VIN = 19V 4.8 4.6 VIN = 5V 4.4 FSEL_1 = VL, FSEL_1 = GND, CONVERTER 1, CONVERTER 2 1 10 FSEL_1 = VL SWITCHING FREQUENCY (MHz) 5.0 10 SWITCHING FREQUENCY (MHz) BOTH CONVERTERS SWITCHING FSEL_1 = VL MAX5099 toc08 LOAD CURRENT (A) MAX5099 toc07 LOAD CURRENT (A) 1.85MHz 1.25MHz 0.6MHz 0.3MHz CONVERTER 1 VIN = 4.5V 4.0 0.1 0.1 400 700 1000 1300 1600 1900 CONVERTER SWITCHING FREQUENCY (kHz) 2200 2.2MHz 1.0 1 4.2 6 VIN = 14V VIN = 16V VIN = 4.5V 3.23 4.90 0.4 VIN = 5.5V 3.28 3.24 VOUT = 5V fSW = 1.85MHz 0 0.3 VIN = 8V 50 LOAD CURRENT (A) 80 0.2 VIN = 16V LOAD CURRENT (A) 90 10 VIN = 14V 60 LOAD CURRENT (A) 100 30 70 20 VIN = 4.5V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT2 EFFICIENCY (%) VIN = 5.5V 10 0 5.2 VIN = 8V 20 10 5.4 VIN = 16V VIN = 14V 80 MAX5099 toc06 30 70 50 90 MAX5099 toc09 VIN = 16V 80 OUTPUT1 EFFICIENCY (%) 70 60 90 OUTPUT2 EFFICIENCY (%) 80 100 MAX5099 toc02 90 OUTPUT1 EFFICIENCY (%) 100 MAX5099 toc01 100 OUTPUT1 EFFICIENCY vs. LOAD CURRENT MAX5099 toc03 OUTPUT1 EFFICIENCY vs. LOAD CURRENT VL OUTPUT VOLTAGE (V) MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection 0 20 40 ROSC (kΩ) 60 80 -40 -5 30 65 TEMPERATURE (°C) _______________________________________________________________________________________ 100 135 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection CONVERTER 1 LOAD-TRANSIENT RESPONSE LINE-TRANSIENT RESPONSE (BUCK CONVERTER) MAX5099 toc11 MAX5099 toc10 0V VIN 5V/div VOUT1 = 5.0V AC-COUPLED 200mV/div 0V VOUT1 = 5.0V/1.5A AC-COUPLED 200mV/div IOUT1 1A/div VOUT2 = 3.3V/0.75A AC-COUPLED 200mV/div 0A 100μs/div 1ms/div CONVERTER 2 LOAD-TRANSIENT RESPONSE SOFT-START/SOFT-STOP FROM EN1 MAX5099 toc13 MAX5099 toc12 fSW = 1.85MHz EN1 5V/div 0V VOUT2 = 3.3V AC-COUPLED 200mV/div VOUT1 = 5V/2A 5V/div 0V PGOOD1 5V/div 0V IOUT2 500mA/div 0A 100μs/div 1ms/div SOFT-START FROM ON/OFF OUT-OF-PHASE OPERATION (FSEL_1 = VL) MAX5099 toc15 MAX5099 toc14 ON/OFF 5V/div 0V VL = EN1 = EN2 5V/div GATE 10V/div V+ 10V/div 0V 0V VOUT1 = 5V/2A 5V/div 0V 2ms/div SOURCE1 10V/div 0V SOURCE2 10V/div 0V DL1 10V/div DL2 10V/div 0V 0V 200ns/div _______________________________________________________________________________________ 7 MAX5099 Typical Operating Characteristics (continued) (V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.) Typical Operating Characteristics (continued) (V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.) OUT-OF-PHASE OPERATION (FSEL_1 = SGND) EXTERNAL SYNCHRONIZATION (FSEL_1 = VL) MAX5099 toc16 MAX5099 toc17 SYNC 5V/div 0V SOURCE1 10V/div 0V SOURCE1 10V/div 0V SOURCE2 10V/div 0V SOURCE2 10V/div 0V DL1 10V/div DL2 10V/div 0V 0V 200ns/div 200ns/div EXTERNAL SYNCHRONIZATION (FSEL_1 = SGND ) OVP BEHAVIOR MAX5099 toc18 MAX5099 toc19 SYNC 5V/div 0V 0V SOURCE1 10V/div 0V 0V GATE 10V/div VOUT2 10V/div VOUT1 10V/div PGOOD2 10V/div 0V 0V 0V 200ns/div 1ms/div FB_ VOLTAGE vs. TEMPERATURE BYPASS VOLTAGE vs. TEMPERATURE 0.820 0.810 0.805 0.800 0.795 VL = V+ = VIN_HIGH = 5.5V 2.006 BYPASS VOLTAGE (V) 0.815 2.008 MAX5099 toc21 VL = V+ = VIN_HIGH = 5.5V 2.004 2.002 2.000 1.998 1.996 1.994 0.790 1.992 0.785 1.990 -40 -5 30 65 TEMPERATURE (°C) 8 2.010 MAX5099 toc20 0.825 100 135 V+ 10V/div EXTERNAL OVERVOLTAGE REMOVED SOURCE2 10V/div 0V FB_ VOLTAGE (V) MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection -40 -5 30 65 100 TEMPERATURE (°C) _______________________________________________________________________________________ 135 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection BYPASS VOLTAGE vs. BYPASS CURRENT SOURCE1, ISOURCE1, DL1, IIDL1 TA = +85°C TA = +125°C BYPASS VOLTAGE (V) 1.998 TA = +135°C MAX5099 toc22 MAX5099 toc23 2.000 SOURCE1 10V/div 0V 1.996 DL1 10V/div OV TA = -40°C 1.994 TA = +25°C ISOURCE1 1A/div 1.992 0A 1.990 0 10 20 30 40 50 60 70 80 90 100 200ns/div BYPASS CURRENT (μA) V+ SWITCHING SUPPLY CURRENT vs. SWITCHING FREQUENCY 80 60 TA = +25°C 40 20 V+ = IN_HIGH = ON/OFF EN1 = EN2 = SGND 3 fSW = 1.85MHz 2 1 TA = -40°C fSW = 300kHz 0 0 680 1060 1440 1820 2200 -50 0 50 100 TEMPERATURE (°C) IN_HIGH SHUTDOWN CURRENT vs. TEMPERATURE IN_HIGH STANDBY CURRENT vs. TEMPERATURE ON/OFF = SGND IN_HIGH = 16V 16 IN_HIGH = 14V 12 IN_HIGH = 8V 8 4 ON/OFF = IN_HIGH EN1 = EN2 = SGND 145 IN_HIGH STANDBY CURRENT (μA) 20 135 125 150 MAX5099 toc27 SWITCHING FREQUENCY (kHz) MAX5099 toc26 300 IN_HIGH SHUTDOWN CURRENT (μA) MAX5099 toc25 TA = +135°C 4 V+ STANDBY SUPPLY CURRENT (mA) V+ = IN_HIGH = ON/OFF MAX5099 toc24 V+ SWITCHING SUPPLY CURRENT (mA) 100 V+ STANDBY SUPPLY CURRENT vs. TEMPERATURE IN_HIGH = 16V 115 IN_HIGH = 14V 105 IN_HIGH = 8V 95 85 75 0 -50 0 50 TEMPERATURE (°C) 100 150 -50 0 50 100 150 TEMPERATURE (°C) _______________________________________________________________________________________ 9 MAX5099 Typical Operating Characteristics (continued) (V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.) Typical Operating Characteristics (continued) (V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.) IN_HIGH CLAMP VOLTAGE vs. CLAMP CURRENT TA = +125°C 20.2 TA = +85°C TA = +25°C 20.1 TA = -40°C 20.0 19.9 5 V+ TO IN_HIGH CLAMP VOLTAGE (V) MAX5099 toc28 IN_HIGH CLAMP VOLTAGE (V) TA = +135°C MAX5099 toc29 V+ TO IN_HIGH CLAMP VOLTAGE vs. GATE SINK CURRENT 20.3 TA = +135°C TA = +125°C 4 3 TA = +85°C 2 TA = +25°C TA = -40°C 1 0 0 10 20 30 50 40 0 2 4 6 8 CLAMP CURRENT (mA) GATE SINK CURRENT (mA) (VGATE - V) vs. VIN_HIGH SYSTEM TURN-ON FROM BATTERY 10 MAX5099 toc31 MAX5099 toc30 10 8 (VGATE - V) (V) MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection TA = +135°C VIN 10V/div IN_HIGH 10V/div GATE 10V/div 0V TA = +125°C 0V 6 TA = +85°C TA = +25°C 4 0V TA = -40°C 2 V+ 10V/div 0V VL 10V/div 0V ON/OFF = IN_HIGH 0 5.0 8.5 12.0 15.5 19.0 10ms/div VIN_HIGH (V) SYSTEM LOAD DUMP SYSTEM TURN-OFF FROM BATTERY MAX5099 toc33 MAX5099 toc32 VIN 50V/div VIN 10V/div IN_HIGH 10V/div 0V 0V GATE 10V/div V+ 10V/div VL 10V/div 0V 0V 0V 10ms/div 10 IN_HIGH 10V/div 0V GATE 10V/div 0V V+ 10V/div 0V VOUT1 AC-COUPLED 100mV/div 0V 0V 100ms/div ______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection PIN NAME FUNCTION 1, 32 SOURCE2 Converter 2 Internal MOSFET Source Connection. For buck converter operation, connect SOURCE2 to the switched side of the inductor. For boost operation, connect SOURCE2 to PGND (Figure 5). 2, 3 DRAIN2 Converter 2 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a highside switch and connect DRAIN2 to the DC-DC converters supply input rail. For boost converter operation, use the MOSFET as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 5). 4 PGOOD2 Converter Open-Drain Power-Good Output. PGOOD2 goes low when converter 2’s output falls below 92.5% of its set regulation voltage. Use PGOOD2 and EN1 to sequence the converters. 5 EN2 Converter 2 Active-High Enable Input. Connect to VL for always-on operation. 6 FB2 Converter 2 Feedback Input. Connect FB2 to a resistive divider between converter 2’s output and SGND to adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-divider from BYPASS to regulator 2’s output (Figure 2). See the Setting the Output Voltage section. 7 COMP2 8 9 10 Converter 2 Internal Transconductance Amplifier Output. See the Compensation section. OSC Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (ROSC) to set the switching frequency (see the Setting the Switching Frequency section). Set ROSC for an oscillator frequency equal to the SYNC input frequency when using external synchronization. ROSC is still required when an external clock is connected to the SYNC input. See the Synchronization (SYNC) section. SYNC External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the switching frequency with the system clock. Each converter frequency is 1/2 of the frequency applied to SYNC (FSEL_1 = VL). For FSEL_1 = SGND, the switching frequency of converter 1 becomes 1/4 of the SYNC frequency. Connect SYNC to SGND when not used. GATE Gate Drive Output. Connect to the gate of the external n-channel load-dump protection MOSFET. GATE = IN_HIGH + 9V (typ) with IN_HIGH = 12V. GATE pulls to IN_HIGH by an internal n-channel MOSFET when V+ raises 2V above IN_HIGH. Leave GATE unconnected if the load-dump protection is not used (MOSFET not installed). 11 ON/OFF n-Channel Switch Enable Input. Drive ON/OFF high for normal operation. Drive ON/OFF low to turn off the external n-channel load-dump protection MOSFET and reduce the supply current to 7μA (typ). When ON/OFF is driven low, both DC-DC converters are disabled and the PGOOD_ outputs are driven low. Connect to V+ if the external load-dump protection is not used (MOSFET not installed). 12 IN_HIGH Startup Input. IN_HIGH is protected by internally clamping to 21V (max). Connect a resistor (4kΩ max) from IN_HIGH to the drain of the protection switch. Bypass IN_HIGH with a 4.7μF electrolytic or 1μF minimum ceramic capacitor. Connect to V+ if the external load-dump protection is not used (MOSFET not installed). 13 V+ Input Supply Voltage. V+ can range from 5.2V to 19V. Connect V+, IN_HIGH, and VL together for 4.5V to 5.5V input operation. Bypass V+ to SGND with a 1μF minimum ceramic capacitor. 14 VL Internal Regulator Output. The VL regulator is used to supply the drive current at input VDRV. When driving VDRV, use an RC lowpass filter to decouple switching noise from VDRV to the VL regulator (see the Typical Application Circuit). Bypass VL to SGND with a 4.7μF minimum ceramic capacitor. ______________________________________________________________________________________ 11 MAX5099 Pin Description MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection Pin Description (continued) PIN NAME FUNCTION Signal Ground. Connect SGND to exposed pad and to the board signal ground plane. Connect the board signal ground and power ground planes together at a single point. 15 SGND 16 BYPASS Reference Output Bypass Connection. Bypass to SGND with a 0.22μF or greater ceramic capacitor. 17 FSEL_1 Converter 1 Frequency Select Input. Connect FSEL_1 to VL for normal operation. Connect FSEL_1 to SGND to reduce converter 1’s switching frequency to 1/2 of converter 2’s switching frequency (converter 1 switching frequency is 1/4 the SYNC frequency). Do not leave FSEL_1 unconnected. 18 COMP1 Converter 1 Internal Transconductance Amplifier Output. See the Compensation section. 19 FB1 Converter 1 Feedback Input. Connect FB1 to a resistive divider between converter 1’s output and SGND to adjust the output voltage. To set the output voltage below 0.8V, connect FB1 to a resistive voltage-divider from BYPASS to regulator 1’s output (Figure 2). See the Setting the Output Voltage section. 20 EN1 Converter 1 Active-High Enable Input. Connect to VL for an always-on operation. 21 PGOOD1 Converter 1 Power-Good Output. Open-drain output goes low when converter 1’s output falls below 92.5% of its set regulation voltage. Use PGOOD1 and EN2 to sequence the converters (converter 1 starts first). 22, 23 DRAIN1 Converter 1 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a highside switch and connect DRAIN1 to the DC-DC converters supply input rail. For boost converter operation, use the MOSFET as a low-side switch and connect DRAIN1 to the inductor and diode junction (Figure 5). 24, 25 SOURCE1 Converter 1 Internal MOSFET Source Connection. For buck operation, connect SOURCE1 to the switched side of the inductor. For boost operation, connect SOURCE1 to PGND (Figure 5). 26 Converter 1 Bootstrap Flying-Capacitor Connection. For buck converter operation, connect BST1/VDD1 to a 0.1μF ceramic capacitor and diode according to the Typical Application Circuit. For boost converter BST1/VDD1 operation, driver bypass capacitor connection. Connect to VDRV and bypass with a 0.1μF ceramic capacitor to PGND (Figure 5). 27 Low-Side Driver Supply Input. Connect VDRV to VL through an RC filter to bypass switching noise to the internal VL regulator. For buck converter operation, connect anode terminals of external bootstrap diodes to VDRV. For boost converter operation, connect VDRV to BST1/VDD1 and BST2/VDD2. Bypass with a minimum 2.2μF ceramic capacitor to PGND (see the Typical Application Circuit). Do not connect to an external supply. 28 DL1 29 PGND 30 DL2 31 — 12 VDRV Converter 1 Low-Side Synchronous-Rectifier Gate Driver Output Power Ground. Connect to the board power ground plane. Converter 2 Low-Side Synchronous-Rectifier Gate Driver Output Converter 2 Bootstrap Flying-Capacitor Connection. For buck converter operation, connect BST2/VDD2 to a 0.1μF ceramic capacitor and diode according to the Typical Application Circuit. For boost converter BST2/VDD2 operation, driver bypass capacitor connection. Connect to VDRV and bypass with a 0.1μF ceramic capacitor from BST2/VDD2 to PGND (Figure 5). EP Exposed Pad. Connect EP to SGND. For enhanced thermal dissipation, connect EP to a copper area as large as possible. Do not use EP as the sole ground connection. ______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection V+ MAX5099 1.8V IN_HIGH GATE CHARGE PUMP ON/OFF 20V SHUNT REGULATOR OVERVOLTAGE STARTUP CIRCUIT/ PROTECTION CIRCUIT/ CHARGE PUMP CONVERTER 1 VL MAX DUTY-CYCLE CONTROL CLK1 VL LDO BST1/VDD1 CURRENT LIMIT OSCILLATOR DRAIN1 FREQUENCY CONTROL BYPASS R S FSEL_1 FREQUENCY DIVIDER PWM COMPARATOR SOURCE1 Q VDRV DL1 FSW/4 PGOOD1 Q TRANSCONDUCTANCE ERROR AMPLIFIER PGND 0.8V EN1 DIGITAL SOFT-START FB1 COMP1 0.2V 0.74V SGND SYNC OSC MAIN OSCILLATOR OVERVOLTAGE 0.9V CLK2 CONVERTER 2 EN2 VDRV VL PGOOD2 DRAIN2 BST2/VDD2 SOURCE2 FB2 COMP2 PGND ______________________________________________________________________________________ 13 MAX5099 Functional Diagram MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection Detailed Description PWM Controller The MAX5099 dual DC-DC converters use a pulse-widthmodulation (PWM) voltage-mode control scheme. On each converter the device includes one integrated nchannel MOSFET switch and requires an external low-forward-drop Schottky diode for output rectification. The controller generates the clock signal by dividing down the internal oscillator (fOSC) or the SYNC input when driven by an external clock; therefore, each controller’s switching frequency equals half the oscillator frequency (fSW = fOSC/2) or half of the SYNC input frequency (fSW = fSYNC/2). An internal transconductance error amplifier produces an integrated error voltage at COMP_, providing high DC accuracy. The voltage at COMP_ sets the duty cycle using a PWM comparator and a ramp generator. At each rising edge of the clock, converter 1’s MOSFET switch turns on and remains on until either the appropriate or maximum duty cycle is reached, or the maximum current limit for the switch is reached. Converter 2 operates 180° out-of-phase, so its MOSFET switch turns on at each falling edge of the clock. In the case of buck operation (see the Typical Application Circuit), the internal MOSFET is used in high-side configuration. During each MOSFET’s on-time, the associated inductor current ramps up. During the second half of the switching cycle, the high-side MOSFET turns off and forward biases the Schottky rectifier. During this time, the SOURCE_ voltage is clamped to a diode drop (VD) below ground. A low-forward-voltage-drop (0.4V) Schottky diode must be used to ensure the SOURCE_ voltage does not go below -0.6V absolute max. The inductor releases the stored energy as its current ramps down, and provides current to the output. The bootstrap capacitor is also recharged when the SOURCE_ voltage goes low during the high-side MOSFET off-time. The maximum duty-cycle limits ensure proper bootstrap charging at startup or low input voltages. The circuit goes in discontinuous conduction mode operation at light load, when the inductor current completely discharges before the next cycle commences. Under overload conditions, when the inductor current exceeds the peak current limit of the respective switch, the high-side MOSFET turns off quickly and waits until the next clock cycle. Synchronous-Rectifier Output The MAX5099 is intended mostly for synchronous buck operation with an external synchronous-rectifier MOSFET. During the internal high-side MOSFET on-time, the inductor current ramps up. When the high-side MOSFET turns off, the inductor reverses polarity and forward biases the Schottky rectifier in parallel with the low-side external 14 synchronous MOSFET. The SOURCE_ voltage is clamped to 0.5V below ground until the adaptive breakbefore-make time (tBBM) of 25ns is over. After tBBM, the synchronous-rectifier MOSFET turns on, thus bypassing the Schottky rectifier and reducing the conduction loss during the inductor freewheeling time. The synchronousrectifier MOSFET keeps the circuit in continuous conduction mode operation even at light load because the inductor current is allowed to go negative. The MAX5099, with the synchronous-rectifier driver output (DL_), has an adaptive break-before-make circuit to avoid cross-conduction between the internal power MOSFET and the external synchronous-rectifier MOSFET. When the synchronous-rectifier MOSFET is turning off, the internal high-side power MOSFET is kept off until VDL falls below 0.97V. Similarly, DL_ does not go high until the internal power MOSFET gate voltage falls below 1.24V. Load-Dump Protection Most automotive applications are powered by a multicell, 12V lead-acid battery with a voltage from 9V to 16V (depending on load current, charging status, temperature, battery age, etc.). The battery voltage is distributed throughout the automobile and is locally regulated down to voltages required by the different system modules. Load dump occurs when the alternator is charging the battery and the battery becomes disconnected. Power in the alternator inductance flows into the distributed power system and elevates the voltage seen at each module. The voltage spikes have rise times typically greater than 5ms and decays within several hundred milliseconds but can extend out to 1s or more depending on the characteristics of the charging system. These transients are capable of destroying sensitive electronic equipment on the first fault event. During load dump, the MAX5099 provides the ability to clamp the input-voltage rail of the internal DC-DC converters to a safe level, while preventing power discontinuity at the DC-DC converters’ outputs. The load-dump protection circuit utilizes an internal charge pump to drive the gate of an external n-channel MOSFET. This series-protection MOSFET absorbs the load-dump overvoltage transient and operates in saturation over the normal battery range to minimize power dissipation. During load dump, the gate voltage of the protection MOSFET is regulated to prevent the source terminal from exceeding 19V. The DC-DC converters are powered from the source terminal of the load-dump protection MOSFET, so that their input voltage is limited during load dump and can operate normally. ______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection Internal Oscillator/ Out-of-Phase Operation The internal oscillator generates the 180° out-of-phase clock signal required by each regulator. The switching frequency of each converter (fSW) is programmable from 200kHz to 2.2MHz using a single 1% resistor at ROSC. See the Setting the Switching Frequency section. With dual-synchronized out-of-phase operation, the MAX5099’s internal MOSFETs turn on 180° out-ofphase. The instantaneous input current peaks of both regulators do not overlap, resulting in reduced RMS ripple current and input-voltage ripple. This reduces the required input capacitor ripple current rating, allows for fewer or less expensive capacitors, and reduces shielding requirements for EMI. Synchronization (SYNC) The main oscillator can be synchronized to the system clock by applying an external clock (fSYNC) at SYNC. The fSYNC frequency must be twice the required operating frequency of an individual converter. Use a TTL logic signal for the external clock with at least a 100ns pulse width. ROSC is still required when using external synchronization. Program the internal oscillator frequency to have fSW = 1/2 fSYNC. The device is properly synchronized if the SYNC frequency fSYNC varies within the range ±20%. Short SYNC to SGND if unused. Input Voltage (V+)/ Internal Linear Regulator (VL) All internal control circuitry operates from an internally regulated nominal voltage of 5.2V (VL). At higher input voltages (V+) of 5.2V to 19V, VL is regulated to 5.2V. At 5.2V or below, the internal linear regulator operates in dropout mode, where VL follows V+. Depending on the load on VL, the dropout voltage can be high enough to reduce V L below the undervoltage-lockout (UVLO) threshold. Do not use VL to power external circuitry. For input voltages less than 5.5V, connect V+ and VL together. The load on VL is proportional to the switching frequency of converter 1 and converter 2. See the VL Output Voltage vs. Converter Switching Frequency graph in the Typical Operating Characteristics . For input voltage ranges higher than 5.5V, disconnect VL from V+. Bypass V+ to SGND with a 1μF or greater ceramic capacitor placed close to the MAX5099. Bypass VL with a low-ESR 4.7μF ceramic capacitor to SGND. Undervoltage Lockout/ Soft-Start/Soft-Stop The MAX5099 includes an undervoltage lockout with hysteresis and a power-on-reset circuit for converter turn-on and monotonic rise of the output voltage. The falling UVLO threshold is internally set to 4.1V (typ) with 180mV hysteresis. Hysteresis at UVLO eliminates “chattering” during startup. When VL drops below UVLO, the internal MOSFET switches are turned off. The MAX5099 digital soft-start reduces input inrush currents and glitches at the input during turn-on. When UVLO is cleared and EN_ is high, digital soft-start slowly ramps up the internal reference voltage in 64 steps. The total soft-start period is 4096 internal oscillator switching cycles. Driving EN_ low initiates digital soft-stop that slowly ramps down the internal reference voltage in 64 steps. The total soft-stop period is equal to the soft-start period. To calculate the soft-start/soft-stop period, use the following equation: t SS (ms) = 4096 fOSC (kHz) where fOSC is the internal oscillator and fOSC is twice each converter’s switching frequency (FSEL_1 = VL). ______________________________________________________________________________________ 15 MAX5099 ON/OFF The MAX5099 provide an input (ON/OFF) to turn on and off the external load-dump protection MOSFET. Drive ON/OFF high for normal operation. Drive ON/OFF low to turn off the external n-channel load-dump protection MOSFET and reduce the supply current to 7μA (typ). When ON/OFF is driven low, both converters are also turned off, and the PGOOD_ outputs are driven, low. V+ will be self-discharged through the converters’ output currents and the IC supply current. MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection VIN VIN VL VL OUTPUT2 N VL DRAIN2 V+ DRAIN1 SOURCE2 SOURCE1 DL2 FB2 MAX5099 OUTPUT1 OUTPUT2 N DL1 N FB1 VL DRAIN2 V+ DRAIN1 SOURCE2 SOURCE1 DL2 MAX5099 DL1 FB2 FB1 EN2 EN1 OUTPUT1 N R2 VL EN2 VL EN1 R1 VL C2 PGOOD1 SEQUENCING—OUTPUT 2 DELAYED WITH RESPECT TO OUTPUT 1. VL C1 R1/C1 AND R2/C2 ARE SIZED FOR REQUIRED SEQUENCING. Figure 1. Power-Supply Sequencing Configurations Enable (EN1, EN2) The MAX5099 dual converter provides separate enable inputs, EN1 and EN2, to individually control or sequence the output voltages. These active-high enable inputs are TTL compatible. Driving EN_ high initiates soft-start of the converter, and PGOOD_ goes logic-high when the converter output voltage reaches the VTPGOOD_ threshold. Driving EN_ low initiates a soft-stop of the converter. Use EN1, EN2, and PGOOD1 for sequencing (see Figure 1). Connect PGOOD1 to EN2 to make sure converter 1’s output is within regulation before converter 2 starts. Add an RC network from VL to EN1 and EN2 to delay the individual converter. Sequencing reduces input inrush current and possible chattering. Connect EN_ to VL for always-on operation. PGOOD_ Converter 1 and converter 2 include power-good flags, PGOOD1 and PGOOD2, respectively. Since PGOOD_ is an open-drain output and can sink 3mA while providing the TTL logic-low signal, pull PGOOD_ to a logic voltage to provide a logic-level output. PGOOD1 goes low when converter 1’s feedback (FB_) drops to 92.5% (VTPGOOD_) of its nominal set point. The same is true for converter 2. Connect PGOOD_ to SGND or leave unconnected, if not used. Current Limit The internal high-side MOSFET switch current of each converter is monitored during its on-time. When the peak switch current crosses the current-limit threshold 16 of 3.45A (typ) and 2.1A (typ) for converter 1 and converter 2, respectively, the on-cycle is terminated immediately and the inductor is allowed to discharge. The MOSFET switch is turned on at the next clock pulse initiating a new clock cycle. In deep overload or short-circuit conditions when VFB drops below 0.2V, the switching frequency is reduced to 1/4 x fSW to provide sufficient time for the inductor to discharge. During overload conditions, if the voltage across the inductor is not high enough to allow for the inductor current to properly discharge, current runaway may occur. Current runaway can destroy the device in spite of internal thermal-overload protection. Reducing the switching frequency during overload conditions prevents current runaway. Output Overvoltage Protection The MAX5099 outputs are protected from output voltage overshoots due to input transients and shorting the output to a high voltage. When the output voltage rises over the overvoltage threshold, 114% (typ) nominal FB, the overvoltage condition is triggered. When the overvoltage condition is triggered on either channel, both converters are immediately turned off, 20Ω pulldown switches from SOURCE_ to PGND are turned on to help the output-voltage discharge, and the gate of the loaddump protection external MOSFET is pulled low. The device restarts as soon as both converter outputs discharge, bringing both FB_ input voltages below 12.5% of their nominal set points. ______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection Applications Information Setting the Switching Frequency The controller generates the clock signal by dividing down the internal oscillator fOSC or the SYNC input signal when driven by an external oscillator. The switching frequency equals half the internal oscillator frequency (fSW = fOSC/2). The internal oscillator frequency is set by a resistor (ROSC) connected from OSC to SGND. To find ROSC for each converter switching frequency fSW, use the formulas: ROSC (kΩ) = ROSC (kΩ) = 10.721 fSW (MHz) 12.184 fSW (MHz) ( ) ( ) f ≥ 1.25MHz 0.920 SW f < 1.25MHz 0.973 SW A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by ROSC. When an external synchronization signal is used, ROSC must be selected such that fSW = 1/2 fSYNC. Buck Converter Effective Input Voltage Range Although the MAX5099 converter operates from input supplies ranging from 5.2V to 19V, the input voltage range can be effectively limited by the MAX5099 dutycycle limitations for a given output voltage. The maximum input voltage is limited by the minimum on-time (tON(MIN)): VIN(MAX) ≤ VOUT t ON(MIN) × fSW where tON(MIN) is 100ns. The minimum input voltage is limited by the maximum duty cycle (DMAX = 0.92): ⎡V ⎤ +V VIN(MIN) = ⎢ OUT DROP1 ⎥ + VDROP2 − VDROP1 DMAX ⎣ ⎦ where VDROP1 is the total parasitic voltage drops in the inductor discharge path, which includes the forward voltage drop (VDS) of the low-side n-channel MOSFET, the series resistance of the inductor, and the PCB resistance. VDROP2 is the total resistance in the charging path that includes the on-resistance of the high-side switch, the series resistance of the inductor, and the PCB resistance. Setting the Output Voltage For 0.8V or greater output voltages, connect a voltagedivider from OUT_ to FB_ to SGND (Figure 2). Select RB (FB_ to SGND resistor) to between 1kΩ and 20kΩ. Calculate RA (OUT_ to FB_ resistor) with the following equation: ⎡⎛ VOUT _ ⎞ ⎤ RA = RB ⎢⎜ ⎟ − 1⎥ ⎢⎣⎝ VFB _ ⎠ ⎥⎦ where VFB_ = 0.8V (see the Electrical Characteristics table). For output voltages below 0.8V, set the MAX5099 output voltage by connecting a voltage-divider from OUT_ to FB_ to BYPASS (Figure 2). Select RC (FB_ to BYPASS resistor) higher than a 50kΩ range. Calculate RA with the following equation: ⎡ V ⎤ −V RA = RC ⎢ FB _ OUT _ ⎥ ⎢⎣ VBYPASS − VFB _ ⎥⎦ where VFB_ = 0.8V, VBYPASS = 2V (see the Electrical Characteristics table), and VOUT_ can range from 0V to VFB_. ______________________________________________________________________________________ 17 MAX5099 Thermal-Overload Protection During continuous short circuit or overload at the output, the power dissipation in the IC can exceed its limit. The MAX5099 provides thermal shutdown protection with temperature hysteresis. Internal thermal shutdown is provided to avoid irreversible damage to the device. When the die temperature exceeds +165°C (typ), an onchip thermal sensor shuts down the device, forcing the internal switches to turn off, allowing the IC to cool. The thermal sensor turns the part on again with soft-start after the junction temperature cools by +20°C. During thermal shutdown, both regulators shut down, PGOOD_ goes low, and soft-start resets. The internal 20V zener clamp from IN_HIGH to SGND is not turned off during thermal shutdown because this clamping action must always be active. MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection VOUT_ VOUT_ SOURCE_ BYPASS RA RC FB_ FB_ MAX5099 RB MAX5099 RA SOURCE_ VOUT_ ≥ 0.8V VOUT_ < 0.8V capacitance requirement. Note that the two converters of the MAX5099 run 180° out-of-phase, thereby effectively doubling the switching frequency at the input. The input ripple waveform would be unsymmetrical due to the difference in load current and duty cycle between converter 1 and converter 2. The worst-case mismatch is when one converter is at full load while the other is at no load or in shutdown. The input ripple is comprised of ΔVQ (caused by the capacitor discharge) and ΔVESR (caused by the ESR of the capacitor). Use ceramic capacitors with high ripple-current capability at the input connected between DRAIN_ and PGND. Assume the contribution from the ESR and capacitor discharge equal to 50%. Calculate the input capacitance and ESR required for a specified ripple using the following equations: Figure 2. Adjustable Output Voltage Inductor Selection Three key inductor parameters must be specified for operation with the MAX5099: inductance value (L), peak inductor current (IL), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (ΔIL). A good compromise is to choose ΔIL equal to 30% of the full load current. To calculate the inductance, use the following equation: L= VIN × fSW × ΔIL Input Capacitor The discontinuous input current waveform of the buck converter causes large ripple currents at the input. The switching frequency, peak inductor current, and allowable peak-to-peak voltage ripple dictate the input ΔVESR ΔI IOUT + L 2 where ΔIL = (VIN − VOUT ) × VOUT VIN × fSW × L and CIN = VOUT (VIN − VOUT ) where VIN and VOUT are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by ROSC (see the Setting the Switching Frequency section). The peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worse at the maximum input voltage. See the Output Capacitor section to verify that the worst-case output ripple is acceptable. The inductor saturation current is also important to avoid runaway current during output overload and continuous short circuit. Select the ISAT to be higher than the maximum peak current limits of 4.3A and 2.6A for converter 1 and converter 2. 18 ESRIN = IOUT × D(1 − D) ΔVQ × fSW where V D = OUT VIN where IOUT is the maximum output current from either converter 1 or converter 2, and D is the duty cycle for that converter. fSW is the frequency of each individual converter. For example, at VIN = 12V, VOUT = 3.3V at I OUT = 2A, and with L = 3.3μH, the ESR and input capacitance are calculated for a peak-to-peak input ripple of 100mV or less, yielding an ESR and capacitance value of 20mΩ and 6.8μF for 1.25MHz frequency. At low input voltages, also add one electrolytic bulk capacitor of at least 100μF on the converters’ input voltage rail. This capacitor acts as an energy reservoir to avoid possible undershoot below the undervoltage-lockout threshold during power-on and transient loading. ______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection ΔVESR ΔIL ΔIL COUT = 8 × ΔVQ × fSW ESROUT = ΔVESR ISTEP ×t I COUT = STEP RESPONSE ΔVQ ESROUT = where I STEP is the load step and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth. Boost Converter The MAX5099 can be configured for step-up conversion since the internal MOSFET can be used as a lowside switch. Use the following equations to calculate the values for the inductor (LMIN), input capacitor (CIN), and output capacitor (COUT) when using the converter in boost operation. Inductor Choose the minimum inductor value so the converter remains in continuous mode operation at minimum output current (IOMIN). where LMIN = ΔVO _ RIPPLE ≅ ΔVESR + ΔVQ ΔIL is the peak-to-peak inductor current as calculated above and fSW is the individual converter’s switching frequency. The allowable deviation of the output voltage during fast transient loads also determines the output capacitance and its ESR. The output capacitor supplies the step load current until the controller responds with a greater duty cycle. The response time (t RESPONSE) depends on the closed-loop bandwidth of the converter. The high switching frequency of the MAX5099 allows for higher closed-loop bandwidth, reducing tRESPONSE and the output capacitance requirement. The resistive drop across the output capacitor ESR and the capacitor discharge causes a voltage droop during a step load. Use a combination of low-ESR tantalum or polymer and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output-voltage deviation within the tolerable limits of the electronics being powered. When using a ceramic capacitor, assume 80% and 20% contribution from the output capacitance discharge and the ESR drop, respectively. Use the following equations to calculate the required ESR and capacitance value: VIN2 × D 2 × fSW × VO × IOMIN where D= VO + VD − VIN VO + VD − VDS VD is the forward voltage drop of the external Schottky diode, D is the duty cycle, and VDS is the voltage drop across the internal MOSFET switch. Select the inductor with low DC resistance and with a saturation current (ISAT) rating higher than the peak switch current limit of 4.3A (ICL1) and 2.6A (ICL2) of converter 1 and converter 2, respectively. Input Capacitor The input current for the boost converter is continuous, and the RMS ripple current at the input is low. Calculate the capacitor value and ESR of the input capacitor using the following equations: CIN = ΔIL 8 × fSW × ΔVQ ESR = ΔVESR ΔIL ______________________________________________________________________________________ 19 MAX5099 Output Capacitor The allowable output ripple voltage and the maximum deviation of the output voltage during step load currents determine the output capacitance and its ESR. The output ripple is comprised of ΔVQ (caused by the capacitor discharge) and ΔVESR (caused by the ESR of the capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic capacitors, the entire output ripple is contributed by ΔVESR. Use the ESROUT equation to calculate the ESR requirements and choose the capacitor accordingly. If using ceramic capacitors, assume the contribution to the output ripple voltage from the ESR and the capacitor discharge are equal. Calculate the output capacitance and ESR required for a specified ripple using the following equations: MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection where where ΔIL = (VIN − VDS ) × D L × fSW where VDS is the voltage drop across the internal MOSFET switch. ΔIL is the peak-to-peak inductor ripple current as calculated above. ΔVQ is the portion of input ripple due to the capacitor discharge, and ΔVESR is the contribution due to ESR of the capacitor. Output Capacitor For the boost converter, the output capacitor supplies the load current when the main switch is on. The required output capacitance is high, especially at higher duty cycles. Also, the output capacitor ESR needs to be low enough to minimize the voltage drop due to the ESR while supporting the load current. Use the following equation to calculate the output capacitor for a specified output ripple tolerance: ΔV ESR = ESR IPK IO × DMAX COUT = ΔVQ × fSW where IPK is the peak inductor current as defined in the following Power Dissipation section, IO is the load current, ΔVQ is the portion of the ripple due to the capacitor discharge, and ΔVESR is the contribution due to the ESR of the capacitor. DMAX is the maximum duty cycle at minimum input voltage. Power Dissipation The MAX5099 includes two internal power MOSFET switches. The DC loss is a function of the RMS current in the switch while the switching loss is a function of switching frequency and instantaneous switch voltage and current. Use the following equations to calculate the RMS current, DC loss, and switching loss of each converter. The MAX5099 is available in a thermally enhanced package and can dissipate up to 2.7W at +70°C ambient temperature. The total power dissipation in the package must be limited so that the operating junction temperature does not exceed its absolute maximum rating of +150°C at maximum ambient temperature. For the buck converter: IRMS = (IDC2 + IPK2 + (IDC × IPK )) × DMAX 3 PDC = IRMS2 × RON(MAX) 20 ΔIL 2 ΔIL IPK = IO + 2 VIN × IO × ( tR + tF ) × fSW IDC = IO − PSW = 4 See the Electrical Characteristics table for the RON(MAX) maximum value. For the boost converter: IRMS = (I2DC + I2PK + (IDC × IPK )) × DMAX 3 V ×I IIN = O O VIN × η ΔIL = (VIN − VDS ) × D L × fSW ΔIL 2 ΔIL IPK = IIN + 2 IDC = IIN − PDC = IRMS2 × RON(MAX) where VDS is the drop across the internal MOSFET and η is the efficiency. See the Electrical Characteristics table for the RON(MAX) value. PSW = VO × IIN × (tR + tF ) × fSW 4 where tR and tF are rise and fall times of the internal MOSFET. The tR and tF can be measured in the actual application. The supply current in the MAX5099 is dependent on the switching frequency. See the Typical Operating Characteristics to find the supply current of the MAX5099 at a given operating frequency. The power dissipation (PS) in the device due to supply current (ISUPPLY) is calculated using following equation: PS = VINMAX x ISUPPLY The total power dissipation PT in the device is: PT = PDC1 + PDC2 + PSW1 + PSW2 + PS where PDC1 and PDC2 are DC losses in converter 1 and converter 2, respectively. PSW1 and PSW2 are switching losses in converter 1 and converter 2, respectively. ______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection 2) Select the unity-gain crossover frequency: f fC ≤ SW 20 If the fZERO,ESR is lower than fC and close to fLC, use a Type II compensation network where RFCF provides a midband zero fMID,ZERO, and RFCCF provides a highfrequency pole. 3) Calculate modulator gain G M at the crossover frequency. Compensation The MAX5099 provides an internal transconductance amplifier with its inverting input and its output available for external frequency compensation. The flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications, use high-ESR aluminum electrolytic capacitors; for component size-sensitive applications, use low-ESR tantalum, polymer, or ceramic capacitors at the output. The high switching frequency of the MAX5099 allows the use of ceramic capacitors at the output. Choose all the passive power components that meet the output ripple, component size, and component cost requirements. Choose the small-signal components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. Use a simple pole-zero pair (Type II) compensation if the output capacitor ESR zero frequency is below the unity-gain crossover frequency (f C). Type III compensation is necessary when the ESR zero frequency is higher than fC or when compensating for a continuous-mode boost converter that has a right-half-plane zero. Use procedure 1 to calculate the compensation network components when fZERO,ESR < fC. GM = 0.8 VIN ESR × × VOSC ESR + (2π × fC × L OUT ) VOUT where VOSC is a peak-to-peak ramp amplitude equal to 1V. The transconductance error-amplifier gain is: GE/A = gM x RF The total loop gain at fC should be equal to 1: GM x GE/A = 1 or V (ESR + 2 π × fC × LOUT ) × VOUT RF = OSC 0.8 × VIN × gM × ESR 4) Place a zero at or below the LC double-pole: CF = 5) Place a high-frequency pole at fP = 0.5 x fSW. CCF = Buck Converter Compensation Procedure 1 (See Figure 3) 1) Calculate the f ZERO,ESR and LC double-pole frequencies: fZERO,ESR = fLC = 2 π LOUT × COUT CF (2 π × 0.5fSW × RF × CF ) − 1 VOUT R1 FB_ 1 2 π × ESR × COUT 1 1 2π × RF × fLC - COMP_ gM R2 VREF + RF CF CCF Figure 3. Type II Compensation Network ______________________________________________________________________________________ 21 MAX5099 Calculate the temperature rise of the die using the following equation: TJ = TC x (PT x θJC) where θJC is the junction-to-case thermal impedance of the package equal to +1.7°C/W. Solder the exposed pad of the package to a large copper area to minimize the case-to-ambient thermal impedance. Measure the temperature of the copper area near the device at a worst-case condition of power dissipation, and use +1.7°C/W as θJC thermal impedance. MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection Procedure 2 (See Figure 4) If the output capacitor used is a low-ESR ceramic type, the ESR frequency is usually far away from the targeted unity crossover frequency (fC). In this case, Type III compensation is recommended. Type III compensation provides two-pole zero pairs. The locations of the zero and poles should be such that the phase margin peaks around fC. It is also important to place the two zeros at or below the double pole to avoid the conditional stability issue. 1) Select a crossover frequency: f fSW ≤ SW 20 VOUT CCF RI CF RF R1 CI FB_ gM R2 COMP_ + VREF Figure 4. Type III Compensation Network 2) Calculate the LC double-pole frequency, fLC: fLC = 7) Place a second pole at 1/2 the switching frequency. 1 2π × L OUT × COUT 3) Place a zero fZ1 = 1 at 0.75 × fLC. 2π × RF × CF where CF = 1 2π × 0.75 × fLC × RF and RF ≥ 10kΩ. 4) Calculate CI for a target unity crossover frequency, fC. CI = 2π × fC × L OUT × COUT × VOSC VIN × RF CCF = Boost Converter Compensation The boost converter compensation gets complicated due to the presence of a right-half-plane zero fZERO,RHP. The right-half-plane zero causes a drop in phase while adding positive (+1) slope to the gain curve. It is important to drop the gain significantly below unity before the RHP frequency. Use the following procedure to calculate the compensation components: 1) Calculate the LC double-pole frequency, fLC, and the right-half-plane-zero frequency. fLC = 1 5) Place a pole fP1 = at fZERO,ESR. 2π × RI × CI RI = 1 R1 = 1 2 π × fZ2 × CI − RI 1− D 2π × L OUT × COUT fZERO,RHP = 2π × fZERO,ESR × CI 6) Place a second zero, f Z2 , at 0.2 x f C or at f LC , whichever is lower. CF (2π × 0.5 × fSW × RF × CF ) − 1 (1 − D)2R(MIN) 2π × L OUT where D = 1− R(MIN) = VIN VOUT VOUT IOUT(MAX) Target the unity-gain crossover frequency for: fC ≤ 22 fZERO,RHP 5 ______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection CF = 1 at 0.75 × fLC. 2 π × RF × CF 1 2π × 0.75 × fLC × RF where RF ≥ 10kΩ. 3) Calculate CI for a target crossover frequency, fC: 2 VOSC ⎡⎢(1 − D) + ω C2L OCO ⎤⎥ ⎣ ⎦ CI = ω CRF VIN where ωC = 2π x fC. 4) Place a pole fP1 = 1 at fZERO,RHP 2 π × RI × CI Choose a suitable power MOSFET that can safely operate in the saturation region. Verify its capability to support the downstream DC-DC converters’ input current during the load-dump event by checking its safe operating area (SOA) characteristics. Since the transient peak power dissipation on the MOSFET can be very high during the load-dump event, also refer to the thermal impedance graph given in the data sheet of the power MOSFET to make sure its transient power dissipation is kept within the recommended limits. Improving Noise Immunity In applications where the MAX5099 is subject to noisy environments, adjust the controller’s compensation to improve the system’s noise immunity. In particular, highfrequency noise coupled into the feedback loop causes jittery duty cycles. One solution is to lower the crossover frequency (see the Compensation section). or 5 x fC, whichever is lower. RI = 1 2π × f × CI VL 1 at fLC. 5) Place the second zero fZ2 = 2 π × R1× CI R1 = VDRV 1 2 π × fLC × CI − RI 6) Place the second pole at 1/2 the switching frequency. CCF = MAX5099 BST_/VDD_ V+ PGND CF (2π × 0.5 × fSW × RF × CF ) − 1 VOUT_ DRAIN_ Load-Dump Protection MOSFET Select the external MOSFET with an adequate voltage rating, VDSS, to withstand the maximum expected loaddump input voltage. The on-resistance of the MOSFET, RDS(ON), should be low enough to maintain a minimal voltage drop at full load, limiting the power dissipation of the MOSFET. During regular operation, the power dissipated by the MOSFET is: PNORMAL = ILOAD2 x RDS(ON) where ILOAD is equal to the sum of both converters’ input currents. The MOSFET operates in a saturation region during load dump, with both high voltage and current applied. DRAIN_ COUT *DL_ SOURCE_ SOURCE_ SGND FB_ *LEAVE DL_ UNCONNECTED. Figure 5. Boost Application ______________________________________________________________________________________ 23 MAX5099 2) Place a zero fZ1 = MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection PCB Layout Guidelines Layout Procedure Careful PCB layout is critical to achieve low switching losses and clean, stable operation. This is especially true for dual converters where one channel can affect the other. Refer to the MAX5098A/MAX5099 Evaluation Kit data sheet for a specific layout example. Use a multilayer board whenever possible for better noise immunity. Follow these guidelines for good PCB layout: 1) Place the power components first, with ground terminals adjacent (inductor, CIN_, and COUT_). Make all these connections on the top layer with wide, copper-filled areas (2oz copper recommended). 2) Group the gate-drive components (bootstrap diodes and capacitors, and VL bypass capacitor) together near the controller IC. 1) For SGND, use a large copper plane under the IC and solder it to the exposed paddle. To effectively use this copper area as a heat exchanger between the PCB and ambient, expose this copper area on the top and bottom side of the PCB. Do not make a direct connection from the exposed pad copper plane to SGND underneath the IC. 2) Isolate the power components and high-current path from the sensitive analog circuitry. 3) Make the DC-DC controller ground connections as follows: a) Create a signal ground plane underneath the IC. b) Connect this plane to SGND and use this plane for the ground connection for the reference (BYPASS), enable, compensation components, feedback dividers, and OSC resistor. 3) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. c) Connect SGND and PGND together (this is the only connection between SGND and PGND). Refer to the MAX5098A/MAX5099 Evaluation Kit data sheet for more information. 4) Connect SGND and PGND together at a single point. Do not connect them together anywhere else (refer to the MAX5099 Evaluation Kit data sheet for more information). 5) Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper PCBs (2oz vs. 1oz) to enhance fullload efficiency. 6) Ensure that the feedback connection to COUT is short and direct. 7) Route high-speed switching nodes (BST_/VDD_, SOURCE_) away from the sensitive analog areas (BYPASS, COMP_, and FB_). Use the internal PCB layer for SGND as an EMI shield to keep radiated noise away from the IC, feedback dividers, and analog bypass capacitors. 24 ______________________________________________________________________________________ SGND PGND VOUT1 R22 C7 R8 R6 C8 L1 R7 D2 VL C20 C9 4 R11 N2 6 5 21 C6 D1 R9 3 2 1 IN_HIGH JU4 17 20 21 18 19 28 FSEL_1 EN1 PGOOD1 COMP1 FB1 DL1 25 SOURCE1 24 SOURCE1 26 BST1/VDD1 OSC 8 R12 ON/OFF BYPASS 16 C11 10 GATE 11 13 MAX5099 V+ 12 15 C19 VDRV C12 27 22 23 VIN DRAIN1 DRAIN1 VDRV C1 C4 2 3 C13 SYNC EN2 PGOOD2 COMP2 FB2 PGND DL2 SOURCE2 SOURCE2 BST2/VDD2 14 VL PGND SGND DRAIN2 DRAIN2 VIN 9 5 4 7 6 29 30 32 1 31 C15 R18 3 C21 C17 4 1 2 56 N3 C14 D4 VDRV R16 D5 L2 R17 C16 R15 C5 R23 SGND PGND VOUT2 MAX5099 VIN = 4.5V TO 5.5V Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection Figure 6. 4.5V to 5.5V Operation ______________________________________________________________________________________ 25 VOUT1 = 5V AT 2A SGND PGND VOUT1 R22 10kΩ 1% R8 976Ω 1% C8 270pF R6 52.3kΩ 1% C7 22μF D2 R7 10kΩ 1% L1 4.7μH VL R11 C20 33pF 2 1 C9 R9 2700pF 12.7Ω 4 N2 6 5 21 C6 0.1μF D1 3 12 JU4 17 20 21 18 19 28 FSEL_1 EN1 PGOOD1 COMP1 FB1 DL1 25 SOURCE1 24 SOURCE1 26 BST1/VDD1 OSC 8 11 R12 6.49Ω ON/OFF VDRV IN_HIGH R1 3.9kΩ C2 4.7μF 35V 16 BYPASS C1 22μF 100V C11 0.22μF 10 GATE PGND MAX5099 15 13 C3 150μF 25V VDRV V+ N1 VDRV C12 2.2μF 27 C19 1μF 25V 22 23 R21 1Ω DRAIN1 DRAIN1 VIN 2 3 14 C13 4.7μF VL SYNC EN2 PGOOD2 COMP2 FB2 PGND DL2 SOURCE2 SOURCE2 BST2/VDD2 C4 10μF 25V VL VIN = 5.2V TO 19V DRAIN2 DRAIN2 26 SGND 9 5 4 7 6 29 32 32 1 31 C15 10μF 25V 4 C21 56pF C17 R18 7.15Ω 2700pF 3 1 2 56 N3 C14 0.1μF D4 VDRV R16 12.1kΩ 1% D5 L2 4.7μH R17 976Ω 1% C16 270pF R15 37.4kΩ 1% C5 22μF R23 10kΩ 1% SGND PGND VOUT2 VOUT2 = 3.3V AT 1A MAX5099 Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection Typical Application Circuit ______________________________________________________________________________________ Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection PROCESS: BiCMOS SOURCE1 DRAIN1 DRAIN1 PGOOD1 EN1 FB1 COMP1 FSEL_1 TOP VIEW 24 23 22 21 20 19 18 17 SOURCE1 25 16 BYPASS BST1/VDD1 26 15 SGND VDRV 27 DL1 28 MAX5099 PGND 29 DL2 30 BST2/VDD2 31 *EP + 4 5 6 7 8 EN2 FB2 COMP2 OSC DRAIN2 3 PGOOD2 2 DRAIN2 1 SOURCE2 SOURCE2 32 14 VL 13 V+ 12 IN_HIGH 11 ON/OFF 10 GATE 9 SYNC Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 TQFN T3255+4 21-0140 TQFN (5mm x 5mm) *CONNECT EXPOSED PAD TO GROUND PLANE AND TO SGND. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX5099 Chip Information Pin Configuration