MAXIM MAX5214

19-5651; Rev 0; 12/10
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
The MAX5214/MAX5216 are pin-compatible, 14-bit
and 16-bit digital-to-analog converters (DACs). The
MAX5214/MAX5216 are single-channel, low-power, buffered voltage-output DACs. The devices use a precision
external reference applied through the high resistance
input for rail-to-rail operation and low system power
consumption. The MAX5214/MAX5216 accept a wide
2.7V to 5.25V supply voltage range. Power consumption is extremely low to accommodate most low-power
and low-voltage applications. These devices feature a
3-wire SPIK-/QSPIK-/MICROWIREK-/DSP-compatible
serial interface to save board space and to reduce
the complexity in isolated applications. The MAX5214/
MAX5216 minimize the digital noise feedthrough from
input to output with SCLK and DIN input buffers powered down after completion of each serial input frame.
On power-up, the MAX5214/MAX5216 reset the DAC
output to zero, providing additional safety for applications that drive valves or other transducers that need
to be off on power-up. The DAC output is buffered
resulting in a low supply current of 80FA (max) and
a low offset error of Q0.25mV. A zero level applied to
the CLR pin asynchronously clears the contents of the
input and DAC registers and sets the DAC output to
zero independent of the serial interface. The MAX5214/
MAX5216 are available in an ultra-small (3mm x 3mm),
8-pin FMAX® package and are specified over the
-40NC to +105NC extended industrial temperature range.
Applications
2-Wire Sensors
Communication Systems
Automatic Tuning
Gain and Offset Adjustment
Features
S Low-Power Consumption (80µA max)
S 14-/16-Bit Resolution in a 3mm x 3mm, 8-Pin
µMAX Package
S Relative Accuracy
±0.25 LSB INL (MAX5214, 14-Bit)
±1.0 LSB INL (MAX5216, 16-Bit)
S Guaranteed Monotonic Over All Operating Ranges
S Low Gain and Offset Error
S Wide 2.7V to 5.25V Supply Range
S Rail-to-Rail Buffered Output Operation
S Safe Power-On Reset (POR) to Zero DAC Output
S Fast 50MHz, 3-Wire, SPI/QSPI/MICROWIRECompatible Serial Interface
S Schmitt-Trigger Inputs for Direct Optocoupler
Interface
S Asynchronous CLR Clears DAC Output to Code 0
S High Reference Input Resistance for Power
Reduction
S Buffered Voltage Output Directly Drives 10kI
Loads
Ordering Information
PART
RESOLUTION
(BITS)
PIN-PACKAGE
MAX5214GUA+
8 FMAX
14
MAX5216GUA+
8 FMAX
16
Note: All devices are specified over the -40°C to +105°C
operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Functional Diagram
Power Amplifier Control
Process Control and Servo Loops
Portable Instrumentation
VDD
REF
Programmable Voltage and Current Sources
Automatic Test Equipment
MAX5214
MAX5216
POR
CS
SCLK
DIN
SERIAL-TOPARALLEL
CONVERTER
INPUT
REGISTER
DAC
REGISTER
14-/16-BIT
DAC
CLR
GND
BUFFER
OUT
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5214/MAX5216
General Description
MAX5214/MAX5216
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
ABSOLUTE MAXIMUM RATINGS
VDD to GND..............................................................-0.3V to +6V
REF, OUT, CLR to GND...............................-0.3V to the lower of
(VDD + 0.3V) and +6V
SCLK, DIN, CS to GND............................................-0.3V to +6V
Continuous Power Dissipation (TA = +70NC)
FMAX (derate at 4.8mW/NC above +70NC)..................387mW
Maximum Current into Any Input or Output..................... Q50mA
Operating Temperature Range......................... -40NC to +105NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
PACKAGE THERMAL CHARACTERISTICS (Note 1)
FMAX
Junction-to-Ambient Thermal Resistance (BJA).........206NC/W
Junction-to-Case Thermal Resistance (BJC)................42NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V, VREF = 5V, CL = 100pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are at TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY (Note 2)
Resolution
N
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Offset Error
OE
MAX5214
14
MAX5216
16
MAX5214 (14-bit) (Note 3)
-1
Q0.25
+1
MAX5216 (16-bit) (Note 3)
-3
Q1
+3
MAX5214 (14-bit) (Note 3)
-1
Q0.1
+1
MAX5216 (16-bit) (Note 3)
-1
Q0.1
+1
-1.25
Q0.25
+1.25
(Note 4)
Offset-Error Drift
Gain Error
Bits
Q0.5
GE
(Note 4)
-0.06
Gain Temperature Coefficient
-0.04
LSB
LSB
mV
FV/NC
0
%FS
ppmFS/
NC
Q2
REFERENCE INPUT
Reference-Input Voltage Range
VREF
2
Reference-Input Impedance
RREF
200
VDD
256
V
kI
DAC OUTPUT
No load (typical)
VDD
Output Voltage Range
10kI load
VDD 0.2
0.2
DC Output Impedance
0.1
Capacitive Load (Note 5)
CL
Resistive Load (Note 5)
RL
I
0.1
Series resistance = 0I
15
Series resistance = 1kI
5
Short-Circuit Current
VDD = 5.25V
Power-Up Time
From power-down mode
-10
V
nF
FF
kI
Q5
25
2 _______________________________________________________________________________________
+10
mA
Fs
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
(VDD = 5V, VREF = 5V, CL = 100pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are at TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN, CS, CLR)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
IIN
Input Capacitance
CIN
Hysteresis Voltage
VHYS
0.7 x
VDD
VIN = 0V or VDD
V
Q0.1
0.3 x
VDD
V
Q1
FA
10
pF
0.15
V
Positive and negative
0.5
V/Fs
1/4 scale to 3/4 scale, to P 0.5 LSB, 14-bit
14
Fs
Hex code = 2000 (MAX5214),
Hex code = 8000 (MAX5216)
100
kHz
Digital Feedthrough
Code = 0, all digital inputs from 0V to VDD,
SCLK < 50MHz
0.5
nV·s
DAC Glitch Impulse
Major code transition
2
nV·s
Output Noise
10kHz
70
Integrated Output Noise
0.1Hz to 10Hz
1.5
nV/√Hz
FVP-P
DYNAMIC PERFORMANCE (Note 5)
Voltage-Output Slew Rate
SR
Voltage-Output Settling Time
Reference -3dB Bandwidth
BW
POWER REQUIREMENTS
Supply Voltage
VDD
Supply Current
IDD
Power-Down Supply Current
2.7
5.25
V
No load; all digital inputs at 0V or VDD,
supply current only; excludes reference
input current, midscale
70
80
FA
No load, all digital inputs at 0V or VDD
0.4
2
FA
50
MHz
TIMING CHARACTERISTICS (Notes 5 and 6) (Figures 1 and 2)
Serial Clock Frequency
fSCLK
0
SCLK Pulse-Width High
tCH
8
ns
SCLK Pulse-Width Low
tCL
8
ns
CS Fall to SCLK Fall Setup Time
tCSS0
8
ns
CS Fall to SCLK Fall Hold Time
tCSH0
0
ns
CS Rise to SCLK Fall Hold Time
tCSH1
0
ns
CS Rise to SCLK Fall
tCSA
SCLK Fall to CS Fall
DIN to SCLK Fall Setup Time
tCSF
100
ns
tDS
5
ns
DIN to SCLK Fall Hold Time
tDH
4.5
ns
CS Pulse-Width High
tCSPW
20
ns
CLR Pulse-Width Low
tCLPW
20
ns
tCSC
20
ns
CLR Rise to CS Fall
Note
Note
Note
Note
Note
2:
3:
4:
5:
6:
12
ns
Static accuracy tested without load.
Linearity is tested within 20mV of GND and VDD.
Gain and offset is tested within 100mV of GND and VDD.
Guaranteed by design; not production tested.
All timing specifications measured with VIL = VGND, VIH = VDD.
_______________________________________________________________________________________ 3
MAX5214/MAX5216
ELECTRICAL CHARACTERISTICS (continued)
MAX5214/MAX5216
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
DIN
DIN15
DIN14
DIN13
DIN12
tDS
SCLK
1
tCSH0
2
DIN11
4
DIN9
DIN8
6
7
8
DIN2
5
14
DIN0
DIN15
tCL
CS
15
16
1
tCSA
tCH1
tCH
tCSS0
DIN1
tCP
tDH
3
DIN10
tCSF
tCSPW
CLR
tCLPW
tCSC
Figure 1. 16-Bit Serial-Interface Timing Diagram (MAX5214)
DIN
DIN23
DIN22
DIN21
DIN20
tDS
SCLK
1
2
DIN19
tDH
3
4
5
tCSS0
CS
DIN17
DIN16
DIN2
6
7
8
22
DIN1
DIN0
23
24
1
tCL
tCSPW
tCSF
CLR
tCLPW
DIN23
tCH1
tCSA
tCH
tCSH0
DIN18
tCP
tCSC
Figure 2. 24-Bit Serial-Interface Timing Diagram (MAX5216)
4 _______________________________________________________________________________________
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
0.6
2.0
0.4
1.00
0.50
0
-0.2
INL (LSB)
0.2
0
0
MIN
-0.50
-0.6
-2.0
-0.75
-0.8
-1.0
-1.00
-3.0
4096
8192
12,288
16,384
16,384
0
32,768
49,152
3.2
2.7
65,536
3.7
4.2
4.7
DIGITAL INPUT CODE (LSB)
SUPPLY VOLTAGE (V)
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
1.00
MAX5214 toc02b
MAX5216
2
0.75
0.50
MAX
INL (LSB)
1
0
MIN
-1
MAX5214
VDD = 5V
3
0
MAX
1
MAX
0.25
MAX5216
VDD = 5V
2
INL (LSB)
3
MIN
-0.25
5.2
MAX5214 toc03b
DIGITAL INPUT CODE (LSB)
MAX5214 toc03a
0
INL (LSB)
MAX
0.25
-0.25
-1.0
-0.4
MAX5214
0.75
1.0
INL (LSB)
INL (LSB)
MAX5216
VDD = 5V
MAX5214 toc02a
MAX5214
VDD = 5V
0.8
3.0
MAX5214 toc01a
1.0
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5214 toc01b
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
0
MIN
-1
-0.50
-1.00
-3
SUPPLY VOLTAGE (V)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
3.7
4.2
4.7
MAX5214
VDD = 5V
0.4
5.2
0.5
0.3
-20
0
80
MAX5216
VDD = 5V
0.4
-3
100
-40
0.3
INL (LSB)
0.1
INL (LSB)
0.2
0.1
0
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.3
-0.4
-0.4
-0.4
-0.5
-0.5
8192
12,288
DIGITAL INPUT CODE (LSB)
16,384
100
MAX
0
-0.2
4096
80
0.3
0.1
0
20
40
60
TEMPERATURE (°C)
MAX5214
0.4
0.2
-0.1
0
0.5
0.2
0
-20
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5214 toc04b
0.5
-40
20 40 60
TEMPERATURE (°C)
3.2
MAX5214 toc04a
2.7
INL (LSB)
-2
-0.75
MAX5214 toc05a
-2
MIN
-0.5
0
16,384
32,768
49,152
DIGITAL INPUT CODE (LSB)
65,536
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________ 5
MAX5214/MAX5216
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
0.3
0.3
0
MIN
0.2
0.1
MAX
0
-0.1
MIN
-0.2
0
-0.1
-0.3
-0.4
-0.4
-0.4
-0.5
-0.5
-0.5
3.7
4.2
4.7
-0.3
-40
5.2
-20
0
OFFSET ERROR vs. SUPPLY VOLTAGE
40
60
80
-40
100
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX5216
1.00
OFFSET ERROR (mV)
1.00
0.75
0.50
0.25
0
0.75
0.50
4.2
4.7
5.2
60
80
0.75
0.50
0
2.7
3.2
3.7
4.2
4.7
5.2
-40
-20
0
20
40
60
80
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OFFSET ERROR vs. TEMPERATURE
FULL-SCALE OUTPUT
vs. SUPPLY VOLTAGE
FULL-SCALE OUTPUT
vs. SUPPLY VOLTAGE
0.60
0.40
2.4991
2.4989
2.4987
0.20
0
-20
0
20
40
60
TEMPERATURE (°C)
80
100
100
MAX5214 toc09b
MAX5216
VREF = 2.5V
2.4993
OUTPUT VOLTAGE (V)
0.80
MAX5214
VREF = 2.5V
2.4993
2.4995
MAX5214 toc09a
MAX5214 toc08b
2.4995
OUTPUT VOLTAGE (V)
1.00
100
MAX5214
VDD = 5V
SUPPLY VOLTAGE (V)
MAX5216
VDD = 5V
-40
40
0.25
0
3.7
20
1.00
0.25
3.2
0
OFFSET ERROR vs. TEMPERATURE
1.25
OFFSET ERROR (mV)
MAX5214
2.7
-20
TEMPERATURE (°C)
1.25
MAX5214 toc07a
1.25
1.20
20
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
MAX5214 toc07b
3.2
MIN
-0.2
-0.3
2.7
MAX
0.1
MAX5214 toc08a
-0.1
-0.2
OFFSET ERROR (mV)
0.3
INL (LSB)
INL (LSB)
MAX
0.1
MAX5216
VDD = 5V
0.4
0.2
0.2
INL (LSB)
MAX5214
VDD = 5V
0.4
0.5
MAX5214 toc06a
MAX5216
0.4
0.5
MAX5214 toc05b
0.5
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5214 toc06b
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
OFFSET ERROR (mV)
MAX5214/MAX5216
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
2.4991
2.4989
2.4987
2.4985
2.4985
2.7
3.2
3.7
4.2
SUPPLY VOLTAGE (V)
4.7
2.7
3.2
3.7
4.2
SUPPLY VOLTAGE (V)
6 _______________________________________________________________________________________
4.7
5.2
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
FULL-SCALE OUTPUT vs. TEMPERATURE
2.4984
2.4982
MAX5216
VDD = 5V
2.4913
OUTPUT VOLTAGE (V)
2.4986
MAX5214 toc10b
MAX5214
VDD = 5V
2.4988
2.4911
2.4909
2.4907
2.4980
-40
-20
0
20
40
60
80
100
2.4905
-40
-20
0
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
78
VDD = 5.25V
74
72
70
68
66
64
62
60
VDD = 2.7V
VDD = 4V
MAX5214
NO LOAD
VDD = VREF
VOUT = MIDSCALE
-40
-20
0
20
80
VDD = 5V
76
70
68
66
60
100
VDD = 2.7V
MAX5216
NO LOAD
VDD = VREF
VOUT = MIDSCALE
-40
-20
0
60
55
45
MAX5214
NO LOAD
VDD = VREF
VOUT = ZEROSCALE
40
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
80
100
MAX5214 toc11d
MAX5214 toc11c
VDD = 5.25V
VDD = 4V
VDD = 2.7V
60
80
75
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
75
50
40
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
65
20
VDD = 4V
TEMPERATURE (°C)
80
VDD = 5V
VDD = 5.25V
72
TEMPERATURE (°C)
70
100
74
64
60
80
78
62
40
60
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
VDD = 5V
40
80
MAX5214 toc11a
80
76
20
TEMPERATURE (°C)
MAX5214 toc11b
OUTPUT VOLTAGE (V)
FULL-SCALE OUTPUT vs. TEMPERATURE
2.4915
MAX5214 toc10a
2.4990
70
65
VDD = 4V
VDD = 5.25V
VDD = 5V
60
55
MAX5216
NO LOAD
VDD = VREF
VOUT = ZEROSCALE
50
VDD = 2.7V
45
40
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
_______________________________________________________________________________________ 7
MAX5214/MAX5216
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT (µA)
76
74
MAX5214
72
70
68
MAX5216
66
64
NO LOAD
VDD = VREF
VOUT = ZEROSCALE
75
SUPPLY CURRENT (µA)
NO LOAD
VDD = VREF
VOUT = MIDSCALE
78
80
MAX5214 toc12a
80
MAX5214 toc12b
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
70
65
MAX5214
60
55
MAX5216
50
45
62
40
60
2.7
3.2
3.7
4.2
4.7
2.7
5.2
3.2
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(POWER-DOWN MODE)
VOUT vs. TIME
(EXITING POWER-DOWN MODE)
NO LOAD
1.20
TA = +25°C
1.00
MAX5216
RL = 10kI
VDD = 5V
VREF = 5V
TA = -40°C
0.80
5.2
MAX5214 toc14a
MAX5214 toc13
1.40
SUPPLY CURRENT (µA)
MAX5214/MAX5216
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
TA = +105°C
OUT = MIDSCALE
1V/div
TA = +85°C
0.60
TA = 0°C
0.40
0V
0.20
0
2.7
3.2
3.7
4.2
4.7
5.2
10µs/div
SUPPLY VOLTAGE (V)
VOUT vs. TIME
(EXITING POWER-DOWN MODE)
MAJOR CODE TRANSITION
(0x8000 TO 0x7FFF)
MAX5214 toc15a
MAX5214 toc14b
MAX5216
VDD = 5V
NO LOAD
REF = 5V
MAX5214
RL = 10kI
VDD = 5V
VREF = 5V
OUT = MIDSCALE
1V/div
OUT = MIDSCALE
AC-COUPLED
1mV/div
0V
10µs/div
4µs/div
8 _______________________________________________________________________________________
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
MAJOR CODE TRANSITION
(0x3FFF TO 0x8000)
MAJOR CODE TRANSITION
(0x2000 TO 0x1FFF)
MAX5214 toc15b
MAX5214 toc15c
MAX5216
VDD = 5V
REF = 5V
NO LOAD
MAX5214
VDD = 5V
REF = 5V
NO LOAD
OUT = MIDSCALE
AC-COUPLED
OUT = MIDSCALE
AC-COUPLED
1mV/div
1mV/div
4µs/div
4µs/div
MAJOR CODE TRANSITION
(0x1FFF TO 0x2000)
SETTLING TIME HIGH
MAX5214 toc16a
MAX5214 toc15d
MAX5216
VDD = 5V
REF = 5V
MAX5214
VDD = 5V
REF = 5V
NO LOAD
OUT = MIDSCALE
AC-COUPLED
1.25V
1mV/div
2µs/div
4µs/div
SETTLING TIME LOW
SETTLING TIME HIGH
MAX5214 toc16b
MAX5216
VDD = 5V
REF = 5V
MAX5214 toc16c
MAX5214
VDD = 5V
REF = 5V
3.75V
3.75V
1.25V
1.25V
2µs/div
3.75V
2µs/div
_______________________________________________________________________________________ 9
MAX5214/MAX5216
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
SETTLING TIME LOW
DIGITAL FEEDTHROUGH
MAX5214 toc16d
MAX5214 toc17
MAX5214
VDD = 5V
REF = 5V
VOUT
AC-COUPLED
1mV/div
3.75V
1.25V
2µs/div
40ns/div
OUTPUT VOLTAGE
vs. OUTPUT CURRENT
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
3500
2.50
DIGITAL SUPPLY CURRENT (µA)
MAX5214 toc18
2.55
2.45
2.40
2.35
2.30
VDD = 5V
VREF = 5V
3000
VDD = 5V
LOW T0 HIGH
2500
VDDI = 5V
HIGH T0 LOW
2000
1500
VDDI = 2.7V
LOW T0 HIGH
1000
VDDI = 2.7V
HIGH T0 LOW
MAX5214 toc19
VSCLK
5V/div
OUTPUT VOLTAGE (V)
500
0
2.25
0
1
2
3
4
5
0
6
1
2
3
4
5
DIGITAL INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
REFERENCE INPUT BANDWIDTH
vs. FREQUENCY
MAX5214 toc20
5
0
ATTENUATION (dB)
MAX5214/MAX5216
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
-5
-10
-15
-20
1
10
100
1000
INPUT FREQUENCY (kHz)
10 �������������������������������������������������������������������������������������
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
TOP VIEW
REF 1
CS 2
SCLK
3
MAX5214
MAX5216
DIN 4
8
GND
7
VDD
6
OUT
5
CLR
µMAX
Pin Description
PIN
NAME
1
REF
FUNCTION
2
3
CS
SCLK
4
DIN
Data In
5
CLR
Active-Low Asynchronous Digital-Clear Input. Drive CLR low to clear the contents of the input and
DAC registers and set the DAC output to zero.
6
OUT
Buffered DAC Output
7
VDD
Supply Voltage. Bypass VDD with a 0.1FF capacitor to GND.
8
GND
Ground
Reference Voltage Input. Bypass REF with a 0.1FF capacitor to GND.
Active-Low Chip-Select Input
Serial-Clock Input
Detailed Description
The MAX5214/MAX5216 are pin-compatible and software-compatible 14-bit and 16-bit DACs. The MAX5214/
MAX5216 are single-channel, low-power, high-reference input resistance, and buffered voltage-output
DACs. The MAX5214/MAX5216 minimize the digital
noise feedthrough from their inputs to their outputs by
powering down the SCLK and DIN input buffers after
completion of each data frame. The data frames are
16-bit for the MAX5214 and 24-bit for the MAX5216. On
power-up, the MAX5214/MAX5216 reset the DAC output
to zero, providing additional safety for applications that
drive valves or other transducers which need to be off on
power-up. The MAX5214/MAX5216 contain a segmented
resistor string-type DAC, a serial-in/parallel-out shift register, a DAC register, power-on-reset (POR) circuit, CLR
to asynchronously clear the device independent of the
serial interface, and control logic. On the falling edge
of the clock (SCLK) pulse, the serial input (DIN) data is
shifted into the device, MSB first.
Output Amplifier (OUT)
The MAX5214/MAX5216 include an internal buffer on the
DAC output. The internal buffer provides improved load
regulation and transition glitch suppression for the DAC
output. The output buffer slews at 0.5V/Fs and drives
up to 10kI in parallel with 100pF. The analog supply
voltage (VDD) determines the maximum output voltage
range of the device as VDD powers the output buffer.
DAC Reference (REF)
The external reference input features a typical input
impedance of 256kI and accepts an input voltage
from +2V to VDD. Connect an external voltage supply
between REF and GND to apply an external reference.
Visit www.maxim-ic.com/products/references for a list
of available voltage-reference devices.
______________________________________________________________________________________ 11
MAX5214/MAX5216
Pin Configuration
MAX5214/MAX5216
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
Serial Interface
transfers its contents to the input registers after loading
16/24 bits of data and updates the DAC output immediately after the data is received on the 16-/24-bit falling
edge of the clock. To initiate a new data transfer, drive
CS high and keep CS high for a minimum of 20ns before
the next write sequence. The SCLK can be either high or
low between CS write pulses. Figures 1 and 2 show the
timing diagram for the complete 3-wire serial interface
transmission. The MAX5216 DAC code is unipolar binary
with VOUT = (code/65,535) x VREF. The MAX5214 DAC
code is unipolar binary with VOUT = (code/16,383) x
VREF. See Tables 1 and 2.
The MAX5214/MAX5216 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSP. The
interface provides three inputs: SCLK, CS, and DIN. The
chip-select input (CS) frames the serial data loading at
DIN. Following a chip-select input high-to-low transition,
the data is shifted synchronously and latched into the
input register on each falling edge of the serial-clock
input (SCLK). Each serial word is 16-bit for the MAX5214
and 24-bit for the MAX5216. The first 2 bits are the
control bits followed by 14 data bits (MSB first) for the
MAX5214 and 22 data bits (MSB first) for the MAX5216
as shown in Tables 1 and 2. The serial input register
Table 1. Operating Mode Truth Table (MAX5214)
16-BIT WORD
CONTROL
BITS
DATA BITS
MSB
FUNCTION
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No operation
1
0
0
X
A1
A0
X
X
X
X
X
X
X
X
X
X
Power-down
(see Table 3)
0
1
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Write through
1
1
Reserved, Do Not Use
Table 2. Operating Mode Truth Table (MAX5216)
24-BIT WORD
CONTROL
BITS
DATA BITS
MSB
LSB
D23
D22
0
0
1
0
0
1
1
1
FUNCTION
D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10
X
0
X
X
X
A1
X
A0
X
X
X
X
B15 B14 B13 B12 B11 B10
X
X
X
X
X
X
D9
D8
D7
D6
D5–
D0
X
X
X
X
X
No operation
X
X
X
X
X
X
X
X
X
X
X
Power-down
(see Table 3)
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
Write through
Reserved, Do Not Use
12 �������������������������������������������������������������������������������������
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
2) Clock 16/24 bits of data into DIN (MSB first and LSB
last), observing the specified setup and hold times.
3) After clocking in the last data bit, drive CS high. CS
must remain high for 20ns before the next transmission is started.
Figure 1 shows a write operation for the transmission of
16 bits. If CS is driven high at any point prior to receiving
16 bits, the transmission is discarded.
Figure 2 shows a write operation for the transmission of
24 bits. If CS is driven high at any point prior to receiving
24 bits, the transmission is discarded.
Clear (CLR)
The MAX5214/MAX5216 feature an asynchronous activelow CLR logic input that sets the DAC output to zero.
Driving CLR low clears the contents of both the input and
DAC registers and also aborts the on-going SPI command. To allow a new SPI command, drive CLR high.
Power-Down Mode
The MAX5214/MAX5216 feature a software-controlled
power-down mode. In power-down, the output disconnects from the buffer and is grounded with one of the
three selectable internal resistors. See Table 3 for the
selectable internal resistor values in power-down mode.
The selected mode takes effect on the 16th SCLK falling
edge of the MAX5214 and 24th SCLK falling edge of the
MAX5216. The serial interface remains active in powerdown mode. In order to abort the power-down mode
selection, pull CS high prior to the 16th (MAX5214) or
24th (MAX5216) SCLK falling edge. The contents of the
DAC register remain valid while in power-down mode,
allowing for the DAC to return to previous code by writing
0x8000 for the MAX5214 or 0x800000 for the MAX5216
(Table 3). A write to the write-through register causes the
device to immediately exit power-down mode and transition to the requested code (see Tables 1 and 2).
Table 3. Power-Down Modes
DAC OPERATION
CONDITION
A1
A0
DESCRIPTION
0
0
DAC powers up and returns to its previous code setting.
0
1
DAC powers down; OUT is high impedance.
1
0
DAC powers down; OUT connects to ground through an internal 100kI resistor.
1
1
DAC powers down; OUT connects to ground through an internal 1kI resistor.
Normal operation
Power-down
Table 4. MAX5216 Input Code vs. Output Voltage
DAC LATCH CONTENTS
MSB g LSB
ANALOG OUTPUT (VOUT)
1111 1111 1111 1111
VREF x (65,535/65,535)
1000 0000 0000 0000
VREF x (32,768/65,535) = 1/2 VREF
0000 0000 0000 0001
VREF x (1/65,535)
0000 0000 0000 0000
0V
Table 5. MAX5214 Input Code vs. Output Voltage
DAC LATCH CONTENTS
MSB g LSB
ANALOG OUTPUT (VOUT)
1111 1111 1111 11XX
VREF x (16,383/16,383)
1000 0000 0000 00XX
0000 0000 0000 01XX
VREF x (8,192/16,383) = 1/2 VREF
VREF x (1/16,383)
0000 0000 0000 00XX
0V
______________________________________________________________________________________ 13
MAX5214/MAX5216
Writing to the Devices
1) Drive CS low, enabling the shift register.
MAX5214/MAX5216
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
Applications Information
Power-On Reset (POR)
When first power is applied to VDD, the input registers
are set to zero so the DAC output is set to code zero.
To optimize DAC linearity, wait until the supplies have
settled. The MAX5214/MAX5216 output voltage range is
0 to VREF.
Power Supplies and
Bypassing Considerations
Bypass VDD with high-quality 0.1µF ceramic capacitors to a
low-impedance ground as close as possible to the device.
Minimize lead lengths to reduce lead inductance.
Connect the GND to the analog ground plane.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to the star ground for the
DAC system. Refer the remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5214/MAX5216 GND.
Carefully lay out the traces between channels to reduce
AC cross-coupling. Do not use wire-wrapped boards
and sockets. Use shielding to improve noise immunity.
Do not run analog and digital signals parallel to one
another, especially clock signals. Avoid routing digital
lines underneath the MAX5214/MAX5216 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Offset Error
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified
is at or near the zero-scale point of the transfer function.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from
the start of a transition, until the DAC output settles to
the new output value within the converter’s specified
accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines
are toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
Digital-to-Analog Power-Up Glitch Impulse
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL is
greater than -1 LSB, the DAC guarantees no missing
codes and is monotonic.
14 �������������������������������������������������������������������������������������
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
POWER SUPPLY
IN
100pF
100nF
MAX6029
OUT
4.7µF
VDD
OUT
DAC
µC
OUTPUT
CLR
CS
SCLK
MAX5214
MAX5216
REF
DIN
GND
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 FMAX
U8+3
21-0036
90-0092
______________________________________________________________________________________ 15
MAX5214/MAX5216
Typical Operating Circuit
MAX5214/MAX5216
14-/16-Bit, Low-Power,
High-Performance, Buffered Single DACs
Revision History
REVISION
NUMBER
REVISION
DATE
0
12/10
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
© 2010
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