19-3586; Rev 0; 2/05 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface The MAX5115/MAX5116 quad, 8-bit, digital-to-analog converters (DACs) feature nonvolatile registers. These nonvolatile registers store the DAC operating modes and output states, allowing the DACs to initialize to specified configurations at power-up. Precision on-chip output buffers swing rail-to-rail, and provide 8µs settling time. The I2C*-compatible, 2-wire serial interface allows for a maximum clock frequency of 400kHz. The MAX5115 has independent high and low reference inputs allowing maximum output voltage range flexibility. The MAX5116 has single high and low reference inputs for all DACs to minimize trace count and save board space. The reference rails accept voltage inputs that range from ground to the positive supply rail. The devices operate from a single +2.7V to +5.25V supply and consume 200µA per DAC. A software-controlled power-down mode decreases supply current to less than 25µA. A software-controlled mute mode sets each DAC, or both DACs simultaneously, to their respective REFL_ voltages. The MAX5116 also includes an asynchronous MUTE input, that drives all DAC outputs simultaneously to their respective REFL_ voltages. The MAX5115 is available in a 20-pin QSOP, and the MAX5116 is available in a 16-pin QSOP package. Both devices are specified for operation over the extended (-40°C to +85°C) temperature range. Features ♦ Nonvolatile Registers Initialize DACs to Stored States ♦ +2.7V to +5.25V Single-Supply Operation ♦ Quad 8-Bit DACs with Independent High and Low Reference Inputs ♦ Rail-to-Rail Output Buffers ♦ Low 200µA per DAC Supply Current ♦ Power-Down Mode Reduces Supply Current to 25µA (max) ♦ 400kHz, I2C-Compatible, 2-Wire Serial Interface ♦ Asynchronous MUTE Input (MAX5116) ♦ Small 16-/20-Pin QSOP Packages Ordering Information PART TEMP RANGE PINPACKAGE REFERENCE INPUTS MAX5115EEP -40°C to +85°C 20 QSOP 4 MAX5116EEE -40°C to +85°C 16 QSOP 1 Simplified Diagram VDD MAX5116 REFH DAC0 NONVOLATILE/ VOLATILE REGISTERS DAC0 DAC1 NONVOLATILE/ VOLATILE REGISTERS DAC1 DAC2 NONVOLATILE/ VOLATILE REGISTERS DAC2 DAC3 NONVOLATILE/ VOLATILE REGISTERS DAC3 OUT0 Applications Digital Gain and Offset Adjustments Programmable Attenuators Portable Instruments SCL SDA A3 Power-Amp Bias Control A2 ATE Calibration A1 A0 Laser Biasing Pin Configuration and Typical Operating Circuit appear at end of data sheet. 2-WIRE SERIAL INTERFACE/ CONTROL OUT1 OUT2 MUTE GND OUT3 REFL *Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associate Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification defined by Philips. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5115/MAX5116 General Description MAX5115/MAX5116 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND, unless otherwise noted.) VDD, A0, A1, A2, A3, SCL, SDA, MUTE.................-0.3V to +6.0V OUT0, OUT1, OUT2, OUT3, REFH0, REFH1, REFH2, REFH3, REFH, REFL0, REFL1, REFL2, REFL3, REFL .......................................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................±50mA Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW 20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature .....................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.25V, GND = 0, REFH_ = VDD, REFL_ = GND, RLOAD = 5kΩ, CL = 100pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution 8 Integral Nonlinearity INL Differential Nonlinearity (Note 2) DNL Offset Error ZCE Code range 0A hex to F0 hex ±2 Code range 0A hex to F0 hex ±0.5 Full code range ±1 Code = 0A hex Code = 0A hex Gain Error Code = F0 hex (Note 3) Gain-Error Temperature Coefficient Code = F0 hex PSRR ±1 Full code range Offset Temperature Coefficient Power-Supply Rejection Ratio Bits ±20 ±20 LSB mV µV/°C ±1 ±0.002 Code = FF hex or 0A hex, VREFH_ = 2.5V, VREFL_ = 0, f = DC LSB LSB LSB/°C 1 LSB/V VDD V REFERENCE INPUT (REFH_, REFL_, REFH, REFL) Input Voltage Range VREFH_, VREFL_ Input Resistance VREFH_ ≥ VREFL_ 0 MAX5115 320 460 600 MAX5116 80 115 150 Input-Resistance Temperature Coefficient Input Capacitance kΩ ±35 ppm/°C 10 pF DAC OUTPUTS (OUT_) Load Regulation Code = F0 hex, RLOAD ≥ 5kΩ Output Leakage DAC powered down, not muted Amplifier Output Resistance 0.5V ≤ VOUT_ ≤ (VDD - 0.5V) ±0.5 0.5 ±1 LSB ±10 µA Ω DIGITAL INPUTS (A_, MUTE) Input High Voltage (Note 4) 2 VIH 2.7V ≤ VDD < 3.6V 0.7 x VDD 3.6V ≤ VDD ≤ 5.25V 2.52 _______________________________________________________________________________________ V Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface (VDD = +2.7V to +5.25V, GND = 0, REFH_ = VDD, REFL_ = GND, RLOAD = 5kΩ, CL = 100pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25°C.) (Note 1) PARAMETER Input Low Voltage (Note 4) SYMBOL VIL CONDITIONS MIN TYP 2.7V ≤ VDD < 3.6V 3.6V ≤ VDD ≤ 5.25V Input Hysteresis IIN Input Capacitance CIN UNITS 0.3 x VDD V 1.1 0.05 x VDD VHYS Input Leakage Current MAX VIN = 0 or VDD V ±1 10 µA pF DIGITAL OUTPUT (SDA) Output Low Voltage VOL Tri-State Leakage ISINK = 3mA 0.4 ISINK = 6mA 0.6 IL Tri-State Output Capacitance ±1 COUT V µA 15 pF 8 µs dB DYNAMIC PERFORMANCE SCL to OUT_ Settling tCOS (Note 5) Crosstalk (Note 6) 55 Multiplying Signal-to-Noise Plus Distortion VREFH_ = 2.5VP-P at 1kHz 65 VREFH_ = 2.5VP-P at 10kHz 52 Multiplying Bandwidth VREFH_ = 0.5VP-P, 3dB bandwidth 325 Reference Feedthrough VREFH_ = 2.5VP-P at 10kHz (Note 7) 88 dB 2.5 nVs 800 nV/√Hz 4 µs 1.5 µs SINAD Clock Feedthrough Output Noise eN Power-Up Time tSDR Power-Down Time tSDN From power-down state dB kHz INTERFACE PORTS (SCL, SDA) 0.3 x VDD VIL Input Voltage VIH Input Hysteresis 0.05 x VDD VHYS Input Current IIN Input Capacitance CIN V 0.7 x VDD V ±1 5 µA pF POWER SUPPLIES Power-Supply Voltage VDD Supply Current IDD Power-Down Current 2.70 ILOAD = 0, digital inputs at GND or VDD Normal operation During nonvolatile write 5.25 0.8 V 1.3 2 25 mA µA _______________________________________________________________________________________ 3 MAX5115/MAX5116 ELECTRICAL CHARACTERISTICS (continued) MAX5115/MAX5116 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.25V, GND = 0, REFH_ = VDD, REFL_ = GND, RLOAD = 5kΩ, CL = 100pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz DIGITAL TIMING (Figure 4, Note 8) SCL Clock Frequency fSCL Setup Time for START Condition tSU:STA 0.6 µs Hold Time for START Condition tHD:STA 0.6 µs SCL High Time tHIGH 0.6 µs SCL Low Time tLOW 1.3 µs Data Setup Time tSU:DAT 100 Data Hold Time tHD:DAT 0 SDA, SCL Rise Time SDA, SCL Fall Time ns tR tF 0.9 µs 300 ns 300 ns Setup Time for STOP Condition tSU:STO 0.6 µs Bus Free Time Between a STOP and START Condition tBUF 1.3 µs Pulse Width of Spike Suppressed tSP Maximum Capacitive Load for Each Bus Line CB Write NV Register Busy Time 50 (Note 9) 400 (Note 10) ns pF 15 ms NONVOLATILE MEMORY RELIABILITY Data Retention Endurance TA= +85°C 50 TA= +25°C 200,000 TA= +85°C 50,000 Years Stores Note 1: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design. Note 2: Guaranteed monotonic. Note 3: Gain error is defined as: 256 × (VF0,Meas − ZCE − VF0,Ideal ) VREFH _ where VF0,Meas is the DAC voltage with input code F0 hex and VF0,Ideal is the ideal DAC voltage with input code F0 hex or (VREFH - VREFL) x (240 / 256) + VREFL. Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND + 0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 5: Output settling time is measured from the 50% point of the rising edge of the last SCL of the data byte to 0.5 LSB of OUT_’s final value for a code transition from 10 hex to F0 hex. Note 6: Crosstalk is defined as the coupling from a DAC switching from code 00 hex to code FF hex to any other DAC that is in a steady state at code 00 hex. Note 7: Reference feedthrough is defined as the coupling from one driven reference with input code = FF hex to any other DAC output with the reference of the DAC at a constant value and input code = 00 hex. Note 8: SCL clock period includes rise and fall times tR and tF. All digital input signals are specified with tR = tF = 2ns and timed from a voltage level of (VIL + VIH) / 2. Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf. Note 10: The busy time begins from the initiation of the stop pulse. 4 _______________________________________________________________________________________ Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface INTEGRAL NONLINEARITY vs. INPUT CODE 0.5 0 -0.5 1.50 1.25 1.00 0.75 0.50 1.75 0 64 128 0.75 0.50 2.5 3.0 3.5 4.0 4.5 5.0 -40 5.5 -15 10 35 60 SUPPLY VOLTAGE (V) TEMPERATURE (°C) DIFFERENTIAL NONLINEARITY vs. INPUT CODE DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. TEMPERATURE 0.25 0 -0.25 -0.50 -0.75 -1.00 64 128 -0.75 -1.00 -1.25 -1.50 256 192 -0.50 MAX5115/5116 toc06 -0.9 -1.0 -1.1 -1.2 2.5 3.0 INPUT CODE 3.5 4.0 4.5 5.0 5.5 -40 -15 SUPPLY VOLTAGE (V) OFFSET ERROR vs. SUPPLY VOLTAGE 0.2 35 60 85 GAIN ERROR vs. SUPPLY VOLTAGE MAX5115/5116 toc08 -0.06 0.35 -0.08 GAIN ERROR (LSB) 0.3 0.40 OFFSET ERROR (LSB) 0.4 10 TEMPERATURE (°C) OFFSET ERROR vs. TEMPERATURE MAX5115/5116 toc07 0.5 85 0.30 MAX5115/5116 toc09 0 -0.25 -0.8 DIFFERENTIAL NONLINEARITY (LSB) 0.50 0 MAX5115/5116 toc05 0.75 DIFFERENTIAL NONLINEARITY (LSB) MAX5115/5116 toc04 DIFFERENTIAL NONLINEARITY (LSB) 1.00 INPUT CODE 1.00 OFFSET ERROR (LSB) 1.25 0 0 256 192 1.50 0.25 0.25 -1.0 MAX5115/5116 toc03 1.75 2.00 INTEGRAL NONLINEARITY (LSB) 1.0 MAX5115/5116 toc02 1.5 2.00 INTEGRAL NONLINEARITY (LSB) MAX5115/5116 toc01 2.0 INTEGRAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY vs. TEMPERATURE INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE -0.10 -0.12 -0.14 -0.16 0.25 -0.18 0.1 -0.20 0.20 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 -40 -15 10 35 TEMPERATURE (°C) 60 85 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 MAX5115/MAX5116 Typical Operating Characteristics (VDD = +3V, VREFH_ = +3V, VREFL_ = GND, RL = 5kΩ, CL = 100pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +3V, VREFH_ = +3V, VREFL_ = GND, RL = 5kΩ, CL = 100pF, TA = +25°C, unless otherwise noted.) OFFSET OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT -0.12 -0.14 -0.16 -0.18 0.35 0.30 VDD = VREFH_ = 5V 0.25 0.20 VDD = VREFH_ = 3V -0.20 5.0 0.15 -15 10 35 60 85 VDD = VREFH_ = 5V 4.0 3.5 VDD = VREFH_ = 3V 3.0 2.5 2.0 0 2 4 6 8 10 0 3 6 9 12 TEMPERATURE (°C) OUTPUT SINK CURRENT (mA) OUTPUT SOURCE CURRENT (mA) SUPPLY CURRENT vs. INPUT CODE SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE SUPPLY CURRENT vs. TEMPERATURE NO LOAD 750 SUPPLY CURRENT (µA) 700 NO LOAD VDD = VREFH = +5V 650 600 550 700 NO LOAD 650 A 600 15 MAX5115/5116 toc15 1000 MAX5115 toc13 800 SUPPLY CURRENT (µA) -40 4.5 MAX5115/5116 toc12 MAX5115/5116 toc11 VREFL_ = 0.2V MAX5115/5116 toc14 GAIN ERROR (LSB) -0.10 0.40 OFFSET OUTPUT VOLTAGE (V) MAX5115/5116 toc10 -0.08 FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT FULL-SCALE OUTPUT VOLTAGE (V) GAIN ERROR vs. TEMPERATURE SUPPLY CURRENT (µA) MAX5115/MAX5116 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface B 550 C D 500 500 450 100 400 0 64 128 INPUT CODE 192 256 450 0 1 2 3 DIGITAL INPUT VOLTAGE (V) 4 5 -40 -15 10 35 60 TEMPERATURE (°C) A: VDD = 5V, VREFH_ = 4.096V, CODE = FFh B: VDD = 5V, VREFH_ = 4.096V, CODE = 00h C: VDD = 3V, VREFH_ = 2.5V, CODE = FFh D: VDD = 3V, VREFH_ = 2.5V, CODE = 00h 6 _______________________________________________________________________________________ 85 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface 650 TA = -40°C 625 600 575 VDD = 5V CODE = FFh TA = +85°C 550 600 550 VDD = 5V CODE = 00h 500 VDD = 3V CODE = 00h VDD = 3V CODE = FFh 450 525 -40 -50 REFERENCE FEEDTHROUGH (dB) 650 NO LOAD MAX5115/5116 toc17 NO LOAD CODE = 00h SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 700 MAX5115/5116 toc16 700 675 REFERENCE FEEDTHROUGH vs. FREQUENCY (MAX5115) SUPPLY CURRENT vs. REFERENCE VOLTAGE -60 -70 MAX5115/5116 toc18 SUPPLY CURRENT vs. SUPPLY VOLTAGE MEASURED AT OUT1, VREFL1 = VREFL0 = GND, VREFH1 = VDD, VREFH0 = 2.5VP-P, SIGNAL CENTERED AT VDD/2, OUT0 = FFh, OUT1 = 00h, NO LOAD V = 5V DD -80 VDD = 3V -90 TA = +25°C 500 -100 400 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 SUPPLY VOLTAGE (V) STARTUP GLITCH 1 2 3 4 0.01 5 0.1 1 10 100 1000 10,000 100,000 REFERENCE VOLTAGE (V) FREQUENCY (kHz) POWER-DOWN TRANSITION POWER-UP TRANSITION MAX5115/5116 toc19 MAX5115/5116 toc20 MAX5115/5116 toc21 SCL 2V/div SCL 2V/div VDD 2V/div GND 26 MAX5115/MAX5116 Typical Operating Characteristics (continued) (VDD = +3V, VREFH_ = +3V, VREFL_ = GND, RL = 5kΩ, CL = 100pF, TA = +25°C, unless otherwise noted.) GND 25 26 GND 27 OUT_ 1V/div OUT_ 500mV/div OUT_ 500mV/div GND GND GND NV REGISTER PREVIOUSLY SET TO CODE FFh 100µs/div 1µs/div 400ns/div POSITIVE CARRY TRANSITION NEGATIVE CARRY TRANSITION MAX5115/5116 toc22 POSITIVE SETTLING TIME MAX5115/5116 toc23 MAX5115/5116 toc24 SCL 2V/div OUT_ 50mV/div AC-COUPLED OUT_ 50mV/div AC-COUPLED 25 26 GND 27 OUT_ 1V/div GND 4µs/div 2µs/div 2µs/div _______________________________________________________________________________________ 7 Typical Operating Characteristics (continued) (VDD = +3V, VREFH_ = +3V, VREFL_ = GND, RL = 5kΩ, CL = 100pF, TA = +25°C, unless otherwise noted.) 26 MAX5115/5116 toc27 MAX5115/5116 toc26 MAX5115/5116 toc25 25 OUTPUT CROSSTALK CLOCK FEEDTHROUGH NEGATIVE SETTLING TIME SCL 2V/div SCL 2V/div GND GND OUT_ 1V/div OUT_ 10mV/div AC-COUPLED 27 SCL 2V/div GND OUT0 2V/div GND GND OUT_ SET TO 7Fh 2µs/div OUT1 10mV/div AC-COUPLED OUT1 SET TO 7Fh 2µs/div 1µs/div Pin Description 8 MAX5116 PIN MAX5115 MAX5115/MAX5116 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 3 4 — — 6 — — 7 8 10 — — 11 — — 14 A2 A1 A0 REFH1 REFL1 OUT1 REFH2 REFL2 OUT2 GND OUT3 REFL3 REFH3 OUT0 REFL0 REFH0 SCL 18 15 VDD 19 20 — 16 1 5 SDA A3 N.C. — 9 MUTE Active-Low Mute Input. Connect MUTE low to drive all DAC outputs to their respective reference low voltages. Connect MUTE to VDD for normal operation. — — 12 13 REFL REFH DAC Low Reference Input. REFL must be equal to or less than REFH. DAC High Reference Input. REFH must be equal to or greater than REFL. NAME FUNCTION Address Select 2. Connect to VDD or GND to set the device address. Address Select 1. Connect to VDD or GND to set the device address. Address Select 0. Connect to VDD or GND to set the device address. DAC1 High Reference Input. REFH1 must be equal to or greater than REFL1. DAC1 Low Reference Input. REFL1 must be equal to or less than REFH1. DAC1 Output. OUT1 is buffered with a unity-gain amplifier. DAC2 High Reference Input. REFH2 must be equal to or greater than REFL2. DAC2 Low Reference Input. REFL2 must be equal to or less than REFH2. DAC2 Output. OUT2 is buffered with a unity-gain amplifier. Ground DAC3 Output. OUT3 is buffered with a unity-gain amplifier. DAC3 Low Reference Input. REFL3 must be equal to or less than REFH3. DAC3 High Reference Input. REFH3 must be equal to or greater than REFL3. DAC0 Output. OUT0 is buffered with a unity-gain amplifier. DAC0 Low Reference Input. REFL0 must be equal to or less than REFH0. DAC0 High Reference Input. REFH0 must be equal to or greater than REFL0. Serial-Clock Input. Connect SCL to VDD through a 2.4kΩ pullup resistor. Positive-Power Input. Connect VDD to a +2.7 to +5.25V power supply. Bypass VDD to GND with a 0.1µF capacitor as close to the device as possible. Serial Data Input/Output. Connect SDA to VDD through a 2.4kΩ pullup resistor. Address Select 3. Connect to VDD or GND to set the device address. No Connection. Not internally connected. _______________________________________________________________________________________ Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface MAX5115/MAX5116 VDD 18 16 REFH0 15 REFL0 MAX5115 DAC0 NONVOLATILE REGISTER DAC0 VOLATILE REGISTER DAC0 14 OUT0 4 REFH1 5 REFL1 SCL 17 SDA 19 A3 20 A2 1 DAC1 NONVOLATILE REGISTER DAC1 VOLATILE REGISTER DAC1 6 OUT1 2-WIRE SERIAL INTERFACE/ CONTROL A1 2 A0 3 7 REFH2 8 REFL2 DAC2 NONVOLATILE REGISTER DAC2 VOLATILE REGISTER DAC2 9 OUT2 13 REFH3 12 REFL3 DAC3 NONVOLATILE REGISTER DAC3 VOLATILE REGISTER DAC3 11 OUT3 POR 10 GND Figure 1. MAX5115 Functional Diagram _______________________________________________________________________________________ 9 MAX5115/MAX5116 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface VDD REFH 15 13 MAX5116 SCL 14 SDA 16 A3 1 A2 2 DAC0 NONVOLATILE REGISTER DAC0 VOLATILE REGISTER DAC0 DAC1 NONVOLATILE REGISTER DAC1 VOLATILE REGISTER DAC1 DAC2 NONVOLATILE REGISTER DAC2 VOLATILE REGISTER DAC2 DAC3 NONVOLATILE REGISTER DAC3 VOLATILE REGISTER DAC3 11 OUT0 6 OUT1 2-WIRE SERIAL INTERFACE/ CONTROL A1 3 A0 4 MUTE 9 7 OUT2 10 OUT3 POR 8 GND 12 REFL Figure 2. MAX5116 Functional Diagram 10 ______________________________________________________________________________________ Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface DAC Operation The MAX5115/MAX5116 use a DAC matrix decoding architecture that saves power. A resistor string divides the difference between the external reference voltages, VREFH_ and VREFL_. Row and column decoders select the appropriate tap from the resistor string, providing the equivalent analog voltage. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. Figure 3 shows a simplified diagram of one DAC. Output Buffer Amplifiers The MAX5115/MAX5116 analog outputs are internally buffered by a precision unity-gain amplifier. The outputs swing from GND to VDD with a VREFL_-to-VREFH_ output transition. The amplifier outputs typically settle to ±0.5 LSB in 8µs when loaded with 5kΩ in parallel with 100pF. REFH_ R0 R1 R15 D7 D6 D5 R16 MSB DECODER The MAX5115/MAX5116 8-bit DACs feature internal, nonvolatile registers that store the DAC states for initialization during power-up. These devices consist of resistor-string DACs, rail-to-rail output buffers, a shift register, power-on reset (POR) circuitry, and volatile and nonvolatile memory registers (Figures 1 and 2). The shift register decodes the control and address bits, routing the data to the proper registers. Writing data to a selected volatile register immediately updates the DAC outputs. The volatile registers retain data as long as the device is powered. Removing power clears the volatile registers. The nonvolatile registers retain data even after power is removed. On startup, when power is first applied, data from the nonvolatile registers is transferred to the volatile registers to automatically initialize the device. Read data from the nonvolatile or volatile registers using the 2-wire serial interface. D4 R255 REFL_ LSB DECODER D3 D2 D1 D0 DAC Figure 3. DAC Simplified Circuit Diagram DAC Registers The MAX5115/MAX5116 feature two registers per DAC, a volatile and a nonvolatile register, that store the DAC data. The volatile DAC register holds the current value of each DAC. Write data to the volatile registers directly from the 2-wire serial interface or by loading the previously stored data from the respective nonvolatile register. Clear the volatile registers by removing power to the device. The volatile registers are read/write. The nonvolatile register retains the DAC values even after power is removed. Read stored data using the 2wire serial interface. On power-up, the devices automatically initialize with data stored in the nonvolatile registers. The nonvolatile registers are read/write and programmed to all zeros at the factory. ______________________________________________________________________________________ 11 MAX5115/MAX5116 Detailed Description MAX5115/MAX5116 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface tR tF SDA tSU:DAT tHD:DAT tLOW tBUF tHD:STA tSU:STA tSU:STO SCL tHD:STA tHIGH tR tF S Sr ACK P S PARAMETERS ARE MEASURED FROM 30% TO 70%. Figure 4. 2-Wire Serial-Interface Timing Diagram Serial Interface The MAX5115/MAX5116 feature an I2C-compatible, 2wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX5115/MAX5116 and the master at rates up to 400kHz (Figure 4). The master (typically a microcontroller) initiates data transfer on the bus and generates SCL. SDA and SCL require pullup resistors (2.4kΩ or greater; see the Typical Operating Circuit). Optional resistors (24Ω) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot of the bus signals. I2C Compatibility The MAX5115/MAX5116 are compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open-drain output. The Typical Operating Circuit shows an I2C application. The communication protocol supports standard I2C 8-bit communications. The general call address is ignored, and CBUS formats are not supported. The devices’ addresses are compatible with 7-bit I2C addressing protocol only. No 10bit address formats are supported. Bit Transfer One data bit transfers during each SCL rising edge. Nine clock cycles are required to transfer the data into or out of the MAX5115/MAX5116. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are read as control signals (see the START and STOP Conditions section). Both SDA and SCL idle high. 12 S Sr P SDA SCL Figure 5. START and STOP Conditions START and STOP Conditions The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high. The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high (Figure 5). A START condition from the master signals the beginning of a transmission to the MAX5115/ MAX5116. The master terminates transmission by issuing a STOP condition. The STOP condition frees the bus. If a REPEATED START condition (Sr) is generated instead of a STOP condition, the bus remains active. Early STOP Conditions The MAX5115/MAX5116 recognize a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 6). This condition is not a legal I2C format. REPEATED START Conditions A REPEATED START (Sr) condition is used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5115/MAX5116 serial interface supports continuous write operations with an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow. ______________________________________________________________________________________ Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface Successful data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX5115/MAX5116 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 7). To generate a not acknowledge, the receiver allows SDA to be pulled Slave Address A master initiates communication with a slave device by issuing a START condition followed by a slave address (Figure 8). The slave address consists of 7 address bits and a read/write bit (R/W). When idle, the device continuously waits for a START condition followed by its slave address. When the device recognizes its slave address, it acquires the data byte and executes the command. The first 3 bits (MSBs) of the slave address have been factory programmed and are always 010. Connect A3–A0 to VDD or GND to program the remaining 4 bits of the slave address. The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX5115/MAX5116. (R/W = 0 selects a write condition. R/W = 1 selects a read condition.) After receiving the address, the MAX5115/MAX5116 (slave) issues an acknowledge by pulling SDA low for one clock cycle. SCL SDA STOP high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time. START LEGAL STOP CONDITION SCL SDA START ILLEGAL STOP ILLEGAL EARLY STOP CONDITION Figure 6. Early STOP Conditions S NOT ACKNOWLEDGE SDA ACKNOWLEDGE 1 SCL 8 9 A1 A0 Figure 7. Acknowledge and Not-Acknowledge Bits S 0 SDA 1 0 A3 A2 R/W ACK ACKNOWLEDGE 1 SCL 2 3 4 5 6 7 8 9 Figure 8. Slave Address Byte ______________________________________________________________________________________ 13 MAX5115/MAX5116 Acknowledge Bit (ACK) and NotAcknowledge Bit (NACK) MAX5115/MAX5116 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface MSB S LSB 0 A3 0 1 A2 A1 R/W =0 A0 ACK MSB C7 C6 C5 C4 C3 C2 C1 LSB C0 1 0 NV V R3 R2 R1 R0 ACK ADDRESS AND COMMAND BYTES GENERATED BY MASTER DEVICE MSB LSB 0 R/W =1 Sr A3 0 1 A2 A1 A0 MSB LSB D7 ACK D6 D5 D4 D3 D2 D1 D0 NACK P NACK GENERATED BY MASTER DEVICE DATA BYTE GENERATED BY MAX5115/MAX5116 Figure 9. Example Read Word Data Sequence Write Cycle The write command requires 27 clock cycles. In write mode (R/W = 0), the command byte that follows the address byte controls the MAX5115/MAX5116 (Table 1). For a write function, set bits C7 and C6 to zero. Set bits C5 and C4 to select the volatile or nonvolatile register (Table 2). Set bits C3–C0 to select the respective DAC register (Table 3). The registers update on the rising edge of the 26th SCL pulse. Prematurely aborting the write cycle does not update the DAC. See Table 4 for a summary of the write commands. Read Cycle A read command requires 36 clock cycles. In read mode, the MAX5115/MAX5116 send the contents of the volatile and nonvolatile registers to the bus. Reading a register requires a REPEATED START (Sr) condition. To read a register first, write a read command (R/W = 0, Figure 9). Set the most significant 2 bits of the command byte to 10 (C7 = 1 and C6 = 0). Set bits C5 and C4 to read from either the volatile or nonvolatile register (Table 5). Set bits C3–C0 to select the desired DAC register (Table 6). After the command byte, send a (Sr) condition followed by the address of the device (R/W = 1). The MAX5115/MAX5116 then acknowledge and send the data on the bus. Mute/Power-Down Mode The MAX5115/MAX5116 feature software-controlled mute and power-down modes for each DAC. The power-down mode places the DAC output in a highimpedance state and reduces quiescent-current consumption (25µA (max) with all DACs powered-down). START Table 1. Write Operation Master S SDA Slave SDA 14 ADDRESS BYTE COMMAND BYTE DATA BYTE STOP 0 1 0 A 3 A 2 A 1 A 0 R/W C 7 C 6 C 5 C 4 C C C 3 2 1 C 0 0 C 7 C 6 N V V R R R 3 2 1 R 0 A C K D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D7–D0 A C K ______________________________________________________________________________________ P A C K Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface 0 0 Table 3. DAC Write Selection R3 R2 R1 R0 FUNCTION 0 0 0 0 DAC0 0 0 0 1 DAC1 Transfer data from NVREG_ to VREG_ 0 0 1 0 DAC2 0 0 1 1 DAC3 1 1 1 1 All DACs* NONVOLATILE VOLATILE (NV) (V) FUNCTION 0 1 Write to VREG_ 1 0 Write to NVREG_ 1 1 Write to NVREG and VREG_ MAX5115/MAX5116 Table 2. Volatile and Nonvolatile Write Selection *This option is only valid for a write to all volatile registers. Table 4. Write-Command Summary COMMAND S T A R T ADDRESS BYTE DATA BYTE COMMAND BYTE A C K A C K R/W C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 MSB D 7 LSB D 6 D 5 D 4 D 3 D 2 D 1 A C K STOP D 0 Write VREG_ S 0 0 0 0 1 R 3 R 2 R 1 R 0 D7–D0 P Write All VREG_* S 0 0 0 0 1 1 1 1 1 D7–D0 P Write NVREG_ S 0 0 0 1 0 R 3 R 2 R 1 R 0 D7–D0 P Write VREG_ and NVREG_ S 0 0 0 1 1 R 3 R 2 R 1 R 0 D7–D0 P Transfer NVREG_ to VREG_ S 0 0 0 0 0 R 3 R 2 R 1 R 0 — P *This option is only valid for a write to all volatile registers. Mute drives the selected DAC output to the corresponding REFL_ voltage. The volatile DAC registers retain data and the output returns to its previous state when mute is disabled. The MAX5116 also features an asynchronous MUTE input that mutes all DACs simultaneously. The volatile and nonvolatile registers remain active while the MAX5115/MAX5116 are in mute and powerdown modes. Writing to or reading from the volatile or nonvolatile registers does not remove the MAX5115/ MAX5116 from mute or power-down mode. Writing or transferring data to the volatile registers while the device is muted or powered down updates the DAC outputs to the new state upon exiting mute or powerdown mode. Mute/Power-Down Register and Operation Separate nonvolatile and volatile control registers store and update the state of the mute/power-down mode for each DAC. Tables 7 and 8 show how to access and control each register. Register access is gained by setting control bits C3–C0 to 0100. Bits C5 and C4 indicate whether the nonvolatile or volatile control register is accessed. The volatile register maintains data while ______________________________________________________________________________________ 15 MAX5115/MAX5116 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface Table 5. Volatile and Nonvolatile Read Selection NONVOLATILE (NV) VOLATILE (V) 0 1 Read from VREG_ 1 0 Read from NVREG_ Table 6. DAC Read Selection FUNCTION R3 R2 R1 R0 FUNCTION 0 0 0 0 DAC0 0 0 0 1 DAC1 0 0 1 0 DAC2 0 0 1 1 DAC3 Table 7. Mute/Power-Down Operation COMMAND S T A R T DATA BYTE ADDRESS BYTE A C K COMMAND BYTE R/ W A A LSB C C MSB K K C C C C C C C C D D D D D D D D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 STOP Write VCTL S 0 0 0 0 1 0 1 0 0 Control register* P Write NVCTL S 0 0 0 1 0 0 1 0 0 Control register* P Write VCTL and NVCTL S 0 0 0 1 1 0 1 0 0 Control register* P Transfer NVCTL to VCTL S 0 0 0 0 0 0 1 0 0 Control register* P *See Mute/Power-Down Control Register (Table 8). Table 8. Mute/Power-Down Control Register BIT IN REGISTER CONTROLLING FUNCTION D7 (MSB) D6 D5 D4 Mute DAC3 Mute DAC2 Mute DAC1 Mute DAC0 the device remains powered. The nonvolatile register maintains data even after power is removed. The MAX5115/MAX5116 start up (power first applied) by transferring the mute/power-down from the nonvolatile to the volatile control register. The nonvolatile control register is set to 00 hex at the factory. Power-On Reset Power-on reset (POR) circuitry controls the initialization of the MAX5115/MAX5116. A power-on reset loads the volatile registers with the data stored in the nonvolatile registers. 16 D3 D2 D1 D0 (LSB) Power-down Power-down Power-down Power-down DAC3 DAC2 DAC1 DAC0 This initialization period takes 500µs (typ). During this time, the DAC outputs are held in mute mode. At the completion of the initialization period, the DAC outputs update in accordance with the configuration register. DAC Data The 8-bit DAC data is decoded as offset binary, MSB first, with 1 LSB = (VREFH_- VREFL_) / 256, and converted into the corresponding analog voltage as shown in Table 9. ______________________________________________________________________________________ Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface DAC Linearity and Offset Voltage The output buffer can have a negative input offset voltage that would normally drive the output negative, but with no negative supply, the output remains at GND (Figure 10). Determine linearity using the end-point method, measuring between code 10 (0A hex) and code 240 (F0 hex) after calibrating the offset and gain error (Figure 10). Table 9. Unipolar Code Output Voltage DAC CODE 1111 1111 OUTPUT VOLTAGE (V) 255 × (VREFH _ − VREFL _ ) 256 1000 0000 External Voltage Reference The MAX5115 features two reference inputs for each DAC (REFH_ and REFL_). The MAX5116 uses a single reference for all four DACs (REFH and REFL). REFH_ sets the full-scale voltage, while REFL_ sets the zero code output. The MAX5115 has a 460kΩ typical input impedance that is independent of the code. The MAX5116 has a 115kΩ typical input impedance that is independent of the code. MAX5115/MAX5116 Applications Information 0000 0001 0000 0000 + VREFL _ 128 × (VREFH _ − VREFL _ + VREFL _ 256 (VREFH _ − VREFL _ ) + VREFL _ 256 VREFL_ Power Sequencing The voltage applied to REFH_ and REFL_ should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REFH_, REFL_, and VDD to ensure compliance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered. Power-Supply Bypassing and Ground Management Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD with a 0.1µF capacitor, located as close to the device as possible. Bypass REFH_ and REFL_ to GND with 0.1µF capacitors. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs. OUTPUT VOLTAGE O NEGATIVE OFFSET DAC CODE Figure 10. Effect of Negative Offset (Single Supply) ______________________________________________________________________________________ 17 Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface MAX5115/MAX5116 Typical Operating Circuit Pin Configurations VDD µC SDA TOP VIEW VDD SCL RP RP RS* VDD SCL A2 1 20 A3 A1 2 19 SDA A0 3 18 VDD REFH1 4 17 SCL RS* SDA REFL1 5 MAX5115 REFH0 OUT0 REFH1 OUT1 REFH2 OUT2 REFH3 REFL0 REFL1 REFL2 REFL3 A1 A0 MAX5115 16 REFH0 OUT1 6 15 REFL0 REFH2 7 14 OUT0 OUT3 REFL2 8 13 REFH3 A3 A2 OUT2 9 12 REFL3 GND 10 11 OUT3 QSOP ADDRESS 0101 110 RS* VDD SCL RS* SDA *OPTIONAL REFH REFL MAX5115 REFH0 OUT0 REFH1 OUT1 REFH2 OUT2 REFH3 OUT3 REFL0 REFL1 A3 A2 REFL2 REFL3 A1 A0 ADDRESS 0101 111 A3 1 16 SDA A2 2 15 VDD 14 SCL A1 3 A0 4 MAX5116 13 REFH N.C. 5 12 REFL OUT1 6 11 OUT0 OUT2 7 10 OUT3 9 GND 8 MUTE QSOP Chip Information TRANSISTOR COUNT: 40,209 PROCESS: BiCMOS 18 ______________________________________________________________________________________ Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface QSOP.EPS PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH 21-0055 E 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX5115/MAX5116 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)