SHARP LH1595

LH1594/LH1595
80-Segment and 17-Common Outputs
LCD Driver IC with A Built-in CGROM
LH1594/LH1595
• Abundant command functions
– Display of 2 lines by 16 characters
– Display ON/OFF
– Normal/reverse display control
– Busy flag readout
– Cursor display
– Blinking : per character
– Display double fonts lengthwise
– Power saving mode
• LCD drive power circuit
– Built-in booster circuit : Two or three times
voltage boost is possible
– Built-in voltage converter : Generates LCD
drive voltages (V0, V1, V2, V3 and V4) based
on the boosted voltage
– Built-in power bias ratio :
1/4 or 1/5 bias (selectable by command)
– Built-in electronic volume : Controllable in 16
steps
– Supply voltages
Logic system : +2.2 to +5.5 V
LCD drive system : +4.0 to +11.0 V
• Operating temperature : –30 to +85 ˚C
• Package : 151-pin TCP (Tape Carrier Package)
DESCRIPTION
The LH1594/LH1595 are LCD drivers with a built-in
character ROM suitable for driving small scale dotmatrix LCD panels, and which are capable of being
directly connected to the bus line of a
microcomputer. The 8-bit parallel or serial data
transferred from a microcomputer is used to
generate LCD drive signals for displaying characters.
Incorporating a character ROM which has font
characters configured in the format of 5 x 8 dots and
a character RAM which allows the user to define
characters, the LH1594/LH1595 provide a higher
freedom of display. Since the LH1594/LH1595 have
80 output pins for a segment drive circuit and 17
output pins for a common drive circuit in a single
chip, a display system for 16 characters x 2 lines
can be implemented easily. The LH1594/LH1595
enable an LCD system for battery-operated, handcarrying information equipment by securing lower
power consumption and wider operating voltage
range.
FEATURES
• Built-in CGROM : 240 characters
(5 x 8 x 240 = 9 600 bits)
• Built-in CGRAM : 8 characters
(5 x 8 x 8 = 320 bits)
• Built-in SEGRAM : 80 segments
(16 x 7 = 112 bits)
• Built-in display data RAM : 32 characters
(32 x 8 = 256 bits)
• Format of font character : 5 x 8 dots including 1
dot which also serves to display a cursor
• General 8-bit MPU interface : Possible to directly
connect 80-family or 68-family MPU to bus line
• Possible to make serial interface
(I2C BUS* format is for LH1594)
• Ratio of display duty cycle :
1/8, 1/9, 1/16 or 1/17 (selectable by command)
* Purchase of I2C components of Sharp Corporation, or one
of its sublicensed Associated Companies conveys a
license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system
conforms to the I2C Standard Specification as defined by
Philips.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LH1594/LH1595
PIN CONNECTIONS
TOP VIEW
151-PIN TCP
COM7 1
COM6
COM5
CHIP SURFACE
COM2
COM1
COM0
COMI
COMS
SEGS4
SEGS3
SEGS2
SEGS1
SEGS0
SEG0
SEG1
SEG2
SEG77
SEG78
SEG79
SEGS5
SEGS6
SEGS7
SEGS8
SEGS9
COMS
COM8
COM9
COM10
COM13
COM14
COM15
COMI 110
NOTE :
Doesn't prescribe TCP outline.
2
151 VR2
VR1
VOUT
CAP2+
CAP2–
CAP1+
CAP1–
VEE
VDD
D7/SDA
D6/SCL
D5/SA0
D4/ISEL
D3
D2
D1
D0
M
FLM
LP
OSCO
OSCI
CKS
CK
PMODE
RDB
WRB
P/S
M86
RS
CSB
RESB
TEST
SHL1
SHL0
VSS
V4
V3
V2
V1
111 V0
LH1594/LH1595
RESB 120
COM0
COM7
95
8
1
ANNUNCIATOR
DRIVE CIRCUIT
CSB 121
102 109
COMI
SEG79
16
COMI
SEG0
96 100 10 101
COM15
COMS
11
COM8
SEGS5
15
COMS
SEGS4
SEGS9
SEGS0
BLOCK DIAGRAM
9
110
LCD DRIVE CIRCUIT
RS 122
ADDRESS
COUNTER
WRB 125
P/S 124
D0 135
D1 136
D2 137
MPU INTERFACE
M86 123
113 V2
CURSOR BLINKING
CONTROL CIRCUIT
SEGRAM
BUSY
D7/SDA 142
CGROM
TEST 119
114 V3
115 V4
146 CAP1+
145 CAP1–
148 CAP2+
147 CAP2–
149 VOUT
150 VR1
151 VR2
OSCI 130
144 VEE
TIMING CONTROL
CIRCUIT
VDD
3
VSS
143 116
M
132 133 134
FLM
OSC
127 PMODE
LP
CKS 129
118 SHL1
112 V1
DATA HOLDER
D6/SCL 141
CK 128
117 SHL0
111 V0
P/S CONVERSION
CIRCUIT
CGRAM
D5/SA0 140
OSCO 131
SHIFT
REGISTER
INSTRUCTION
DECODER
D3 138
D4/ISEL 139
LATCHING
CIRCUIT
DDRAM
LCD POWER SUPPLY CIRCUIT
RDB 126
LH1594/LH1595
1. PIN DESCRIPTION
1.1. Power Supply Pins
SYMBOL
VDD
VSS
I/O
DESCRIPTION
Power supply Power supply pin for logic, connected to +2.2 to +5.5 V.
Power supply Ground pin, connected to 0 V.
Bias power supply pins for LCD drive voltage.
• When using an external power supply, convert impedance by using resistancedivision of LCD drive power supply or operational amplifier before adding voltage to
the pins.
V0
V1
V2
V3
V4
• When using the external power supply, maintain the following power supply
conditions.
Power supply
VSS < V4 < V3 < V2 < V1 < V0
• When the power supply circuit is ON, LCD drive voltage of V 0 to V4 are generated
by the internal booster circuit and voltage converter.
• When using the internal power supply, be sure to connect each capacitor between
V0 to V4 and VSS.
1.2. LCD Power Supply Circuit Pins
SYMBOL
I/O
CAP1+
O
CAP1–
O
CAP2+
O
CAP2–
O
VEE
Power Supply
VOUT
Power Supply/ Output pin of boosted voltage in the internal booster circuit.
O
The capacitor must be connected between VSS and VOUT.
VR1
VR2
I
DESCRIPTION
Connecting pin for the internal booster's capacitor + side.
The capacitor is connected between CAP1– and CAP1+.
Connecting pin for the internal booster's capacitor – side.
The capacitor is connected between CAP1+ and CAP1–.
Connecting pin for the internal booster's capacitor + side.
The capacitor is connected between CAP2– and CAP2+.
Connecting pin for the internal booster's capacitor – side.
The capacitor is connected between CAP2+ and CAP2–.
Voltage supply pin for generating boosted voltage in the internal booster circuit.
Usually the same voltage level as VDD.
Used as input pins for voltage converter.
Voltage must be input between the VEE and VOUT pins by voltage divided by resistors.
Pin for controlling LCD power supply.
PMODE
I
A combination of PMODE pin and ON/OFF command of power supply (PON)
enables selection of a specific drive operation.
4
LH1594/LH1595
1.3. System Bus Pins
SYMBOL
I/O
DESCRIPTION
• When set to parallel interface mode (P/S = "H").
Used as an 8-bit bi-directional data bus (D7 to D0), which is connected to 8-bit MPU
data bus.
• When set to serial interface mode (P/S="L").
Used as serial interface signals (SDA, SCL, SA0, ISEL).
[SDA]
LH1594 : I/O pin for the I2C BUS data line when serial interface is selected.
D0
Must be connected to a positive power supply via pull-up resistor.
D1
LH1595 : Serial-data input pin at time of serial interface selection.
[SCL]
D2
D3
D4/ISEL
D5/SA0
I/O
LH1594 : Input pin for the I2C BUS clock signal when serial interface is selected.
Must be connected to a positive power supply via pull-up resistor.
LH1595 : Serial clock pin at time of serial interface selection.
D6/SCL
[SA0]
LH1594 : Used for LSB bit of slave address for I2C BUS (7 bits width).
D7/SDA
Must be fixed to "H" or "L".
LH1595 : Must be set to "L". If set to "H", LH1595 operation is not warranty.
[ISEL]
LH1594 : Used to identify I2C BUS. When using I2C BUS, fix to "H".
If ISEL is set to "L", LH1594 operation is not warranty.
CSB
I
LH1595 : Must be set to "L". If set to "H", LH1595 operation is not warranty.
Chip selection input pin that decoded address bus signal is input.
Distinguishes display RAM data/commands of D7 to D0 data transferred from MPU.
RS
I
RESB
I
1 : The data of D7 to D0 show the display RAM data.
0 : The data of D7 to D0 show the command data.
Initialized by setting to "L". The reset signals of the system are normally input. Reset
operation is performed in accordance with RESB signal level.
• In connecting to 80-family MPU :
This RDB is a pin for connecting the RDB signal of 80-family MPU. When the
RDB
(E)
signal enters in the "L" state, the data bus of this IC turns to the "output" state.
I
• In connecting to 68-family MPU :
This RDB becomes a pin for connecting the enable clock signal of 68-family MPU.
When the signal enters in the "H" state, the data bus of this IC turns to the "active"
state.
5
LH1594/LH1595
SYMBOL
I/O
DESCRIPTION
• In connecting to 80-family MPU :
This WRB is a pin for connecting the WRB signal of 80-family MPU, and when
WRB
(R/W)
WRB signal is "L", this pin is "active".
The data bus signal is input at the rising edge of WRB signal.
I
• In connecting to 68-family MPU :
This WRB becomes a pin for connecting the R/W signal of controlling read/write of
68-family MPU.
R/W = "H" : Read
R/W = "L" : Write
M86
I
MPU interface-type shift pin.
M86 = "H" : 68-family interface
M86 = "L" : 80-family interface
Fixed to either "H" or "L".
Used to shift between parallel interface and serial interface.
P/S
I
TEST
I
P/S = "H" for parallel interface. Fix SDA and SCL pins to either "H" or "L".
P/S = "L" for serial interface. Fix D3 to D0 pins to High-Z, RDB and WRB pins to
either "H" or "L".
For testing. Fix to "L".
1.4. LCD Drive Circuit Signals
SYMBOL
I/O
LP
O
DESCRIPTION
The latching signal of display data to count up the display line counter at the rising,
and to output the LCD drive signals at the falling.
Output pin for LCD display synchronous signals (first line marker).
FLM
O
M
O
When FLM pin is set to "H", the display starting line address is preset in the display
line counter.
Output pin for alternating signals of LCD drive output.
Segment output pins for LCD drive.
According to the data of the display data,
non-lighted at "0", lighted at "1" (Normal mode)
non-lighted at "1", lighted at "0" (Reverse mode)
and, by a combination of M signal and display data, one signal level among V0, V2,
V3, and VSS is selected.
SEG0-SEG79
O
M Signal
Display Data
Normal Mode
Reverse Mode
V2
V0
6
V0 V2
V3
VSS
VSS
V3
LH1594/LH1595
SYMBOL
I/O
DESCRIPTION
Common output pins for LCD drive.
By a combination of the scanning data and M signal, one signal level among V0, V1,
COM0-COM15
O
V4 and VSS is selected.
Output level
M
Data
VSS
H
H
L
H
V1
H
L
L
V0
V4
L
Common output pin for marker display.
When executing duty + 1 (PLUS) command, it functions as a common output pin.
Having two output pins for COMI, they output same level. It is able to select output
COMI
COMS
O
O
pin for COMI when wiring pattern.
Duty + 1 ON
Duty + 1 OFF
COM16 (when displaying 2 lines),
COMI state
V0 or V4
COM8 (when displaying 1 line)
Common drive output pin for static LCD drive (for annunciator display).
Having two output pins for COMS, they output same level. It is able to select output
pin for COMS when wiring pattern.
When DA = "0", outputs VSS level.
Segment drive output pin for static LCD drive (for annunciator display).
SEGS0-SEGS9
O
One level is selected from VDD and VSS levels depending on the combination of
COMS signal and display data.
When DA = "0", outputs VSS level.
Input pin to control the transfer direction of the segment and common signal output
data.
SHL0
SHL1
I
SHL0 = "0" : Segment data display direction is SEG0 to SEG79.
SHL0 = "1" : Segment data display direction is SEG79 to SEG0.
SHL1 = "0" : Common data display direction is COM0 to COM15.
SHL1 = "1" : Common data display direction is COM15 to COM0.
1.5. Pins for Oscillation Circuit
SYMBOL
OSCI
OSCO
I/O
I
O
DESCRIPTION
Feedback-resistance connecting pin for the internal oscillation circuit.
Input pin of display master clock.
CK
I
When using CK pin as an input of the master clock, fix OSCI pin to VSS.
When using the internal oscillation circuit as the display master clock, fix CK pin to
VSS.
Selection input pin of display master clock.
CKS
I
CKS = "H" : Input the external clock to CK pin.
CKS = "L" : The internal oscillation circuit by using OSCI and OSCO pins is used.
* Master clock : Clock for oscillation circuit or external clock.
7
LH1594/LH1595
1.6. Input/Output Circuits
VDD
I
To Internal Circuit
VSS (0 V)
¿Applicable pins¡
M86, P/S, SHL0, SHL1,
OSCI, CK, CKS,
PMODE, RESB, TEST
Fig. 1 Input Circuit (1)
VDD
To Internal Circuit
I
VSS (0 V)
VSS (0 V)
¿Applicable pins¡
CSB, RS, WRB,
RDB
Input Control Signal
Fig. 2 Input Circuit (2)
VDD
I
To Internal Circuit
O
VSS (0 V)
VDD
Output Control Signal
Output Signal
VSS (0 V)
Fig. 3 Input/Output Circuit (1)
8
¿Applicable pin¡
OSCO
LH1594/LH1595
VDD
I
To Internal Circuit
O
VSS (0 V)
VSS (0 V)
Input Control Signal
VDD
Output Control Signal
Output Signal
VSS (0 V)
¿Applicable pins¡
D7-D0
Fig. 4 Input/Output Circuit (2)
VDD
VDD
O
Output Signal
VSS (0 V)
¿Applicable pins¡
LP, FLM, M,
SEGS0-SEGS9,
COMS
VSS (0 V)
Fig. 5 Output Circuit
V0
V1/V2
V0
Output
Control Signal 1
Output
Control Signal 2
Output
Control Signal 3
Output
SEG0-SEG79,
Control Signal 4
O
¿Applicable pins¡
VSS (0 V)
V3/V4
VSS (0 V)
VSS (0 V)
Fig. 6 LCD Drive Output Circuit
9
COM0-COM15,
COMI
LH1594/LH1595
2. FUNCTIONAL DESCRIPTION
2.1. MPU Interface
2.1.1. INTERFACE TYPE SELECTION
The LH1594/LH1595 transfer data through 8-bit
parallel I/O (D7 to D0) or serial data input (SDA,
SCL).
P/S
H
I/F TYPE
Parallel
L
Serial
CSB
RS
CSB
RS
– (LH1594) – (LH1594)
CSB (LH1595) RS (LH1595)
The selection between parallel interface and serial
interface is made by setting the state of P/S pin to
"H" or "L".
RDB
RDB
WRB
WRB
M86
M86
SDA
–
SCL
–
DATA BUS
D7 to D0
–
–
–
SDA
SCL
–
2.1.2. PARALLEL INPUT
The LH1594/LH1595 can transfer data in parallel
by directly connecting 8-bit MPU to the data bus
when parallel interface is selected with P/S pin.
As an 8-bit MPU, either 80-family MPU interface or
68-family MPU interface is selected with M86 pin.
M86
H
MPU TYPE
68-family MPU
CSB
CSB
RS
RS
RDB
E
WRB
R/W
DATA
D7 to D0
L
80-family MPU
CSB
RS
RDB
WRB
D7 to D0
2.1.3. DATA IDENTIFICATION
The LH1594/LH1595 can identify the data of 8-bit data
bus by combinations of RS, RDB and WRB signals.
RS
68-FAMILY
80-FAMILY
RDB
WRB
0
1
FUNCTION
0
R/W
1
0
0
1
0
Writes to commands
1
1
1
0
0
1
1
0
Reads from data RAM
Writes to data RAM
Reads out busy flags
10
LH1594/LH1595
2.1.4. SERIAL INTERFACE
[FOR LH1594]
The serial interface for the LH1594 is I2C BUS
format. I2C BUS is for bi-directional two-line
communication between different ICs or other
modules.
LH1594 always operates as a slave device, so
sending data of start and stop is controlled by
start/stop bits which are sent by master device.
The identification whether the serial data inputs
(SDA) are display data or commands is judged by
input to RS pin.
RS = "H" : Display data
RS = "L" : Commands
After completing 8-bit data transferring, or when
making no access, be sure to set serial clock input
(SCL) to "L".
Protection of SDA and SCL signals against external
noise should be taken in actual wiring. To prevent
the successive recognition errors of transferring
data from external noise, release the chip selection
state (CSB = "H") at every completion of 8-bit data
transferring.
[FOR LH1595]
The serial interface of LH1595 can accept inputs of
SDA and SCL in the chip selection state (CSB =
"L"). When not in the chip selection state, the
internal shift register and counter are reset to their
initial condition.
Serial data SDA are input sequentially in order of
D7 to D0 at the rising edge of serial clock (SCL)
and are converted into 8-bit parallel data (by serial
to parallel conversion) at the rising edge of the 8th
serial clock, being processed in accordance with
the data.
CSB
Valid
RS
SDA
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
SCL
11
LH1594/LH1595
2.2. Busy Flag
2.7. Segment RAM (SEGRAM)
When the busy flag is "1", this indicates that the
LH1594/LH1595 are internally operating. In this
state, the LH1594/LH1595 do not accept the next
instruction. As shown in the command function
table, the busy flag is output to the data bus D7
when RS is "0" or R/W is "1" (for the 68-family
interface), and when RS is "0" or RDB is "0" (for
the 80-family interface). The busy flag is generated
only when the display clear command or the ACL
command is executed. It must be confirmed that
the busy flag is "0" before the next instruction can
be executed.
The SEGRAM allows user-written programs to
freely control icons and marks. When the COMI
outputs the selection signal, the data stored in the
SEGRAM is read out to display 80 segments.
2.8. Timing Generation Circuit
The timing generation circuit generates the timing
signals to operate the internal circuits, including the
DDRAM, CGROM, CGRAM, and SEGRAM, as
well as those for segment and common drive
outputs. Readout of the display data to the LCD
drive circuit is completely independent of MPU.
Therefore, a MPU that has no relationship the readout operation of the display data can access it.
2.3. Address Counter (AC)
The address counter (AC) is used to address the
DDRAM, CGRAM, or SEGRAM. When the
addressing instruction is written into the AC, the
address information is transferred to the AC.
Simultaneously, the instruction also determines
which RAM is to be selected among the DDRAM,
CGRAM, and SEGRAM. After data is written into
(read out from) the DDRAM, CGRAM, or
SEGRAM, the AC is automatically counted up or
down by one. As shown in the command function
table, the AC outputs data to the data buses D6 to
D0 when RS is "0" and R/W is "1" (for the 68-family
interface).
2.9. Cursor Blinking Control Circuit
This circuit generates the cursor, the blinking
cursor, or the reverse-display cursor. The cursor or
the blinking cursor appears in the digit that
corresponds to the address in the DDRAM which is
specified in the address counter.
2.4. Display Data RAM (DDRAM)
The DDRAM stores display data presented with 8bit character codes. Its capacity is 32 characters in
a format of 8 bits.
2.5. Character Generator ROM (CGROM)
The CGROM generates 240 different character
patterns in a format of 5 x 8 dots from 8-bit
character codes.
2.6. Character Generator RAM (CGRAM)
The CGRAM allows user-written programs to freely
overwrite characters. Eight different types of
characters can be written in a format of 5 x 8 dots.
12
LH1594/LH1595
2.10. Output Timing of LCD Driver
Display timing at normal mode, 1/16 duty
15
16
1
2
3
16
1
2
3
16
1
LP
FLM
M
V0
V1
COM0
V4
V4
VSS
VSS
V0
V1
COM1
V1
V1
V4
V4
V4
VSS
V0
V0
SEG0
V2
V3
V3
VSS
V0
V2
SEG1
V2
V2
V3
V3
V3
VSS
13
SEG2
COM1
SEG1
SEG0
COM0
LH1594/LH1595
the voltage converter which converts this high input
voltage into V0, V1, V2, V3 and V4 which are used
to drive the LCD.
This internal power supply should not be used to
drive a large LCD panel containing many pixels or
a large LCD panel that has large capacity
consisting of more than one chip. Otherwise,
display quality will degrade considerably. Instead,
use an external power supply.
This internal power supply is controlled by the
power supply circuit ON/OFF command (PON).
When the internal power supply is turned off, the
booster circuit and voltage converter are also
turned off.
When using the external power supply, turn off the
internal power supply, disconnect pins CAP1+,
CAP1–, CAP2+, CAP2–, VOUT, VEE, VR1 and VR2,
and keep PMODE pin at VSS. Then, feed external
LCD drive voltages to pins V0, V1, V2, V3 and V4.
This circuit can be changed by the state of PMODE
pin.
2.11. LCD Drive Circuit
This drive circuit generates 4 levels of LCD drive
voltage. The circuit has 80 segment outputs and 17
common outputs and outputs combined display
data and M signal. Character data is transferred by
80 bits from the CGROM or the CGRAM to the
segment drive circuit.
One of the common outputs, COMI is for marker
display only. A common drive circuit that has a shift
register sequentially outputs common scan signals.
2.12. Oscillation Circuit
The frequency of this CR oscillator is controlled by
the feedback resistor RF.
The output from this oscillator is used as the timing
signal source of the display and the boosting clock
to the booster circuit.
If external clock is used, maintain OSCI pin at VSS
and OSCO pin open (NC), and feed the clock to
CK pin.
The duty cycle of the external clock must be 50%.
The CKS pin is used to select either internal
oscillation circuit or external clock.
CKS OSCILLATION CIRCUIT
L
Enabled
H
PON PMODE
BOOSTER VOLTAGE
EXTERNAL
EXTERNAL CLOCK
Disabled
0
0
0
1
CIRCUIT CONVERTER VOLTAGE INPUT
Disabled Disabled V0, V1, V2, V3, V4
Disabled Disabled V0, V1, V2, V3, V4
Enabled
1
1
0
1
Enabled
Disabled
Disabled
Enabled
Enabled
NOTE
1
1
–
VOUT, VR1, VR2
2
NOTES :
2.13. Annunciator Circuit
1. Because the booster circuit and voltage converter are
not functioning, disconnect pins CAP1+, CAP1–, CAP2+,
CAP2–, VOUT, VEE, VR1, and VR2.
Apply external LCD drive voltages to corresponding pin.
2. Because the booster circuit is not functioning, disconnect
pins CAP1+, CAP1–, CAP2+, CAP2– and VEE.
Derive the voltage source to be supplied to the voltage
converter from VOUT pin and then output LCD drive
voltage to VR1, and VR2 pins. The voltage level at VR1
and VR2 pins must be VR2 ≤ VR1 ≤ VOUT.
This is the drive circuit which generates 2-value
levels for static LCD drive. This circuit provides
displaying annunciators for icons or marks. It
consists of common drivers (COMS x 2) and 10
segment drivers (SEGS0 to SEGS9). One level is
selected from VDD and VSS levels for static LCD
drive. When this circuit is not displaying
annunciator, it outputs VSS level.
2.14. Power Supply Circuit
This circuit supplies voltages necessary to drive an
LCD. The circuit consists of booster circuit and
voltage converter.
Boosted voltage from the booster circuit is fed to
14
LH1594/LH1595
2.15. Booster Circuit
from the internal oscillation circuit or external clock
as the boosting clock, the internal oscillation circuit
must be enabled, or if external clock is selected, it
must be fed to CK pin.
The output level at the VOUT pin does not exceed
the recommended maximum operating voltage
(11.0 V) when the voltage is boosted. If this value
is exceeded, the operation of the LH1594/LH1595
are not covered by warranty.
Placing capacitor C1 across CAP1+ and CAP1–
and across CAP2+ and CAP2– and across VOUT
and VSS boosts the voltage coming from VEE and
VSS three times and outputs the boosted voltage to
VOUT pin.
Placing C1 across CAP1+ and CAP1– and shorting
together pins CAP1+ and CAP2+ limits the output
on VOUT pin to two times the input voltage.
Since the booster circuit uses the clock derived
VOUT = 9 V
VOUT = 6 V
VEE = 3 V
VEE = 3 V
VSS = 0 V
VSS = 0 V
When Boosted Two Times
When Boosted Three Times
15
LH1594/LH1595
2.16. Voltage Control Circuit
2.17. Electronic Volume
The boosted voltage at the VOUT pin is connected
to the VR1 and VR2 pins and then the LCD drive
voltages (V0, V1, V2, V3, and V4) are generated via
the voltage converter circuit. The input level at the
VR1 and VR2 must meet the electric potential
condition of VR1 ≥ VR2. The internal electronic
volume divides the electric potential between the
VR1 and VR2 into 16 segments.
Since the VR1 and VR2 pins have high input
impedance, the input voltage levels at the VR1 and
VR2 are determined by the resistance ratio of R1,
R2, and R3. The current flowing between the VOUT
and VSS pins is determined by the combined
resistance of R1, R2, and R3.
Therefore, R1, R2, and R3 must be selected in
accordance with the above current as well as the
input voltage levels at the VR1 and VR2.
The boosted voltage at the VOUT pin originates
from the voltage supplied at the VEE pin.
Thus, the DC path current generated with R1, R2,
and R3 connected between the VOUT and VSS pins
is supplied as current at the VEE pin. The electric
current value, three times larger than the DC path
current generated between the VOUT and VSS pins
when the voltage is tripled, is added as supply
current at the VEE pin (two times larger current is
added for doubled voltage). Take sufficient care
that the input levels at the VR1 and VR2 pins do not
fluctuate with external noise (connect capacitor C3).
The voltage converter incorporates an electronic
volume, which allows the LCD drive voltage level
V0 to be controlled with a command and also
allows the tone of LCD to be controlled.
If 4-bit data is stored in the register of the electronic
volume, one level can be selected among 16
voltage values for the LCD drive voltage V0.
The voltage control range of the electronic volume
is determined by the input voltage levels at the VR1
and VR2. This means that the voltage range of (VR1
to VR2) is the controllable voltage range of the
electronic volume. The electric potential relation
between the VR1 and VR2 pins must be VR1 ≥ VR2.
The input voltage levels at the VR1 and VR2 pins
must be selected in accordance with the voltage
levels to be obtained with the electronic volume.
2.18. LCD Drive Voltage Generation
Circuit
The voltage converter contains the voltage
generation circuit. The LCD drive voltages other
than V0, that is, V1, V2, V3 and V4, are obtained by
dividing V0 through a resistor network. The LCD
drive voltages from LH1594/LH1595 are biased at
1/4 or 1/5.
When using the internal power supply, connect a
stabilizing capacitor C2 to each of pins V0 to V4.
The capacitance of C2 should be determined while
observing the LCD panel to be used. In this case,
connect a capacitor C3 to stabilize input voltage to
VR1 and VR2. A value of C3 can be defined
selectively.
VOUT
C1
R1
LH1594/LH1595
VR1
C3
R2
VR2
C3
R3
VSS
Example of Voltage Control Circuit
16
LH1594/LH1595
2.19. Example of Power Supply Circuit
VDD
VDD
VDD
VDD
VEE
VEE
CAP1+
CAP1+
C1
CAP1–
CAP1–
CAP2+
CAP2+
C1
CAP2–
CAP2–
VOUT
VR1
VR2
R1
C3
VSS
R2
C3
VSS
R3
VSS
V0
VOUT
C1
VSS
VR1
VR2
VSS
VSS
V0
V0
C2
V1
External
Power
Supply
V1
V1
C2
V2
V2
V2
C2
V3
V3
V3
C2
V4
V4
V4
C2
VSS
OSCI
RF
OSCO
OSCO
CKS
CKS
When Using The External Power Supply
Recommended values
C1
C2
OSCI
RF
1.0 to 5.0 µF (B)*
C3
RF
0.1 to 5.0 µF (B)*
0.01 to 0.1 µF
1.2 M$
R1 + R2 + R3
2.0 to 4.0 M$
* B characteristics must be used with C1 and C2.
17
When Using The Internal Power Supply
LH1594/LH1595
2.20. Initialization
3. PRECAUTIONS
The LH1594/LH1595 are initialized by setting RESB
pin to "L". Normally, RESB pin is initialized together
with MPU by connecting to the reset pin of MPU.
When power is ON, be sure to reset operation.
Precautions when connecting or disconnecting
the power supply
This IC may be permanently damaged by a high
current which may flow if voltage is supplied to the
LCD drive power supply while the logic system
power supply is floating. The details are as follows.
PARAMETER
Function
PIN DESCRIPTION
RE = 0 : Writes to expanded
register disabled.
q When using an external power supply
ø When connecting the power supply
After connecting the logic system power supply,
make reset operation and then apply external
LCD drive voltages to corresponding pins. (V0,
V1, V2, V3, V4 or VOUT, VR1 and VR2)
ø When disconnecting the power supply
After executing HALT command, disconnect
external LCD drive voltages and then disconnect
the logic system power supply.
BE = 0 : SEGRAM blink OFF
DUB = 0 : Normal display mode
(Displaying double
fonts lengthwise OFF)
BT = 0 : Blinking type is normal/
reverse display.
Entry mode
I/D = 1 : Increments by one.
S = 0 : No shift occurs.
Display mode
Display control (1)
NL = 0 : Displays 2 lines.
D = 0 : Display OFF
C = 0 : Cursor OFF
B = 0 : Blink OFF
Display control (2)
w When using the internal power supply
ø When connecting the power supply
After connecting the logic system power supply,
make reset operation and then execute PON
command.
ø When disconnecting the power supply
After executing HALT command, disconnect the
logic system power supply.
PLUS = 0 : 1/16 duty
REV = 0 : Normal display
ALON = 0 : Normal display
Power control
HALT = 0 : Power saving OFF
PON = 0 : Power supply circuit OFF
ACL = 0 : ACL operation OFF
BIAS : 1/5 bias
Register in electronic
volume
Annunciator control
It is advisable to connect the serial resistor (50 to
100 $) or fuse to the LCD drive power VOUT or V0
of the system as a current limiter. Set up a suitable
value of the resistor in consideration of the display
grade.
(1, 1, 1, 1)
DA = 0 : Annunciator display
OFF
I0 to I9 = (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
RAM data
DDRAM : Not determined.
CGRAM : Not determined.
SEGRAM : Not determined.
18
LH1594/LH1595
4. COMMAND FUNCTION
The busy state check is only necessary when the
display clear command or the ACL command is
executed.
Since the instructions for the LH1594/LH1595 are
executed within execution cycle time, the MPU can
be operated at a high speed without a waiting time.
4.1. Command Function Table
INSTRUCTION
RAM data write
RAM data read
0/1
1
Display clear set
0/1
0
0
0
0
0
0
0
0
1
Specifies address 0 from DDRAM
in AC after clearing all display.
Cursor home set
0/1
0
0
0
0
0
0
0
1
*
Allocates address 0 for DDRAM
in AC and resets shifted display.
0
0
0
0
0
0
1
I/D
S
*
NL
Sets display 2 lines or 1line (NL).
B
Turns ON/OFF all display (D). Turns
ON/OFF cursor (C). Specifies blinking
0
Display mode set
1
Display control (1) set
Display control (2) set
Cursor/display shift
set
Power control set
Function set
0
0
0
0
0
0
0
0
SEGRAM address set
DDRAM address set
1
Electronic volume set
1
Annunciator control
set
0
0
1
0/1
C
0
0
0
0
1
0
1
0
0
1
1
0
BF
*
1
R/L
*
*
BE DUB RE
BT
*
*
*
I5
DA
I4
*
without changing data in DDRAM.
ASEG
ADD
I2
I8
AC
* mark means "Don't care".
19
I1
I7
Specifies resetting (ACL).
Sets bias ratio (BIAS).
Enables writes to expanded register (RE).
Enables blinking for SEGRAM (BE).
Enables display double font lengthwise (DUB).
Sets DDRAM address.
Sets electronic volume.
DVOL
I3
I9
Turns ON power supply circuit (PON).
Sets blinking character type (BT).
Sets CGRAM address.
Sets SEGRAM address.
ACG
*
Turns ON all display (ALON).
Moves cursor and shifts display
Specifies HALT ON (HALT).
1
*
*
and whether or not to shift display.
Specifies duty + 1 (PLUS).
PLUS REV ALON Displays data in reverse display (REV).
BIAS HALT PON ACL
0
Specifies cursor moving direction
character indicated by cursor (B).
1
S/C
1
CGRAM address set
Busy flag/address
read
0
1
0/1
Writes to data RAM.
Reads from data RAM.
D
0
D0
READ DATA
0
0
D1
DESCRIPTION
RS
1
Entry mode set
D7
INSTRUCTION CODE
D6 D5 D4 D3 D2
WRITE DATA
RE
0/1
I0
I6
Sets data for annunciator (I0 to I9).
Enables display annunciator (DA).
Reads out busy flag and data
from AC.
LH1594/LH1595
4.2. Write Data to RAM
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
0/1
1
D
D
D
D
D
D
D
D
SEGRAM address setting. After writing, the address
automatically increments or decrements by 1, in
accordance with the entry mode.
Writes binary 8-bit data D7 to D0 to the CGRAM or
DDRAM or SEGRAM.
The RAM is to be written into is determined by the
previous specification of CGRAM or DDRAM or
4.3. Read Data to RAM
RE
0/1
RS
1
D7
D
D6
D
D5
D
D4
D
D3
D
D2
D
D1
D
D0
D
automatically increments or decrements by 1, in
accordance with the entry mode.
Reads binary 8-bit data D7 to D0 from the CGRAM
or DDRAM or SEGRAM.
The most recent set address command determines
the RAM is to be read. After writing, the address
4.4. Display Clear Register Set
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
0/1
0
0
0
0
0
0
0
0
1
When the clearing of the display starts, the busy
flag is generated. Therefore, to execute an
instruction after clearing the display, monitor the
busy flag and then execute the next instruction after
checking that the flag has been released; or allow a
waiting period of 34 times the master clock
frequency.
Space code "20H" (for 32 characters) is written to
all addresses in the DDRAM. The address counter
specifies DDRAM address 0.
If the display is shifted, it is reset in place. This
means that the display is cleared and the cursor or
blinking cursor, if displayed, returns to the left end
in the first line.
Set the I/D of the increment mode to "Increment".
"S" will not change.
4.5. Cursor Home Register Set
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
0/1
0
0
0
0
0
0
0
1
*
* mark means "Don't care".
the blinking cursor, if displayed, returns to the left
end in the first line.
Specify DDRAM address 0 in the address counter.
If the display is shifted, it is reset in place. The data
in the DDRAM remains unchanged. The cursor or
20
LH1594/LH1595
4.6. Entry Mode Register Set
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
I/D
S
shifted to the left; or if I/D = 0, the entire
display is shifted to the right. Therefore,
if I/D = 1, the cursor looks stationary with
only the display shifted. When any
character code is read out from the
DDRAM, the display is not shifted. If S =
0, the display remains unshifted. When
any data is written into or read out from
the CGRAM or SEGRAM, the display
also remains unshifted.
When duty + 1 command is ON (PLUS
= 1), if S = 1 and any code is written
into DDRAM, the line that COMI scans
is also shifted, so that this command is
allowed only when duty + 1 command is
OFF (PLUS = 0) state.
When the extended register enable bit (RE) is "0",
the following I/D, and S bits are accessed :
I/D
: When any character code is written into
or read out from the DDRAM, the
DDRAM address is shifted by +1 (I/D =
1) or –1 (I/D = 0). In case of +1, the
cursor or the blinking cursor moves to
the right. This is also applicable when
any data is written into or read out from
the CGRAM or SEGRAM.
S
: If S = 1, the entire display is shifted to
either the left or right when any
character code is written into the
DDRAM. If I/D = 1, the entire display is
4.7. Display Mode Register Set
RE
1
RS
0
D7
0
D6
0
D5
0
D4
0
D3
0
* mark means "Don't care".
When the extended register enable bit (RE) is "1",
the following NL bit is accessed :
NL
: This command selects the displaying
lines.
NL = "0" : Displays 2 lines. Display duty
ratio is 1/16.
NL = "1" : Displays 1 line. Display duty
ratio is 1/8.
21
D2
1
D1
*
D0
NL
LH1594/LH1595
4.8. Display Control (1) Register Set
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
D
C
B
unchanged when the display data is
written. The cursor is shown with 5 dots
in the 8th line.
When the extended register enable bit (RE) is "0",
the following D, C, and B bits are accessed :
D
C
: Turns ON the display if D = 1; or turns
OFF the display if D = 0. Since the data
in the DDRAM is retained, the display
can be resumed by specifying D = 1.
B
: Displays the cursor if C = 1; or hides the
cursor if C = 0. Even if the cursor is
hidden, I/D and other features remain
: Blinks the character in the cursor
position if B = 1. This blinking turns
ON/OFF all dots displayed in reverse.
The blinking frequency is 300 ms when
fOSC = 55 kHz and displays 2 lines. This
value varies in proportion to the inverse
number of fOSC.
4.9. Display Control (2) Register Set
RE
1
RS
0
D7
0
D6
0
D5
0
D4
0
D3
1
D2
PLUS
REV
When the extended register enable bit (RE) is "1",
the PLUS, REV, and ALON bits are accessed.
Once the specified values are stored in this
register, they are retained even if the RE bit is set
to "0".
D1
REV
D0
ALON
: Toggles between normal and reverse
videos for display.
REV = "0" : Normal video
REV = "1" : Reverse video
ALON : Toggles between normal and fully lit-up
displays regardless the data type in the
DDRAM. The setting of this bit takes
priority over that of REV.
ALON = "0" : Normal display
ALON = "1" : Fully lit-up display
PLUS : Specifies "duty + 1". Toggles the display
duty. The COMI pin functions as the
COM8 (when displaying 1 line) or
COM16 (when displaying 2 lines) for
marker. When the COMI is scanned, the
data in the SEGRAM is output as
display data from the segment driver.
PLUS = "0" : Sets the display duty to 1/8
(when displaying 1 line)
or 1/16 (when displaying
2 lines).
PLUS = "1" : Sets the display duty to 1/9
(when displaying 1 line)
or 1/17 (when displaying
2 lines).
22
LH1594/LH1595
4.10. Cursor/Display Shift Register Set
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
S/C
R/L
*
*
* mark means "Don't care".
line. Note that all the lines are shifted
simultaneously.
When duty + 1 command is ON (PLUS = 1), if S =
1 and any code is written into DDRAM, the line that
COMI scans is also shifted, so that this command
is allowed only when duty + 1 command is OFF
(PLUS = 0) state.
When the extended register enable bit (RE) is "0",
the following S/C and R/L bits may be set.
The cursor position or the display is shifted to the
left or right without writing the display data or
reading it out. This may be used to modify or
search the display. The cursor movement from the
1st to 2nd line occurs after the 16th digit in the 1st
S/C
0
0
R/L
0
1
1
1
0
1
ACTION
Shifts cursor to left (counts down the AC by one).
Shifts cursor to right (counts up the AC by one).
Shifts entire display to left. Cursor moves as display is shifted.
Shifts entire display to right. Cursor moves as display is shifted.
If only the display shift is made, the address
counter (AC) remains unchanged.
4.11. Power Control Register Set
RE
RS
D7
D6
D5
D4
1
0
0
0
0
1
D3
D2
BIAS HALT
D1
D0
PON
ACL
• The LCD drive is disabled. The output
from the segment and common drivers
are made at the VSS level.
• The clock input at the CK pin is
inhibited.
BIAS : This command selects the displaying
bias ratio.
BIAS = "0" : 1/5 bias
BIAS = "1" : 1/4 bias
HALT : Turns ON/OFF the power saving mode.
When the LH1594/LH1595 enter the
power saving mode, the supply current
can be reduced to nearly the standby
current value.
HALT = "0" : Normal mode
HALT = "1" : Power saving mode
The internal state in the power saving
mode is described below.
• The oscillation and power circuits are
stopped.
PON : Turns ON/OFF the internal power supply
circuit.
PON = "0" : Turns OFF the power supply
circuit.
PON = "1" : Turns ON the power supply
circuit.
The booster circuit and the voltage
converter become active when the power
supply circuit is turned on. The operating
section in the circuits varies depending
on the setting of the PMODE pin. See
Table in Section 2.14. for details.
23
LH1594/LH1595
ACL
operation, monitor the busy flag and
then execute the next instruction after
checking that the flag has been
released; or allow a waiting period of 2
times the master clock frequency.
: The internal circuit can be initialized.
ACL = "0" : Normal mode.
ACL = "1" : ACL operation is ON.
When the ACL command is turned on,
the busy flag is generated. Therefore, to
execute an instruction after ACL
4.12. Function Register Set
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
0/1
0
0
0
1
BE
DUB
RE
BT
*
* mark means "Don't care".
RE
BE
bits is used to allow for blinking the
display data from the SEGRAM.
: This bit is the enable bit for extended
register. If RE = "1", the extended
function setting can be accessed. When
setting instruction, it is necessary to
follow the state of RE bit. (refer to
"INSTRUCTION CODE" in section 4.1..)
RE bit consists of register, once the
specified value is stored in this register,
it is retained the value.
DUB
: This bit is toggled the display double
fonts lengthwise.
DUB = "0" : Displays normal mode.
DUB = "1" : Displays double fonts lengthwise.
NOTES :
• Double fonts lengthwise can display only first
line.
• Not using these setting, when displaying 1 line
mode. (NL = 1)
: When BE = "1", the information which is
stored in the SEGRAM using its upper 2
Example of Display (DUB = "1")
BT
BT = "1" : Displaying normal/black per
32 frames.
: This command selects the character
blinking type.
BT = "0" : Displaying normal/reverse per
32 frames.
Example of Display (BT = "0")
Example of Display (BT = "1")
24
LH1594/LH1595
4.13. CGRAM Address Register Set
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
A
A
A
A
A
A
number for "AAAAAA" is allocated in the address
counter. Subsequently data is written into or read
from the MPU in reference to the CGRAM.
If the extended register enable bit (RE) is "0",
CGRAM addresses may be specified.
In the above example, the address shown in binary
4.14. SEGRAM Address Register Set
RE
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
*
*
A
A
A
A
* mark means "Don't care".
"AAAA" is allocated in the address counter.
Subsequently data is written into or read from the
MPU in reference to the SEGRAM.
If the extended register enable bit (RE) is "1",
SEGRAM addresses may be specified.
The SEGRAM address shown in binary number for
4.15. DDRAM Address Register Set
RE
0
RS
0
D7
1
D6
0
D5
*
D4
A
D3
A
D2
A
D1
A
D0
A
* mark means "Don't care".
"AAAAA" is allocated in the address counter.
Subsequently data is written into or read from the
MPU in reference to the DDRAM.
If the extended register enable bit (RE) is "0",
DDRAM addresses may be specified.
The DDRAM address shown in binary number for
4.16. Electronic Volume Register Set
RE
1
RS
0
D7
1
D6
0
D5
*
D4
*
D3
MSB
D2
D1
πππππππ
D0
LSB
* mark means "Don't care".
The LCD drive voltage V0 output from the internal
power supply circuit can be controlled and the
display tone on the LCD can be also controlled.
The LCD drive voltage V0 takes one out of 16
voltage values by setting 4-bit data register.
If the electronic volume is not used, specify
(1, 1, 1, 1) in the 4-bit data register. After the
LH1594/LH1595 are reset, the 4-bit data register is
automatically set to (1, 1, 1, 1).
MSB
0
πππππππ
0
0
LSB
0
|
1
25
1
V0
Smaller
|
1
1
Larger
LH1594/LH1595
4.17. Annunciator Control Register Set
RE
0
1
RS
0
D6
D7
1
1
D5
D4
D3
D2
D1
I5
I4
I3
I2
I1
D0
I0
DA
*
I9
I8
I7
I6
* mark means "Don't care".
DA
I0 to I9 : These bits are setting data for
annunciator. Io to I9 correspond to
SEGS0 to SEGS9 for static LCD drive
outputs.
Display OFF ("DA" = "0")
: When DA = "1", output pin for static
LCD drive (for annunciator display). One
level is selected from VDD and VSS
levels depending on the combination of
COMS signal and display data (I0 to I9).
When DA = "0", outputs VSS level.
Display ON ("DA" = "1")
"VDD"
COMS
"VSS"
"VSS"
"VSS"
"VSS"
"VDD"
SEGS0
Not lighted
"VDD"
Lighted
"VSS"
"VSS"
SEGS1
1 Frame
1 Frame
Example of Outputs for Annunciator (DA = "1", I0 = "0", I1 = "1")
4.18. Busy Flag/Address Read
RE
0/1
RS
0
D7
BF
D6
*
D5
A
D4
A
D3
A
D2
A
D1
A
D0
A
* mark means "Don't care".
Simultaneously, the address counter value
presented in binary number for "AAAAAA" is read
out. The address counter is used by the DDRAM,
CGRAM, and SEGRAM. The data read out from
the RAMs is determined by specifying a command
before reading out.
"BF = 1" indicates that the LH1594/LH1595 are
internally operating and the next instruction is not
accepted until "BF = 0".
The busy flag is only generated when the display is
cleared or the ACL command is executed.
Therefore, any other instruction can be executed
without monitoring the busy flag.
26
LH1594/LH1595
4.19. Example of Instructions vs. Display
NO.
1
INSTRUCTION
2
Function set
0 0 0
1
*
*
0
0
*
3
Display clear
0 0 0 0
0
0
0
0
1
1
1
1
0
4
5
6
Display ON/OFF control
0 0 0 0
Entry mode set
0
0 0 0 0 0
DDRAM data write
1
0
1
0
1
7
:
:
8
DDRAM data write
1 0 1 0 1
9
10
0 1 0 * 1
DDRAM data write
1
0
1
0
0
:
ACTION
No display appears.
"0" is written to RE bit.
Display is cleared.
Turns ON display and cursor. If display is
_
cleared, display is filled with blank spaces.
Counts up address by one and moves
_
cursor to right when data is written to RAM.
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
L_
0
0
1
0
SHARP
LCDDRIVER_
Writes "R".
*
S
_ HARP
LCDDRIVER
Resets both display and cursor in place
(address 0).
DDRAM address set
11
S_
Writes "S".
SHARP_
Writes "P".
SHARP
Sets DDRAM address so that cursor is
_
SHARP
positioned at the top of 2nd line.
Writes "L".
:
12
DDRAM data write
1 0 1 0 1
13
:
:
14
DISPLAY
RS D7 D6 D5 D4 D3 D2 D1 D0
Power ON
Cursor home
0 0 0 0
0
0
0
1
* mark means "Don't care".
27
LH1594/LH1595
5. CONFIGURATION OF CGROM
Character codes vs. character patterns
Low order
High order
0000
XXXX0000
CG
RAM
(1)
XXXX0001
CG
RAM
(2)
XXXX0010
CG
RAM
(3)
XXXX0011
CG
RAM
(4)
XXXX0100
CG
RAM
(5)
XXXX0101
CG
RAM
(6)
XXXX0110
CG
RAM
(7)
XXXX0111
CG
RAM
(8)
XXXX1000
CG
RAM
(1)
XXXX1001
CG
RAM
(2)
XXXX1010
CG
RAM
(3)
XXXX1011
CG
RAM
(4)
XXXX1100
CG
RAM
(5)
XXXX1101
CG
RAM
(6)
XXXX1110
CG
RAM
(7)
XXXX1111
CG
RAM
(8)
0001
0010
0011
0100
0101
0110
28
0111
1000
1001
1010
1011
1100
1101
1110
1111
LH1594/LH1595
6. CONFIGURATION OF CGRAM
CGRAM addresses vs. character codes (DDRAM) and character patterns (CGRAM).
CHARACTER CODE
CGRAM ADDRESS
CGRAM DATA
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 * 0 0 0 0 0 0 0 0 0 * * * 1 0 0 0 1
1 0 0 0 1
0 0 1
1 0 0 0 1
0 1 0
0 1 0 1 0
0 1 1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
:
:
0
1
*
1
1
* mark means "Don't care".
1
1
1
(Y)
:
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
1
0
*
*
*
(H)
Upper section : Character pattern 1 (Y display)
Lower section : Character pattern 2 (H display)
NOTES:
1. Character code bits D2 to D0 correspond to CGRAM
addresses A5 to A3 (3 bits : 8 types).
2. CGRAM addresses A2 to A0 correspond to line positions
of the character pattern (3 bits : 8 lines).
3. The columns of the character pattern are laid out with bit
0 allocated to the right end. Therefore, the pattern of bits
4 to 0 is displayed.
4. If the upper 4 bits (D7 to D4) of the character code are
zeros, the CGRAM is selected. Since bit D3 is "Don't
care", "00H" and "08H" are the same CGRAM address.
5. If the CGRAM data is "1", data is displayed; if "0", data
isn't displayed.
29
LH1594/LH1595
7. CONFIGURATION OF SEGRAM
SEGRAM addresses vs. display patterns
SEGRAM ADDRESS
A2
A1
A0
A3
D7
D6
SEGRAM DATA
D5
D4
D3
D2
D1
D0
0
0
0
0
B1
B0
*
S0
S1
S2
S3
S4
0
0
0
1
B1
B0
*
S5
S6
S7
S8
S9
0
0
0
0
1
1
0
1
B1
B1
B0
B0
*
*
S10
S15
S11
S16
S12
S17
S13
S18
S14
S19
0
1
0
0
B1
B0
*
S20
S21
S22
S23
S24
0
0
1
1
0
1
1
0
B1
B1
B0
B0
*
*
S25
S30
S26
S31
S27
S32
S28
S33
S29
S34
0
1
1
0
1
0
1
0
B1
B1
B0
B0
*
*
S35
S40
S36
S41
S37
S42
S38
S43
S39
S44
1
0
0
1
B1
B0
*
S45
S46
S47
S48
S49
1
1
0
0
1
1
0
1
B1
B1
B0
B0
*
*
S50
S55
S51
S56
S52
S57
S53
S58
S54
S59
1
1
1
1
0
0
0
1
B1
B1
B0
B0
*
*
S60
S65
S61
S66
S62
S67
S63
S68
S64
S69
1
1
1
0
B1
B0
*
S70
S71
S72
S73
S74
1
1
1
1
B1
B0
*
S75
S76
S77
S78
S79
* mark means "Don't care".
D7 and D6 : Blink control
D4 to D0 : Pattern displayed
NOTES :
1. Data stored in the SEGRAM is output for one-line
display when COMI is selected.
2. Pins S0 to S79 are segment drive pins. Pin S0 is shown
at the left end on the screen.
3. After output at pin S79, output at pin S0 is repeated.
4. For SEGRAM data, the lower 5 bits are used for display
data.
5. If BE bit in the function set register is set to "1", the
upper 1 bit (D7) in SEGRAM is used to control the
blinking of the lower 5-bit pattern. When D7 is set to "1",
the lower 5-bit display blinks. If bit D6 is "1", only the
pattern of bit D4 can be blinked.
6. If SEGRAM data is "1", data is displayed; if "0", data isn't
displayed.
30
LH1594/LH1595
8. CONFIGURATION OF DDRAM
Display positions vs. display data RAM (DDRAM) addresses
DIGIT
COM0 to COM7
COM8 to COM15
1st
00
2nd
01
3rd
02
4th
03
5th
04
6th
05
7th
06
8th
07
9th 10th 11th 12th 13th 14th 15th 16th
08
09
0A 0B 0C 0D 0E 0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
If the display data is shifted, the DDRAM addresses
are changed as follows :
The above addressing is used because 16 digits
are displayed. The DDRAM stores data for 32
characters.
Shift to right
DIGIT
COM0 to COM7
COM8 to COM15
1st
1F
0F
2nd
00
10
3rd
01
11
4th
02
12
5th
03
13
6th
04
14
7th
05
15
8th
06
16
1st
01
11
2nd
02
12
3rd
03
13
4th
04
14
5th
05
15
6th
06
16
7th
07
17
8th
08
18
9th 10th 11th 12th 13th 14th 15th 16th
07
08
09
0A 0B 0C 0D 0E
17
18
19
1A 1B 1C 1D 1E
Shift to left
DIGIT
COM0 to COM7
COM8 to COM15
9th 10th 11th 12th 13th 14th 15th 16th
09
0A 0B 0C 0D 0E 0F
10
19
1A 1B 1C 1D 1E 1F
00
NOTE :
• The memory in the DDRAM is configured as follows :
Display area (16 characters x 2 lines)
As shown above, the 2nd data appears following
the end of the data in the 1st line. Notice that the
addresses are consecutive.
31
LH1594/LH1595
9.1.1. DATA TRANSFER
A change of SDA-state is allowed while SCL is low
level. If SDA changes while SCL is high, this action
is recognized as start bit or stop bit.
9. DESCRIPTION OF SERIAL INTERFACE
[FOR LH1594]
LH1594 is built in I2C BUS format interface.
The I2C BUS is for bi-directional two-line communication between different ICs or modules.
9.1.
I2C
9.1.2. START SIGNAL
When the bus is not busy, SDA transfers high to
low while SCL is high. This state is defined as the
start condition.
BUS Protocol
I2C BUS protocol consists of a data receiver and
data transmitter.
The device which controls protocol is the master,
the device which is controlled is the slave.
The master controls data transfer and provides
clock signal.
The LH1594 is used as a slave receiver or slave
transmitter.
9.1.3. STOP SIGNAL
When the bus is not busy, SDA transfers low to
high while SCL is high. This state is defined as the
stop condition.
SCL
SDA
Stop Signal
Start Signal
Start/Stop Timing
9.1.4. ACKNOWLEDGE
Acknowledge bit is used to confirm data transfer.
A transmitter (master or slave) releases the bus line
after receiving 8-bit data. During next clock (9th
SCL
SDA
clock) receive, put low level on the bus to indicate
data receive completely.
1
2
8
Data
Data
Data
9
Acknowledge
Acknowledge Timing
32
LH1594/LH1595
9.1.5. DEVICE ADDRESS CODE
After sending start bit, master device must transfer
8-bit device address code at first. Address code
consists of 7 bits slave address and 1 bit R/W.
During read operation, R/W bit is "1". During write
operation, R/W bit is "0".
Slave address (7 bits)
9.1.7. SECOND TRANSFERRED DATA
During slave receive mode, LH1594 is specified as
a control-byte waiting mode after receiving start
condition and first cycle of 1 byte. Control-byte
consists of 3 bits.
These bits are used to specify function mode for
operating instruction.
Co
: This bit defines transfer mode.
"0" : From next transfer byte, only data
byte can be transferred.
"1" : Next transfer byte is data byte and
after next transfer byte, control-byte
must be input again.
RS
: RS corresponds to "RS" signal in
command function table. This bit
identifies transfer data.
R/W
: This bit defines read/write mode.
"0" : Readable mode
"1" : Write enable mode.
R/W ACK
: Slave receiver
{ "0"
"1" : Slave transmitter
Send Data at First Cycle
9.1.6. DEVICE ADDRESSING
Bus master must generate start-condition to start
data transfer between 2 devices.
After generating start condition, master puts 8-bit
word on SDA bus line.
LH1594 is fixed higher order bits (corresponding to
DB7 to DB2). To identify device, it is fixed to
"011101".
Next 1 bit is used to select LCD driver among
some devices connecting to same bus.
LH1594 can connect to same bus, up to 2 chips.
SA0 is used for LSB bit for identifying device.
8th bit (R/W bit) defines operation mode.
R/W = "0" : Write operation
R/W = "1" : Read operation
0
1
1
1
0
C0 RS R/W *
*
*
*
*
* mark means "Don't care".
Transfer Data at Second Cycle
1 SA0 R/W
LH1594 Slave Address
33
LH1594/LH1595
9.2. Description of Pins Connected
with The I2C BUS
SCL
Serial clock input pin.
SCL is used for clock of all data I/O.
SDA
SDA is bi-directional pin, which is used
for data I/O.
SDA is open drain pin, connect to VDD
via pull-up resistor.
SA0
SA0 is used for LSB bit of slave address
(7 bits width). Must be fixed to "H" or "L"
externally.
ISEL
ISEL selects whether to use I2C BUS or
not.
When ISEL is "H", I2C BUS is enable.
If ISEL is low, I2C BUS operation of
LH1594 is not warrantied.
34
LH1594/LH1595
9.3. Example of I2C BUS Operation
STEP
I2C BUS TRANSFER BYTE
1
START I2C BUS
Send slave address
2
DISPLAY
During the acknowledge cycle SDA will be
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK
0
1
1
1
0
1
0
0
0
0
0
0
OPERATION
Initialized. Nothing display.
pulled down by LH1594.
1
Send control byte
3
C0 RS R/W
0
4
6
7
8
0
ACK
0
Control bits RS, C0 and R/W are specified.
1
Set function
D7 D6 D5 D4 D3 D2 D1 D0 ACK
0
5
0
0
1
0
0
0
0
0
Sets RE bit to "0".
1
Clear display
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Display clear.
0 0 0 0 0 0
Control display ON/OFF
Display and cursor are ON.
0
1
1
D7 D6 D5 D4 D3 D2 D1 D0 ACK _
All displays are cleared by operating
0 0 0 0
Set entry mode
display clear.
1
1
1
0
1
Entry mode set.
D7 D6 D5 D4 D3 D2 D1 D0 ACK _
0 0 0 0 0 1 1 0 1
When writing into RAM, address is increased
by 1 and cursor is shifted to right.
Set CGRAM address
D7 D6 D5 D4 D3 D2 D1 D0 ACK _
Sets address to write into CGRAM.
0
1
0
0
0
0
0
0
1
Start condition
9
Sets RS bit to "1" and generated start
_
condition again for writing.
Send slave address
10
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK _
0 1 1 1 0
Send control byte
11
C0 RS R/W
0 1 0 0
0
1
0
0
0
0
0
1
ACK _
1
Write CGRAM data
12
D7 D6 D5 D4 D3 D2 D1 D0 ACK _
0 0 0 CG4 CG3 CG2 CG1 CG0 1
Writes data into CGRAM.
:
:
13
:
Start condition
14
Generates start condition again for setting
_
RS "0".
35
LH1594/LH1595
STEP
15
I2C BUS TRANSFER BYTE
Send slave address
1
0
0
0
0
0
C0 RS R/W
0
17
OPERATION
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK _
0 1 1 1 0
Send control byte
16
DISPLAY
0
0
0
0
1
ACK _
1
Set DDRAM address
D7 D6 D5 D4 D3 D2 D1 D0 ACK _
1
0
0
0
0
0
0
0
Sets address for writing into DDRAM.
1
Start condition
18
Sets RS "1" and generates start condition
_
again for writing into DDRAM.
Send slave address
19
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK _
0 1 1 1 0
Send control byte
20
C0 RS R/W
0 1 0 0
0
1
0
0
0
0
0
1
ACK _
1
Write DDRAM data
21
D7 D6 D5 D4 D3 D2 D1 D0 ACK S_
0 1 0 1 0 0 1 1 1
Writes "S".
:
:
22
:
23
Write DDRAM data
D7 D6 D5 D4 D3 D2 D1 D0 ACK SHARP_
0 1 0 1
Start condition
0
0
0
0
Writes "P".
1
24
SHARP_
25
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK SHARP_
0 1 1 1 0 1 0 0 1
Generates start condition again for setting
RS "0".
Send slave address
26
Send control byte
C0 RS R/W
0
27
0
0
0
ACK SHARP_
0
0
0
0
1
Set DDRAM address
SHARP
D7 D6 D5 D4 D3 D2 D1 D0 ACK
_
1 0 0 1 0 0 0 0 1
36
Sets DDRAM address so that cursor is
positioned at the top of 2nd line.
LH1594/LH1595
STEP
I2C BUS TRANSFER BYTE
Start condition
DISPLAY
28
29
30
SHARP
Sets RS "1" and generates start condition
_
again for writing into DDRAM.
Send slave address
SHARP
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK
_
0 1 1 1 0 1 0 0 1
Send control byte
C0 RS R/W
0
31
OPERATION
1
0
0
ACK
0
0
0
0
1
SHARP
_
Write DDRAM data
SHARP
D7 D6 D5 D4 D3 D2 D1 D0 ACK
L_
0 1 0 0 1 1 0 0 1
:
32
Writes "L".
:
:
Write DDRAM data
33
34
35
36
SHARP
D7 D6 D5 D4 D3 D2 D1 D0 ACK
LCDDRIVER_
0 1 0 1 0 0 1 0 1
Start condition
SHARP
LCDDRIVER_
Send control byte
C0 RS R/W
ACK
0
0
0
1
SHARP
LCDDRIVER_
SHARP
D7 D6 D5 D4 D3 D2 D1 D0 ACK
LCDDRIVER_
1 0 0 0 0 0 0 0 1
Send control byte
38
Generates start condition again for setting
RS "0".
Send slave address
SHARP
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK
LCDDRIVER_
0 1 1 1 0 1 0 0 1
1 0 0 0 0
Set DDRAM address
37
Writes "R".
C0 RS R/W
0 1 1 0
Start condition
0
0
0
SHARP
ACK
LCDDRIVER_
0 1
39
SHARP
LCDDRIVER_
40
Send slave address
SHARP
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK
LCDDRIVER_
0 1 1 1 0 1 0 1 1
37
Sets control bit C0 "1".
Sets address for reading out DDRAM
data.
Sets control bit RS "1" and R/W "1".
Generates start condition again for
reading out DDRAM.
Sets R/W "1" for reading out DDRAM
data.
LH1594/LH1595
STEP
41
I2C BUS TRANSFER BYTE
Read out data
D7 D6 D5 D4 D3 D2 D1 D0 ACK
MSB π
π
π
42
43
DISPLAY
π
:
π
π LSB 0
SHARP
LCDDRIVER_
OPERATION
Reads out DDRAM data from MSB to
LSB.
Master outputs acknowledge.
:
:
Read out data
SHARP
D7 D6 D5 D4 D3 D2 D1 D0 ACK
LCDDRIVER_
MSB π π π π π π LSB 1
Stop condition
SHARP
44
LCDDRIVER_
As master does not output acknowledge,
data will not be output in the next cycle.
Generates stop condition and finishes.
10. ABSOLUTE MAXIMUM RATINGS
Supply
Supply
Supply
Supply
Supply
PARAMETER
voltage (1)
voltage (2)
voltage (3)
voltage (4)
voltage (5)
Supply voltage (6)
Input voltage
Storage temperature
SYMBOL
VDD
VEE
VOUT
VR1, VR2
V0
V1, V2,
V3, V4
VI
APPLICABLE PINS
VDD
VEE
VOUT
VR1, VR2
V0
RATING
–0.3 to +6.0
–0.3 to +6.0
–0.3 to +13.0
–0.3 to +13.0
–0.3 to +13.0
UNIT
V
V
V
V
V
V1, V2, V3, V4
–0.3 to V0 + 0.3
V
D7-D0, CSB, RS, M86, RDB,
WRB, CK, CKS, OSCI, P/S,
RESB, PMODE, SHL0, SHL1,
TEST
–0.3 to VDD + 0.3
V
–45 to +125
˚C
TSTG
NOTE
1, 2
NOTES :
1. TA = +25 ˚C
2. The maximum applicable voltage on any pin with respect to VSS (0 V).
11. RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply voltage
Operating voltage
Operating temperature
SYMBOL
VDD
VEE
V0
VOUT
VR1, VR2
TOPR
APPLICABLE PINS
VDD
VEE
V0
VOUT
VR1, VR2
MIN.
+2.2
+2.4
+4.0
+4.0
+4.0
–30
TYP.
MAX.
+5.5
+5.5
+11.0
+11.0
+11.0
+85
UNIT
V
V
V
V
V
˚C
NOTE
1
2
3
4
NOTES :
3. Ensure that voltages are set such that VSS < V4 < V3 <
V2 < V1 < V0.
4. The operating range is adjusted by the external circuit
constructed between VOUT and VR1, VR2. The electric
potential relation between the VR1, VR2 and VOUT pins
must be VR2 ≤ VR1 ≤ VOUT.
1. The applicable voltage on any pin with respect to VSS (0 V).
2. When using the booster circuit, power supply, VEE at the
primary circuit must be used within the above-described
range. If the drive voltage of LCD panel can be boosted
by utilizing the voltage level of VDD, usually connect this
pin to VDD power supply.
38
LH1594/LH1595
12. ELECTRICAL CHARACTERISTICS
12.1. DC Characteristics
(Unless otherwise specified, VSS = 0 V, VDD = +2.2 to +5.5 V, TOPR = –30 to +85 °C)
PARAMETER
SYMBOL
Input "Low" voltage
VIL
Input "High" voltage
VIH
Output "Low" voltage
Output "High" voltage
VOL
VOH
Input leakage current
ILI
Output leakage current
LCD drive output ON
resistance
Static LCD drive
output ON resistance
ILO
RON1
RON2
Standby current
ISTB
Supply current (1)
IDD1
Supply current (2)
IDD2
Oscillation frequency
fOSC
Boosted output voltage VOUT
Reset ("L") pulse width
CONDITIONS
APPLICABLE PINS
MIN. TYP. MAX. UNIT NOTE
D7-D0, CSB, RS, M86, RDB,
0
0.2VDD V
WRB, CK, CKS, OSCI, P/S,
VDD
V
RESB, PMODE, SHL0, SHL1 0.8VDD
IOL = 0.4 mA
0.4
V
D7-D0, LP, FLM, M
IOH = –0.4 mA
VDD – 0.4
V
CSB, RS, M86, RDB, WRB,
CK, CKS, OSCI, P/S, RESB, –10
VI = VSS or VDD
10
µA
PMODE, SHL0, SHL1
VI = VSS or VDD
D7-D0, LP, FLM, M
–10
10
µA
1
|∆VON|
SEG0-SEG79, COM0-COM15,
V0 = 8 V
4
8
k$
2
= 0.5 V
COMI
|∆VON| = 0.5 V
SEGS0-SEGS9, COMS
8
k$
VDD
5
10
µA
3
CK = 0 V VDD = 3 V
CSB = VDD VDD = 5 V
Boosting VDD = 3 V
3 times V0 = 6 V
Boosting VDD = 3 V
2 times V0 = 5 V
RF =
VDD = 3 V
1.2 M$±2%
Boosting
VEE = 3 V
3 times
Boosting
VEE = 3 V
2 times
VDD, VEE
50
90
µA
4
VDD, VEE
35
60
µA
4
55
80
kHz
5
V
6
OSCO
30
8.6
VOUT
5.7
tRW
RESB
10
µs
NOTES :
1. Applied when D7 to D0, LP, FLM, and M are in the high
impedance state.
2. Resistance when 0.5 V is applied between each output
pin and each power supply (V0, V1, V2, V3, V4 or VSS).
Applied when power is supplied at power bias ratio of
1/7 in the external power supply mode.
3. Current at the VDD pin when the master clock stops, the
chip is not selected (CSB = VDD), and no load is used.
All circuits stop.
4. Applied when no access is made by the MPU when the
internal oscillation circuit (RF = 1.2 M$) and power
supply circuit (PMODE = "L") are used. The electronic
volume is pre-set (the code is "1 1 1 1"). The display is
fully lit-up (ALON = "1") and the LCD drive pin is not
loaded.
Measuring conditions : VDD = VEE, VR1 = VR2, C1 = C2 =
1 µF, R1 + R2 + R3 = 4 M$, the current flowing through
voltage control resistors (R1, R2, and R3) is included.
5. Oscillation frequency when connecting a feedback
resistor (RF) of 1.2 M$ between OSCI and OSCO.
6. Applied when the internal oscillation circuit (RF = 1.2
M$) and power supply circuit (PMODE = "L") are used.
Measuring conditions : C1 = C2 = 1 µF, VOUT pin is
connected only to C1 and the LCD drive pin is not loaded.
39
LH1594/LH1595
12.2. AC Characteristics
12.2.1. SYSTEM BUS READ/WRITE TIMING (80-FAMILY MPU)
(Write Timing)
tAS8
tAH8
CSB
RS
tWRW8
WRB
tDS8
tDH8
D7-D0
tCYC8
(Read Timing)
tAS8
tAH8
CSB
RS
tRDW8
RDB
tRDH8
D7-D0
tRDD8
tCYC8
40
LH1594/LH1595
(80-family MPU Timing Characteristics)
PARAMETER
Address hold time
SYMBOL
tAH8
Address setup time
tAS8
System cycle time
tCYC8
Read pulse width
tRDW8
Write pulse width
tWRW8
Data setup time
tDS8
Data hold time
tDH8
Read data output delay time
tRDD8
Read data hold time
tRDH8
Input signal rise and fall time
tR, tF
(VDD = 4.5 to 5.5 V, TOPR = –30 to +85 ˚C)
CONDITIONS
APPLICABLE PINS
CSB
MIN.
60
RS
20
400
WRB
RDB
D7-D0
CL = 15 pF
D7-D0
MAX.
UNIT
ns
ns
ns
200
ns
50
50
ns
ns
20
150
10
All of above pins
ns
ns
ns
15
ns
(VDD = 2.7 to 4.5 V, TOPR = –30 to +85 ˚C)
PARAMETER
Address hold time
SYMBOL
tAH8
Address setup time
tAS8
System cycle time
tCYC8
Read pulse width
tRDW8
Write pulse width
tWRW8
Data setup time
tDS8
Data hold time
tDH8
Read data output delay time
tRDD8
Read data hold time
tRDH8
Input signal rise and fall time
tR, tF
CONDITIONS
APPLICABLE PINS
CSB
MIN.
100
RS
40
600
ns
ns
400
ns
100
100
ns
ns
WRB
RDB
D7-D0
CL = 15 pF
D7-D0
MAX.
40
300
ns
ns
15
ns
ns
10
All of above pins
UNIT
ns
(VDD = 2.2 to 2.7 V, TOPR = –30 to +85 ˚C)
PARAMETER
Address hold time
Address setup time
SYMBOL
tAH8
CONDITIONS
tAS8
System cycle time
tCYC8
Read pulse width
tRDW8
Write pulse width
tWRW8
Data setup time
tDS8
Data hold time
tDH8
Read data output delay time
tRDD8
Read data hold time
tRDH8
Input signal rise and fall time
tR, tF
APPLICABLE PINS
CSB
MIN.
200
RS
80
1 200
ns
ns
600
150
ns
ns
WRB
RDB
D7-D0
CL = 15 pF
D7-D0
All of above pins
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
41
MAX.
UNIT
ns
150
ns
80
500
ns
ns
30
ns
ns
10
LH1594/LH1595
12.2.2. SYSTEM BUS READ/WRITE TIMING (68-FAMILY MPU)
(Write Timing)
tCYC6
E
tEW6
R/W
tAS6
CSB
RS
tDS6
tAH6
D7-D0
tDH6
(Read Timing)
tCYC6
E
tEW6
R/W
tAS6
tAH6
CSB
RS
D7-D0
tRDD6
42
tRDH6
LH1594/LH1595
(68-family MPU Timing Characteristics)
PARAMETER
Address hold time
SYMBOL
tAH6
Address setup time
tAS6
System cycle time
tCYC6
Enable pulse width (READ)
Enable pulse width (WRITE)
Data setup time
(VDD = 4.5 to 5.5 V, TOPR = –30 to +85 ˚C)
CONDITIONS
RS
E
tEW6
tDS6
Data hold time
tDH6
Read data output delay time
tRDD6
Read data hold time
tRDH6
Input signal rise and fall time
tR, tF
APPLICABLE PINS
CSB
D7-D0
CL = 15 pF
D7-D0
MIN.
60
MAX.
UNIT
ns
20
ns
400
ns
200
ns
50
ns
50
ns
20
150
10
All of above pins
ns
ns
ns
15
ns
(VDD = 2.7 to 4.5 V, TOPR = –30 to +85 ˚C)
PARAMETER
Address hold time
SYMBOL
tAH6
Address setup time
tAS6
System cycle time
tCYC6
Enable pulse width (READ)
Enable pulse width (WRITE)
Data setup time
CONDITIONS
RS
E
tEW6
tDS6
Data hold time
tDH6
Read data output delay time
tRDD6
Read data hold time
tRDH6
Input signal rise and fall time
tR, tF
APPLICABLE PINS
CSB
D7-D0
CL = 15 pF
D7-D0
MIN.
100
MAX.
UNIT
ns
40
ns
600
ns
400
ns
100
ns
100
ns
40
300
ns
ns
15
ns
ns
10
All of above pins
(VDD = 2.2 to 2.7 V, TOPR = –30 to +85 ˚C)
PARAMETER
Address hold time
SYMBOL
tAH6
Address setup time
tAS6
System cycle time
tCYC6
Enable pulse width (READ)
Enable pulse width (WRITE)
CONDITIONS
tDS6
Data hold time
tDH6
Read data output delay time
tRDD6
Read data hold time
tRDH6
Input signal rise and fall time
tR, tF
MIN.
200
RS
80
E
tEW6
Data setup time
APPLICABLE PINS
CSB
D7-D0
CL = 15 pF
D7-D0
All of above pins
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
43
MAX.
UNIT
ns
ns
1 200
ns
600
150
ns
ns
150
ns
80
500
ns
ns
30
ns
ns
10
LH1594/LH1595
12.2.3. SERIAL INTERFACE TIMING (I2C BUS) [FOR LH1594]
SDA
tBUF
tLOW
tR
tHD:DAT
tSU:DAT
tSU:STA
SCL
tHD:STA
tSU:STO
tF
tHIGH
fSCL
(VDD = 2.2 to 5.5 V, TOPR = –30 to +85 ˚C)
PARAMETER
SCL clock frequency
Start condition hold time
SYMBOL
fSCL
tHD:STA
SCL LOW time
tLOW
SCL HIGH time
tHIGH
Bus free time
tBUF
Data setup time
tSU:DAT
Data hold time
tHD:DAT
Setup time for START condition
tSU:STA
Setup time for STOP condition
SCL and SDA rise time
tSU:STO
tR
SCL and SDA fall time
CONDITIONS
MIN.
SCL
4.7
4.7
µs
µs
4
4.7
µs
µs
250
ns
0
4.7
ns
µs
SDA
SCL
SDA
tF
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
44
MAX.
100
APPLICABLE PINS
4
UNIT
kHz
1
µs
µs
0.3
µs
LH1594/LH1595
12.2.4. SERIAL INTERFACE TIMING [FOR LH1595]
tCSS
tCSH
CSB
RS
tASS
tAHS
tSLW
tSHW
SCL
tDSS
tDHS
SDA
tCYCS
(VDD = 4.5 to 5.5 V, TOPR = –30 to +85 ˚C)
PARAMETER
Serial clock period
SYMBOL
tCYCS
SCL "H" pulse width
SCL "L" pulse width
tSHW
tSLW
Address setup time
Address hold time
tASS
tAHS
Data setup time
tDSS
Data hold time
tDHS
CSB to SCL time
tCSS
CSB hold time
tCSH
Input signal rise and fall time
tR, tF
CONDITIONS
APPLICABLE PINS
MIN.
500
SCL
200
200
ns
ns
40
40
ns
ns
200
ns
200
40
ns
ns
RS
SDA
CSB
MAX.
40
All of above pins
15
UNIT
ns
ns
ns
(VDD = 2.2 to 4.5 V, TOPR = –30 to +85 ˚C)
PARAMETER
Serial clock period
SYMBOL
tCYCS
SCL "H" pulse width
SCL "L" pulse width
tSHW
tSLW
Address setup time
tASS
tAHS
Address hold time
Data setup time
tDSS
Data hold time
tDHS
CSB to SCL time
tCSS
CSB hold time
tCSH
Input signal rise and fall time
tR, tF
CONDITIONS
APPLICABLE PINS
MIN.
1 000
SCL
400
UNIT
ns
ns
400
ns
RS
80
80
ns
ns
SDA
400
400
ns
ns
80
ns
CSB
All of above pins
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
45
MAX.
80
30
ns
ns
LH1594/LH1595
13. CONNECTION EXAMPLES OF REPRESENTATIVE APPLICATIONS
(a) Connection to The 80-family MPU
2.2 to 5.5 V
VDD
VCC
A0
RS
A7-A1
7
Æ
(80-family MPU) D7-D0
Decoder
8
CSB
D7-D0
˛
RDB
ª
WRB
(LH1594/LH1595)
RESB
º
GND
VSS
Reset input
(b) Connection to The 68-family MPU
2.2 to 5.5 V
VDD
VCC
A0
RS
A15-A1
VMA
(68-family MPU) D7-D0
15
Decoder
8
CSB
D7-D0
(LH1594/LH1595)
RDB (E)
E
R/¸
WRB (R/W)
º
RESB
GND
Reset input
46
VSS
LH1594/LH1595
(c) Connection to The MPU with Serial Interface
2.2 to 5.5 V
VDD
VCC
A0
RS
A7-A1
7
(MPU)
Decoder
CSB
PORT1
SDA
PORT2
SCL
(LH1594/LH1595)
RESB
º
GND
Reset input
VSS
* When connecting multiple LH1594/LH1595s, input to each CSB pin by varying the decoder conditions of
address signals.
47
LH1594F
Ø2.0
(Good device hole)
2.0 (SL)
12.9
3.65 (SR)
4.05 (SR)
[6.45 (Cut line)]
UPILEX is a trademark of UBE INDUSTRIES, LTD..
48
DUMMY
COMI
COM15
COM14
5.4MAX.
(Resin area)
COM9
COM8
COMS
SEGS9
SEGS8
SEGS7
SEGS6
SEGS5
SEG79
SEG78
SEG1
SEG0
SEGS0
SEGS1
SEGS2
SEGS3
SEGS4
COMS
COMI
COM0
COM1
COM6
COM7
DUMMY
[7.05 (Cut line)]
5.85±0.05
8.8±0.5
[13.5 (Cut line)]
0.4±0.02
0.6±0.02
Substrate
Adhesive
Cu foil [thickness]
Solder resist
ø Tape Material
UPILEX S75
#7100
VLP 25 µm
Epoxy resin
1.0(SL)
1.42
Tape width
Tape type
Perforation pitch
12.9
1.42
4.75
35 mm
Super wide
4 pitches
[26.8 (Cut line)]
25.4±0.035
P0.22 x (112 – 1) = 24.42±0.03 W0.11
Ø1.2 (Hole)
Ø1.8 (SR)
7.9 (SL)
[0.5]
ø Tape Specification
5.525
13.2MAX. (Resin area)
20.0±0.05 (Holes)
9.85 (SL)
Pattern side
0.2MAX.
1.1MAX.
Total
Chip center
Sprocket center
0.75MAX.
Backside
14. PACKAGE
0.6±0.02
0.2
5.525
P0.55 x (43 – 1) = 23.1±0.03 W0.275±0.02
V0
V1
V2
V3
V4
VSS
SHL0
VDD
SHL1
VSS
TEST
RESB
CSB
RS
M86
P/S
WRB
RDB
PMODE
CK
CKS
OSCI
OSCO
LP
FLM
M
D0
D1
D2
D3
D4/ISEL
D5/SA0
D6/SCL
D7/SDA
VDD
VEE
CAP1–
CAP1+
CAP2–
CAP2+
VOUT
VR1
VR2
5.1 (SL)
[0.5]
0.4±0.02
Device center
2.7 (SL)
1.0(SL)
25.4 (SL)
31.82
34.975
0.6 (SL)
2-R0.9 (SR)
2-R0.6 (Hole)
12.5±0.5
Film center
PACKAGES FOR LCD DRIVERS
(Unit : mm)
7.8
2.7 (SL)
3.95
[3.0TYP.(2.7MIN.)]