WED9LC6816V White Electronic Designs 256Kx32 SSRAM/4Mx32 SDRAM EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP DESCRIPTION FEATURES The WED9LC6816V is a 3.3V, 256K x 32 Synchronous Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with one 256K x 32 SBSRAM and two 4Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm x 22mm, BGA. Clock speeds: SSRAM: 200, 166,150, and 133 MHz SDRAMs: 125 and 100 MHz DSP Memory Solution The WED9LC6816V provides a total memory solution for the Texas Instruments TMS320C6201 and the TMS320C6701 DSPs The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150,v and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port . Texas Instruments TMS320C6201 Texas Instruments TMS320C6701 Packaging: 153 pin BGA, JEDEC MO 163 3.3V Operating supply voltage Common address and databus The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port. Direct control interface to both the SSRAM and SDRAM ports on the “C6x” The WED9LC6816V is available in both commercial and industrial temperature ranges. 65% space savings vs. monolithic solution Reduced system inductance and capacitance This product is subject to change without notice. FIG. 1 PIN CONFIGURATION TOP VIEW PIN DESCRIPTION 1 2 3 4 5 6 7 8 9 A0-17 A DQ19 DQ23 VCC VSS VSS VSS VCC DQ24 DQ28 DQ0-31 Address Bus Data Bus B DQ18 DQ22 VCC VSS SDCE# VSS VCC DQ25 DQ29 SSCK# SSRAM Clock SSRAM Address Status Control C VCCQ VCCQ VCC SDWE# SDA10 NC VCC VCCQ VCCQ SSADC# D DQ17 DQ21 VCC VSS VSS VSS VCC DQ26 DQ30 SSWE# SSRAM Write Enable E DQ16 DQ20 VCC VSS SDCK VSS VCC DQ27 DQ31 SSOE# SSRAM Output Enable VSS VSS VSS VCC VCCQ VCCQ SDCK SDRAM Clock SDRAS# SDCAS# VSS A2 A4 A5 SDRAS# SDRAM Row Address Strobe SDRAM Column Address Strobe F VCCQ VCCQ VCC G NC NC NC H NC NC A8 VSS VSS NC A1 A3 A10 SDCAS# J A6 A7 A9 VSS VSS NC A0 A11 A12 SDWE# SDRAM Write Enable K A17 VSS VSS NC NC A13 A14 SDA10 SDRAM Address 10/auto precharge SSRAM Byte Write Enables SDRAM SDQM 0-3 NC/A18 NC/A19 L NC NC NC BWE2# BWE3# NC NC A15 A16 BWE0-3# M VCCQ VCCQ VCC BWE0# BWE1# NC VCC VCCQ VCCQ SSCE Chip Enable SSRAM Device N DQ12 DQ11 VCC VSS VSS VSS VCC DQ4 DQ0 SDCE Chip Enable SDRAM Device P DQ13 DQ10 VCC VSS SSCK VSS VCC DQ5 DQ1 VCC Power Supply pins, 3.3V R VCCQ VCCQ VCC VSS VSS VSS VCC VCCQ VCCQ VCCQ Data Bus Power Supply pins, 3.3V (2.5V future) T DQ14 DQ9 VCC SSADC# SSWE# NC VCC DQ6 DQ2 VSS Ground U DQ15 DQ8 VCC NC VCC DQ7 DQ3 NC No Contact SSOE# SSCE# Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 2 BLOCK DIAGRAM A0-17 A0 A1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 SSWE# BWE0# BWE1# BWE2# BWE3# BWE# BW1# BW2# BW3# BW4# SSCE# SSOE# SSADC# CE2# OE# ADSC# SSCK# SDA10 DQ1-8 DQ0-7 DQ9-16 DQ8-15 DQ17-24 DQ16-23 DQ25-32 DQ24-31 CK# A12 A13 SDCE# SDRAS# SDCAS# SDWE# SDCK# A12 A13 DQ0-31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A10/AP BA0 BA1 LDQM# UDQM# CS# RAS# CAS# WE# CK# DQ8-15 DQ8-15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A10/AP BA0 BA1 LDQM# UDQM# CS# RAS# CAS# WE# CK# DQ0-7 DQ16-23 DQ8-15 DQ24-31 DQ0-7 DQ0-7 Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LC6816V Output Functional Descriptions Symbol Type Signal Polarity Function SSCK# Input Pulse Positive Edge SSADS# SSOE# SSWE# Input Pulse Active Low When sampled at the positive rising edge of the clock, SSADS#, SSOE#, and SSWE# define the operation to be executed by the SSRAM. SSCE# Input Pulse Active Low SSCE# disable or enable SSRAM device operation. SDCK# Input Pulse Positive Edge SDCE Input Pulse Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCK# and BWE0-3. SDRAS# SDCAS# SDWE# Input Pulse Active Low When sampled at the positive rising edge of the clock, SDCAS#, SDRAS#, and SDWE# define the operation to be executed by the SDRAM. The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Address bus for SSRAM and SDRAM A0 and A1 are the burst address inputs for the SSRAM During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10) when sampled at the rising clock edge. A0-17 SDA10 Input Level — During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A12 and A13 define the bank to be precharged. If SDA10 is low, autoprecharge is disabled. During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control which bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless of the state of A12 and A13. If SDA10 is low, then A12 and A13 are used to define which bank to precharge. DQ0-31 Input Output Level BWE0-3 Input Pulse VCC, VSS Supply VCCQ , — Supply Data Input/Output are multiplexed on the same pins. BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31. Power and ground for the input buffers and the core logic. Data base power supply pins, 3.3V (2.5V future). Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs Absolute Maximum Ratings Voltage on VCC Relative to VSS VIN (DQx) Recommended DC Operating Conditions (Vcc = 3.3V -5% / +10% unless otherwise noted; 0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial) -0.5V to +4.6V -0.5V to Vcc +0.5V Parameter -55°C to +125°C Storage Temperature (BGA) Junction Temperature +150°C Short Circuit Output Current 100 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Min Max Units Supply Voltage (1) VCC 3.135 3.6 V Input High Voltage (1,2) VIH 2.0 VCC +0.3 V Input Low Voltage (1,2) VIL -0.3 0.8 V Input Leakage Current 0 VIN VCC ILI -10 10 A Output Leakage (Output Disabled) 0 VIN VCC ILO -10 10 A SSRAM Output High (IOH = -4mA) (1) VOH 2.4 — V SSRAM Output Low (IOL = 8mA) (1) VOL — 0.4 V SDRAM Output High (IOH = -2mA) VOH 2.4 — V SDRAM Output Low (IOL = 2mA) VOL — 0.4 V NOTES: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +6.0V for t tKC/2 Underershoot: VIL -2.0V for t tKC/2 DC Electrical Characteristics (Vcc = 3.3V -5% / +10% unless otherwise noted; 0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial) Description Power Supply Current Operating (1, 2, 3) Power Supply Current Operating (1, 2, 3) Power Supply Current Operating (1, 2, 3) CMOS Standby TTL Standby Conditions Symbol SSRAM Active / DRAM Auto Refresh ICC1 ICC2 SSRAM Active / DRAM Idle SSRAM Active / SSRAM Idle SSCE# and SDCE# VCC -0.2V, All other inputs at VSS +0.2 VIN or VIN VCC -0.2V, Clk frequency = 0 SSCE# and SDCE# VIH min All other inputs at VIL max VIN or VIN VCC -0.2V, CK# frequency = 0 Auto Refresh Frequency Typ Max 133MHz 500 625 150MHz 500 650 166MHz 550 700 200MHz 600 800 133MHz 325 425 150MHz 350 450 166MHz 400 495 200MHz 450 585 Units mA mA 83MHz 500 625 100MHz 500 650 125MHz 550 700 ISB1 20.0 40.0 mA ISB2 30.0 55.0 mA ICC5 250 300 mA ICC3 mA NOTES: 1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading. 2. "Device idle" means device is deselected (CE# = VIH) Clock is running at max frequency and Addresses are switching each cycle. 3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs SSRAM AC Characteristics (Vcc = 3.3V -5% / +10% unless otherwise noted; 0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial) Parameter 200MHz Min Max Symbol 166MHz Min Max 150MHz Min Max 133MHz Min Max Units Clock Cycle Time tKHKH 5 6 7 8 ns Clock HIGH Time tKLKH 1.6 2.4 2.6 2.8 ns Clock LOW Time tKHKL 1.6 2.4 2.6 2.8 ns Clock to output valid tKHQV Clock to output invalid tKHQX 1.5 1.5 1.5 1.5 Clock to output on Low-Z tKQLZ 0 0 0 0 Clock to output in High-Z tKQHZ 1.5 Output Enable to output valid tOELQV Output Enable to output in Low-Z tOELZ Output Enable to output in High-Z tOEHZ 2.5 3.5 3 1.5 2.5 3.5 3.8 1.5 3.5 0 0 3.0 3.8 4.0 1.5 3.8 0 3.5 ns ns 4.0 ns 4.0 ns 0 3.5 ns ns 3.8 ns Address, Control, Data-in Setup Time to Clock tS 1.5 1.5 1.5 1.5 ns Address, Control, Data-in Hold Time to Clock tH 0.5 0.5 0.5 0.5 ns BGA Capacitance Description Conditions Symbol Typ Max Units Address Input Capacitance (1) TA = 25°C; f = 1MHz CI 5 8 pF Input/Output Capacitance (DQ) (1) TA = 25°C; f = 1MHz CO 8 10 pF Control Input Capacitance (1) TA = 25°C; f = 1MHz CA 5 8 pF Clock Input Capacitance (1) TA = 25°C; f = 1MHz CCK 4 6 pF NOTE: 1. This parameter is sampled. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs SSRAM Operation Truth Table Operation Address Used SSCE# SSADS# SSWE# SSOE# DQ None H L X X High-Z WRITE Cycle, Begin Burst External L L L X D READ Cycle, Begin Burst External L L H L Q READ Cycle, Begin Burst External L L H H High-Z READ Cycle, Suspend Burst Current X H H L Q READ Cycle, Suspend Burst Current X H H H High-Z READ Cycle, Suspend Burst Current H H H L Q READ Cycle, Suspend Burst Current H H H H High-Z WRITE Cycle, Suspend Burst Current X H L X D WRITE Cycle, Suspend Burst Current H H L X D Deselected Cycle, Power Down NOTE: 1. X means “don’t care”, H means logic HIGH. L means logic LOW. 2. All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to HIGH) of SSCK. 3. Suspending burst generates wait cycle 4. For a write operation following a read operation, SSOE# must be HIGH before the input data required setup time plus High-Z time for SSOE# and staying HIGH through out the input data hold time. 5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. SSRAM Partial Truth Table Function SSWE# BWE0# BWE1# BWE2# BWE3# READ H X X X X WRITE one Byte (DQ0-7) L L H H H WRITE all Bytes L L L L L Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 3 SSRAM READ TIMING tKHKL tKLKH tKHKH SSCK tS tH SSADS# tS SSCE# tH tS ADDR A1 A2 A3 A5 A4 tH SSOE# tOEHZ tOELQ V SSWE# tKHQX tKHQV tKQLZ Q(A1) DQ Q(A2) Q(A3) Q(A4) Q(A5) FIG. 4 SSRAM WRITE TIMING tKHK H t KHK L t KLKH SSCK tH tS SSADS# tH SSCE# tH tS A2 A1 ADDR A3 A4 A5 tH t OEHZ SSOE# Must be HIGH KHG WX tS tH SSWE# tS DQ D(A1) tH D(A2) D(A3) D (A4) D(A5) Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs SDRAM AC Characteristics (Vcc = 3.3V -5% / +10% unless otherwise noted; 0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial) 125MHz Parameter Clock Cycle Time (1) CL = 3 CL = 2 100MHz 83MHz Symbol Min Max Min Max Min Max Units tCC 8 1000 10 1000 12 1000 ns tCC 10 1000 12 1000 15 1000 ns 8 ns Clock to valid Output delay (1,2) tSAC 6 7 Output Data Hold Time (2) tOH 3 3 3 ns Clock HIGH Pulse Width (3) tCH 3 3 3 ns Clock LOW Pulse Width (3) tCL 3 3 3 ns Input Setup Time (3) tSS 2 2 2 ns Input Hold Time (3) tSH 1 1 1 ns CK# to Output Low-Z (2) tSLZ 2 2 2 CK# to Output High-Z tSHZ Row Active to Row Active Delay (4) tRRD 20 20 24 ns RAS# to CAS# Delay (4) tRCD 20 20 24 ns Row Precharge Time (4) tRP 20 Row Active Time (4) tRAS 50 Row Cycle Time - Operation (4) tRC 70 80 90 Row Cycle Time - Auto Refresh (4,8) tRFC 70 80 90 ns Last Data in to New Column Address Delay (5) tCDL 1 1 1 CK# Last Data in to Row Precharge (5) tRDL 1 1 1 CK# Last Data in to Burst Stop (5) tBDL 1 1 1 CK# Column Address to Column Address Delay (6) tCCD 1.5 1.5 1.5 CK# 2 2 2 ea 1 2 1 7 Number of Valid Output Data (7) 7 20 10,000 50 ns 8 24 10,000 60 ns ns 10,000 ns ns NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (trise/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(trise = tfall)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self-refresh exit. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs Clock Frequency and Latency Parameters - 125MHz SDRAM (Unit = number of clock) CAS Latency tRC 70ns tRAS 50ns tRP 20ns tRRD 20ns tRCD 20ns tCCD 10ns tCDL 10ns tRDL 10ns 125MHz (8.0ns) 3 9 6 3 2 3 1 1 1 100MHz (10.0ns) 3 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 4 2 2 2 1 1 1 Frequency Clock Frequency and Latency Parameters - 100MHz SDRAM (Unit = number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100MHz (12.0ns) 3 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 5 2 2 2 1 1 Frequency Refresh Cycle Parameters Parameter Refresh Period (1,2) Symbol -10 Min tREF — Max -12 Min 64 — Max Units 64 ms NOTES: 1. 4096 cycles 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. SDRAM Command Truth Table SDA10 Function Mode Register Set Auto Refresh (CBR) SDCE# SDRAS# SDCAS# SDWE # BWE# L L L L X A12, A13 A11-0 Notes OP CODE L L L H X X Single Bank L L H L X BA L Precharge all Banks L L H L X X H Bank Activate L L H H X BA Row Address 2 Write L H L L X BA L 2 Write with Auto Precharge L H L L X BA H 2 Read L H L L X BA L 2 Read with Auto Precharge L H L H X BA H 2 Burst Termination L H H L X X X 3 No Operation L H H H X X X Device Deselect H X X X X X X Data Write/Output Disable X X X X L X X 4 Data Mask/Output Disable X X X X H X X 4 Precharge X 2 NOTES: 1. All of the SDRAM operations are defined by states of SDCE#, SDWE#, SDRAS#, SDCAS#, and BWE0-3# at the positive rising edge of the clock. 2. Bank Select (BA), A12 (BA0) and A13 (BA1) select between different banks. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. The BWE# has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE# goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. BWE# also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs MODE REGISTER SET TABLE A11 A10 A9 A8 A7 A6 A5 A3 A4 A2 A1 A0 Address Bus Mode Register (Mx) Reserved* WB Op Mode CAS# Latency BT Burst Length *Should program M11, M10 = "0, 0" to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access All other states reserved Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs SDRAM CURRENT STATE TRUTH TABLE Current State Idle Row Active Read Write Read with Auto Precharge Command SDCE# SDRAS # SDCAS# SDWE# A12 & A13 (BA) A11-A0 Description Action Notes L L L L OP Code Mode Register Set Set the Mode Register 1 L L L H X X Auto or Self Refresh Start Auto L L H L X X Precharge No Operation L L H H BA Row Address Bank Activate Activate the specified bank and row L H L L BA Column Write w/o Precharge ILLEGAL 2 L H L H BA Column Read w/o Precharge ILLEGAL 1 L H H L X X Burst Termination No Operation 1 L H H H X X No Operation No Operation H X X X X Device Deselect No Operation L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge Precharge L L H H BA Row Address Bank Activate ILLEGA 1 L H L L BA Column Write Start Write; Determine if Auto Precharge 4,5 L H L H BA Column Read Start Read; Determine if Auto Precharge 4,5 L H H L X X Burst Termination No Operation X OP Code 1 3 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge Terminate Burst; Start the Precharge L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write Terminate Burst; Start the Write cycle 5,6 L H L H BA Column Read Terminate Burst; Start a new Read cycle 5,6 L H H L X X Burst Termination Terminate the Burst OP Code L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge Terminate Burst; Start the Precharge L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write Terminate Burst; Start a new Write cycle 5,6 L H L H BA Column Read Terminate Burst; Start the Read cycle 5,6 L H H L X X Burst Termination Terminate the Burst OP Code L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL 2 L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write ILLEGAL L H L H BA Column Read ILLEGAL L H H L X X Burst Termination ILLEGAL L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst OP Code Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs SDRAM Current State Truth Table (cont.) Current State Write with Auto Precharge Precharging Row Activating Write Recovering With Recovering with Auto Precharging Command SDCE# SDRAS # SDCAS# SDWE# A12 & A13 (BA) A11-A0 Description OP Code Action Notes L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL 2 L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write ILLEGAL ILLEGAL L H L H BA Column Read L H H L X X Burst Termination ILLEGAL L H H H X X No Operation Continue the Burst H X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge No Operation; Bank(s) idle after tRP X OP Code L L H H BA Row Address Bank Activate ILLEGAL L H L L BA Column Write w/o Precharge ILLEGAL 2 L H L H BA Column Read w/o Precharge ILLEGAL 20 L H H L X X Burst Termination No Operation; Bank(s) idle after tRP L H H H X X No Operation No Operation; Bank(s) idle after tRP H X X X X X Device Deselect No Operation; Bank(s) idle after tRP L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL 2 L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write ILLEGAL 2 L H L H BA Column Read ILLEGAL 2 L H H L X X Burst Termination No Operation; Row active after tRCD OP Code 2 L H H H X X No Operation No Operation; Row active after tRCD H X X X X X Device Deselect No Operation; Row active after tRCD L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL 2 L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write Start Write; Determine if Auto Precharge 6 L H L H BA Column Read Start Read; Determine if Auto Precharge 6 L H H L X X Burst Termination No Operation; Precharge after tDPL OP Code L H H H X X No Operation No Operation; Precharge after tDPL H X X X X X Device Deselect No Operation; Precharge after tDPL L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write ILLEGAL 2,6 L H L H BA Column Read ILLEGAL 2,6 L H H L X X Burst Termination No Operation; Precharge after tDPL L H H H X X No Operation No Operation; Precharge after tDPL H X X X X X Device Deselect No Operation; Precharge after tDPL OP Code 2 Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs SDRAM Current State Truth Table (cont.) Current State Refreshing Mode Register Accessing Command SDCE# SDRAS # SDCAS# SDWE# L L L L L L L H L L H L L L H L L A12 & A13 (BA) Action A11-A0 Description Mode Register Set ILLEGAL X X Auto or Self Refresh ILLEGAL L X X Precharge ILLEGAL H H BA Row Address Bank Activate ILLEGAL L L BA Column Write ILLEGAL H L H BA Column Read ILLEGAL H H L X X Burst Termination No Operation; Idle after tRC OP Code L H H H X X No Operation No Operation; Idle after tRC H X X X X X Device Deselect No Operation; Idle after tRC L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL L L H H BA Row Address Bank Activate ILLEGAL L H L L BA Column Write ILLEGAL L H L H BA Column Read ILLEGAL L H H L X X Burst Termination ILLEGAL L H H H X X No Operation No Operation; Idle after two clock cycles H X X X X X Device Deselect No Operation; Idle after two clock cycles OP Code Notes NOTES: 1. Both Banks must be idle otherwise it is an illegal action. 2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 3. The minimum and maximum Active time (tRAS) must be satisfied. 4. The RAS# to CAS# Delay (tRCD) must occur before the command is given. 5. Address SDA10 is used to determine if the Auto Precharge function is activated. 6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 5 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3, BURST LENGTH = 1 0 2 1 4 3 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK tCH tCC tCL tRCD tRAS SDCE# tSS tRCD tSH tRP tSH tSS SDRAS# tSS tCCD tSH SDCAS# tSS tSH tSH tSS ADDR Ra Ca Cb Cc BA0, 1 [A12,A13] BS BS BS BS SDA10 Ra Rb BS BS Rb tRAC tSS tSAC Qa DQ tSLZ tOH tSH Qc Db tSS tSH tSS tSH SDWE# BWE# Row Active Read Read Write Row Active Precharge DON’T CARE Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 6 SDRAM POWER UP SEQUENCE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK SDCE# tRFC tRP tRFC SDRAS# SDCAS# ADDR Key RAa BA0,1 [A12,A13] RAa SDA10 HIGH-Z DQ SDWE# BWE# High level is necessary Precharge (All Banks) Auto Refresh Mode Register Set Auto Refresh Row Active (A-Bank) DON’T CARE Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 1 0 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK Note 1 tRC SDCE# tRCD SDRAS# SDCAS# ADDR Ra Ca0 Rb Cb0 BA0, 1 [A12,A13] SDA10 Ra Rb tRAC Note 3 tSHZ Note 4 Qa0 CL=2 tRAC Note 3 DQ Qa1 Qa2 Db0 Qa3 Qa1 Db1 Db2 tSHZ Note 4 tOH tSAC Qa0 CL=3 tRDL tOH tSAC tRDL Qa3 Qa2 Db3 Db0 Db1 Db2 Db3 SDWE# BWE# Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS# Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS# Latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 1 0 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK SDCE# tRCD SDRAS# Note 2 SDCAS# ADDR Ra Cb0 Ca0 Cc0 Cd0 BA0, 1 [A12,A13] SDA10 Ra tRDL Qa0 CL=2 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Qa0 Qa1 Qa2 Qa3 Dc0 Dc1 DQ Dd0 Dd1 Dd0 Dd1 tCDL CL=3 SDWE# Note 3 Note 1 BWE# Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. To write data before burst read ends. BWE# should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written. 3. BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 17 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 1 0 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK Note 1 SDCE# SDRAS# Note 2 SDCAS# ADDR RAa CAa RBb CBb CAc CBd CAe BA0, 1 [A12,A13] SDA10 RAa RBb QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 CL=2 DQ QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 Qbb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 CL=3 SDWE# BWE# Row Active (A-Bank) Row Active (B-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Precharge (A-Bank) DON’T CARE Read (A-Bank) NOTES: 1. SDCE# can be “don’t care” when SDRAS#, SDCAS# and SDWE# are high at the clock going high edge. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 18 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 10 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK SDCE# SDRAS# Note 2 SDCAS# ADDR RAa CAa RBb CBb CAc CBb BA0, 1 [A12,A13] SDA10 RAa RBb tCDL tRDL DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 DQ SDWE# Note 1 BWE# Row Active (A-Bank) Row Active (A-Bank) Write (A-Bank) Write (B-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) DON’T CARE NOTES: 1. To interrupt burst write by Row precharge, BWE# should be asserted to mask invalid input data. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 19 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 11 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK SDCE# SDRAS# SDCAS# ADDR RAa RBb CAa CBb RAc CAc BA0, 1 [A12,A13] SDA10 RAa RBb RAc tCDL QAa0 QAa1 QAa2 QAa3 CL=2 Note 1 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 DQ QAa0 QAa1 QAa2 QAa3 CL=3 SDWE# BWE# Row Active (A-Bank) Read (A-Bank) Write (B-Bank) Precharge (A-Bank) Row Active (A-Bank) Row Active (A-Bank) Read (A-Bank) DON’T CARE NOTES: 1. tCDL should be met to complete write. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 20 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 12 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK SDCE# SDRAS# SDCAS# ADDR Ra Rb Ra Rb Ca Cb BA0, 1 [A12,A13] SDA10 Qa0 CL=2 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 DQ CL=3 Qa3 SDWE# BWE# Row Active (A-Bank) Read with Auto Precharge (A-Bank) Row Active (B-Bank) Write with Auto Precharge (B-Bank) Auto Precharge Start Point (A-Bank) Auto Precharge Start Point (B-Bank) DON’T CARE NOTES: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2 and BRSW mode) Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 21 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 13 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH = FULL PAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK SDCE SDRAS# SDCAS# ADDR RAa CAa CAb BA0, 1 [A12,A13] SDA10 RAa CL=2 Note 2 1 1 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 DQ CL=3 2 2 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 SDWE# BWE# Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is the same as the case of SDRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each of them. But at burst write, burst stop and SDRAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”. 3. Burst stop is valid at every burst length. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 22 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 14 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @ BURST LENGTH = FULL PAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK SDCE# SDRAS# SDCAS# ADDR RAa CAa CAb BA0, 1 [A12,A13] SDA10 RAa tRDL tBDL Note 2 DAb0 DAb1 DAb2 DAb3 DAB4 DAb5 DAa0 DAa1 DAa2 DAa3 DAa4 DQ SDWE# BWE# Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. BWE# at write interrupt by precharge command is needed to prevent invalid write.BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 23 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2 0 1 2 3 4 5 6 RBb CAb 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCK SDCE# SDRAS# SDCAS# ADDR RAa CAa RAc CBc CAd BA0, 1 [A12,A13] SDA10 RBb RAa DAa0 CL=2 RAc DBc0 QAb0 QAb1 QAd0 QAd1 DQ DAa0 CL=3 QAd0 QAd1 DBc0 QAa1 QAb1 SDWE# BWE# Row Active (A-Bank) Row Active Write with (A-Bank) Auto Precharge (B-Bank) Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank) Read (A-Bank) Precharge (Both Banks) DON’T CARE NOTES: 1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 24 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs FIG. 16 SDRAM MODE REGISTER SET CYLE 0 1 2 3 4 5 6 SDRAM AUTO REFRESH CYCLE 7 8 0 1 2 3 4 5 6 7 8 9 10 SDCK HIG H SDCE# Note 2 t RF C SDRAS# Note 1 SDCAS# Note 3 Key ADDR DQ Ra HI- Z HI- Z SDWE# BWE# MR S Ne w Comman d Aut o Refres h Ne w Comman d DON'T CARE *Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle. NOTES: MODE REGISTER SET CYCLE 1. SDCE#, SDRAS#, SDCAS# & SDWE# activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new SDRAS# activation. 3. Please refer to Mode Register Set Table. Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 25 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs PACKAGE DESCRIPTION: 153 LEAD BGA (17 X 9 BALL ARRAY) JEDEC MP-163 3.50 (0.138) MAX 14.00 (0.551) BSC A B PIN 1 INDEX C D E F G H 22.00 (0.866) BSC J K L M N P R T U 1.27 (0.050) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE: Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION COMMERCIAL (0°C TA 70°C) Part Number INDUSTRIAL (-40°C TA 85°C) SSRAM Access SDRAM Access WED9LC6816V2012BC 200MHz 125MHz WED9LC6816V2010BC 200MHz 100MHz WED9LC6816V1612BC 166MHz WED9LC6816V1610BC Part Number SSRAM Access SDRAM Access WED9LC6816V2012BI 200MHz 125MHz WED9LC6816V2010BI 200MHz 100MHz 125MHz WED9LC6816V1612BI 166MHz 125MHz 166MHz 100MHz WED9LC6816V1610BI 166MHz 100MHz WED9LC6816V1512BC 150MHz 125MHz WED9LC6816V1512BI 150MHz 125MHz WED9LC6816V1510BC 150MHz 100MHz WED9LC6816V1510BI 150MHz 100MHz WED9LC6816V1312BC 133MHz 125MHz WED9LC6816V1312BI 133MHz 125MHz WED9LC6816V1310BC 133MHz 100MHz WED9LC6816V1310BI 133MHz 100MHz Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 26 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED9LC6816V White Electronic Designs INTERFACING THE TEXAS INSTRUMENTS TMS 320C6x WITH THE WED9LC6816V (256Kx32 SSRAM/4Mx32 SDRAM) Address Bus EA2-21 EA2 A0 EA3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Texas Instruments TMS320C6x DSP SSWE# CE2# SSOE# SSADS# SSCK BE0# BE1# BE2# BE3# Data Bus ED0-31 SDA10 CE0# SDRAS# SDCAS# SDWE# SDCK EDI9LC644V 128K x 32 SSRAM 1M x 32 SDRAM DQ0-7 DQ8-15 DQ16-23 DQ24-31 SSWE# SSCE# SSOE# SSADC# SSCK SSRAM Control BWE0# BWE1# BWE2# BWE3# Shared Controls SDA10 SDCE# SDRAS# SDCAS# SDWE# SDCK SDRAM Control Contact factory for ordering information. White Electronic Designs Corp. reserves the right to change products or specifications without notice. September, 2003 Rev. 1 27 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com