19-0626; Rev 0; 1/07 KIT ATION EVALU E L B AVAILA 6-Channel High-Speed Logic-Level Translators The MAX13030E–MAX13035E 6-channel, bidirectional level translators provide the level shifting necessary for 100Mbps data transfer in multivoltage systems. The MAX13030E–MAX13035E are ideally suited for memory-card level translation, as well as generic level translation in systems with six channels. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a higher voltage logic signal on the V CC side of the device and vice versa. The MAX13035E features a CLK_RET output that returns the same clock signal applied to the CLK_VL input. The MAX13030E–MAX13035E operate at full speed with external drivers that source as little as 4mA output current. Each I/O channel is pulled up to VCC or VL by an internal 30µA current source, allowing the MAX13030E–MAX13035E to be driven by either pushpull or open-drain drivers. The MAX13030E–MAX13034E feature an enable (EN) input that places the device into a low-power shutdown mode when driven low. The MAX13030E–MAX13035E features an automatic shutdown mode that disables the part when VCC is less than VL. The state of I/O VCC_ and I/O VL_ during shutdown is chosen by selecting the appropriate part version (see Ordering Information/ Selector Guide). The MAX13030E–MAX13035E accept V CC voltages from +2.2V to +3.6V and VL voltages from +1.62V to +3.2V, making them ideal for data transfer between low-voltage ASIC/PLDs and higher voltage systems. The MAX13030E–MAX13035E are available in 16-bump UCSP (2mm x 2mm) and 16-pin TQFN (4mm x 4mm) packages, and operate over the extended -40°C to +85°C temperature range. Features o Compatible with 4mA Input Drivers or Larger o 100Mbps Guaranteed Data Rate o Six Bidirectional Channels o Clock Return Output (MAX13035E) o Enable Input (MAX13030E–MAX13034E) o ±15kV ESD Protection on I/O VCC Lines o +1.62V ≤ VL ≤ +3.2V and +2.2V ≤ VCC ≤ +3.6V Supply Voltage Range o Lead-Free, 16-Bump UCSP (2mm x 2mm) and 16-pin TQFN (4mm x 4mm) Packages Typical Operating Circuits +3.3V +1.8V 0.1μF 0.1μF VL +1.8V SYSTEM CONTROLLER VCC MAX13035E +3.3V SD CARD DAT3 I/O VL_ DAT2 DAT1 I/O VL_ I/O VL_ I/O VCC_ I/O VCC_ I/O VCC_ DAT2 DAT1 DAT0 I/O VL_ I/O VL_ I/O VCC_ DAT0 I/O VCC_ CMD CLK_VCC CLOCK CMD CLOCK CLOCK_IN GND 1μF CLK_VL CLK_RET GND DAT3 GND Applications Typical Operating Circuits continued at end of data sheet. SD Card Level Translation MiniSD Card Level Translation MMC Level Translation Transflash Level Translation Memory Stick Card Level Translation Functional Diagram and Pin Configurations appear at end of data sheet. Ordering Information/Selector Guide PIN-PACKAGE I/O VL_ STATE DURING SHUTDOWN I/O VCC_ STATE DURING SHUTDOWN PKG CODE MAX13030EEBE+ 16 UCSP High impedance High impedance B16-1 MAX13030EETE+ 16 TQFN-EP** High impedance High impedance T1644-4 PART Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead-free package. **EP = Exposed paddle. Ordering Information/Selector guide continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX13030E–MAX13035E General Description MAX13030E–MAX13035E 6-Channel High-Speed Logic-Level Translators ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VCC, VL .....................................................................-0.3V to +4V I/O VCC_, CLK_VCC ....................................-0.3V to (VCC + 0.3V) I/O VL_, CLK_VL, CLK_RET ..........................-0.3V to (VL + 0.3V) EN.............................................................................-0.3V to +4V Short-Circuit Duration I/O VL_, I/O VCC_, CLK_VCC, CLK_VL, CLK_RET to GND.......................Continuous Continuous Power Dissipation (TA = +70°C) 16-Bump UCSP (derate 8.2mW/°C) ..............................660mW 16-Pin TQFN (derate 25.0mW/°C)...............................2000mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Bump Temperature (soldering)........................................+235°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V and TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.20 V POWER SUPPLIES VL Supply Range VCC Supply Range Supply Current from VCC Supply Current from VL VCC Shutdown Supply Current VL Shutdown Supply Current I/O VCC_, I/O VL_, CLK_VCC Tri-State Leakage Current EN Input Leakage Current VL (Note 2) VCC 1.62 3.6 V IQVCC I/O VCC_ = VCC, I/O VL_ = VL 16 25 µA IQVL I/O VCC_ = VCC, I/O VL_ = VL 6 10 µA TA = +25°C, EN = GND or VL > VCC + 0.7V, MAX13030E–MAX13034E 2 4 TA = +25°C, VL > VCC + 0.7V, MAX13035E, 2 4 TA = +25°C, EN = GND or VL > VCC + 0.7V, MAX13030E–MAX13034E 0.1 4 TA = +25°C, VL > VCC + 0.7V, MAX13035E 0.1 4 TA = +25°C, EN = GND or VL > VCC + 0.7V 0.1 2 µA 1 µA ISHDN-VCC ISHDN-VL ILEAK ILEAK_EN 2.2 µA TA = +25°C, MAX13030E–MAX13034E µA VL - VCC Shutdown Threshold High VTH_H VCC rising -0.2 0.05VL 0.7 V VL - VCC Shutdown Threshold Low VTH_L VCC falling -0.2 0.1VL 0.7 V I/O VCC_ Pulldown Resistance During Shutdown RVCC_PD_SD EN = GND, MAX13032E/MAX13034E 10 16.5 23 kΩ I/O VCC_ Pullup Resistance During Shutdown RVCC_PU_SD EN = GND, MAX13031E 10 16.5 23 kΩ 10 16.5 23 kΩ I/O VL_ Pulldown Resistance During Shutdown 2 RVL_PD_SD EN = GND, MAX13033E/MAX13034E _______________________________________________________________________________________ 6-Channel High-Speed Logic-Level Translators (VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = 1.8V and TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 75 105 kΩ I/O VL_, CLK_VL, CLK_RET Pullup Resistance During Shutdown RVL_PU_SD (VL > VCC + 0.7V), MAX13035E 45 I/O VL_, CLK_VL, CLK_RET Pullup Current RVL_PU EN = VCC or VL, I/O VL_ = GND 20 µA I/O VCC_, CLK_VCC Pullup Current RVCC_PU EN = VCC or VL, I/O VCC_ = GND 20 µA I/O VL to I/O VCC DC Resistance RIOVL_IOVCC (Note 3) 3 kΩ ESD PROTECTION (Note 3) I/O VCC_, CLK_VCC Human Body Model, CVCC = 1.0µF ±15 IEC 61000-4-2 Air-Gap Discharge, CVCC = 1.0µF ±12 IEC 61000-4-2 Contact Discharge, CVCC = 1.0µF ±8 kV LOGIC-LEVEL THRESHOLDS I/O VL_, CLK_VL Input-Voltage High Threshold VIHL (Note 4) I/O VL_, CLK_VL Input-Voltage Low Threshold VILL (Note 4) I/O VCC_, CLK_VCC InputVoltage High Threshold VIHC (Note 4) I/O VCC_, CLK_VCC InputVoltage Low Threshold VILC (Note 4) EN Input-Voltage High Threshold VIH MAX13030E–MAX13034E EN Input-Voltage Low VIL MAX13030E–MAX13034E I/O VL_, CLK_VL, CLK_RET Output-Voltage High VOHL I/O VL_, CLK_VL, CLK_RET source current = 20µA, I/O VCC_ ≥ VCC - 0.4V I/O VL_, CLK_VL, CLK_RET Output-Voltage Low VOLL I/O VL_, CLK_VL, CLK_RET sink current = 20µA, I/O VCC_ ≤ 0.2V I/O VCC_, CLK_VCC OutputVoltage High VOHC I/O VCC_, CLK_VCC source current = 20µA, I/O VL_ ≥ VL - 0.2V VL 0.2 0.15 V V VCC 0.4 0.2 V V VL 0.4 V 0.4 V 2/3 VL V 1/3 VL 2/3 VCC V V _______________________________________________________________________________________ 3 MAX13030E–MAX13035E ELECTRICAL CHARACTERISTICS (continued) MAX13030E–MAX13035E 6-Channel High-Speed Logic-Level Translators ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = 1.8V and TA = +25°C.) (Notes 1, 2) PARAMETER I/O VCC_, CLK_VCC OutputVoltage Low SYMBOL VOLC CONDITIONS MIN TYP I/O VCC_, CLK_VCC sink current = 20µA, I/O VL_ ≤ 0.15V MAX UNITS 1/3 VCC V RISE/FALL TIME ACCELERATOR STAGE (Note 3) Accelerator Pulse Duration VL-Output-Accelerator Source Impedance VCC-Output-Accelerator Source Impedance VL-Output-Accelerator Sink Impedance VCC-Output-Accelerator Sink Impedance On falling edge 3 On rising edge 3 VL = 1.62V 11 VL = 3.2V 6 VCC = 2.2V 9 VCC = 3.6V 8 VL = 1.62V 9 VL = 3.2V 8 VCC = 2.2V 10 VCC = 3.6V 9 ns Ω Ω Ω Ω TIMING CHARACTERISTICS (VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, CI/OVL ≤ 15pF, CI/OVCC ≤ 15pF, RSOURCE = 150Ω, EN = VL, I/O VL_ to I/O VCC_ rise/fall time = 3ns, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = 1.8V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I/O VCC_, CLK_VCC Rise Time tRVCC RS = 150Ω, CI/OVCC = 10pF, CCLK_VCC = 10pF, push-pull drivers (Figure 1) 2.5 ns I/O VCC_, CLK_VCC Fall Time tFVCC RS = 150Ω, CI/OVCC = 10pF, CCLK_VCC = 10pF (Figures 1, 2) 2.5 ns I/O VL_, CLK_VL Rise Time tRVL RS = 150Ω, CI/OVL = 15pF, CCLK_VL = 15pF, push-pull drivers (Figure 3) 2.5 ns I/O VL_, CLK_VL Fall Time tFVL RS = 150Ω, CI/OVL = 15pF, CCLK_VL = 15pF (Figures 3, 4) 2.5 ns Propagation Delay (Driving I/O VL_, CLK_VL) tPVL-VCC RS = 150Ω, CI/OVCC = 10pF, CCLK_VCC = 10pF, push-pull drivers (Figure 1) 6.5 ns Propagation Delay (Driving I/O VCC_, CLK_VCC) tPVCC-VL RS = 150Ω, CI/OVL = 15pF, CCLK_VL = 15pF, push-pull drivers (Figure 3) 6.5 ns tSKEW RS = 150Ω, CI/OVCC = 10pF, CI/OVL = 15pF 0.8 ns tEN-VCC RLOAD = 1MΩ, CI/OVCC = 10pF (Figure 5) (MAX13030E–MAX13034E) Channel-to-Channel Skew Propagation Delay from I/O VL_ to I/O VCC_ after EN 4 5 _______________________________________________________________________________________ µs 6-Channel High-Speed Logic-Level Translators (VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, CI/OVL ≤ 15pF, CI/OVCC ≤ 15pF, RSOURCE = 150Ω, EN = VL, I/O VL_ to I/O VCC_ rise/fall time = 3ns, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = 1.8V and TA = +25°C.) (Note 1) PARAMETER Propagation Delay from I/O VCC_ to I/O VL_ after EN Maximum Data Rate SYMBOL tEN-VL CONDITIONS MIN RLOAD = 1MΩ, CI/OVL = 15pF (Figure 5) (MAX13030E–MAX13034E) Push-pull operation, RSOURCE = 150_, CI/OVCC_ = 10pF, CI/OVL_ = 15pF, CCLK_VCC = 10pF, CCLK_VL = 15pF TYP 5 100 MAX UNITS µs Mbps Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 2: VL must be less than or equal to VCC - 0.2V during normal operation. However, VL can be greater than VCC during startup and shutdown conditions and the part will not latch-up or be damaged. Note 3: Guaranteed by design. Note 4: Input thresholds are referenced to the boost circuit. _______________________________________________________________________________________ 5 MAX13030E–MAX13035E TIMING CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = 3.3V, VL = 1.8V, CL = 15pF, RSOURCE = 150Ω, data rate = 100Mbps, push-pull driver, TA = +25°C, unless otherwise noted.) 810 800 790 780 7 6 5 4 3 2 760 1 25.0 2.4 2.6 2.8 3.0 3.2 3.4 DRIVING ONE I/O VL 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 0 2.2 1.6 3.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC SUPPLY VOLTAGE (V) VL SUPPLY VOLTAGE (V) VCC SUPPLY VOLTAGE (V) VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING I/O VCC_, VCC = 3.6V) SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O VCC_) SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O VL_) 18.0 17.5 17.0 16.5 12 10 8 6 16.0 4 15.5 2 15.0 ICC 16 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 ICC 14 12 10 8 6 4 IL 2 0 0 1.6 DRIVING ONE I/O VL 18 IL MAX13030E toc06 14 20 SUPPLY CURRENT (mA) 18.5 DRIVING ONE I/O VCC 16 SUPPLY CURRENT (mA) 19.0 MAX13030E toc05 DRIVING ONE I/O VCC 19.5 18 MAX13030E toc04 20.0 -40 -15 10 35 60 -40 85 -15 10 35 60 VL SUPPLY VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C) VL SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_) VCC SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_) RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_) 4.0 3.5 3.0 2.5 2.0 DRIVING ONE I/O VL 19.5 19.0 18.5 18.0 17.5 17.0 10 15 20 25 30 CAPACITIVE LOAD (pF) 35 40 1300 1200 tRVCC 1100 1000 tFVCC 900 800 600 16.0 1.0 1400 700 16.5 1.5 1500 85 MAX13030E toc09 4.5 20.0 RISE/FALL TIME (ps) DRIVING ONE I/O VCC VCC SUPPLY CURRENT (mA) MAX13030E toc07 5.0 MAX13030E toc08 VCC SUPPLY CURRENT (mA) 8 770 750 6 DRIVING ONE I/O VCC 9 VCC SUPPLY CURRENT (mA) 820 MAX13030E toc02 830 10 VL SUPPLY CURRENT (mA) DRIVING ONE I/O VL 840 VL SUPPLY CURRENT (μA) MAX13030E toc01 850 VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING I/O VL_, VL = 1.8V) VL SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING I/O VCC_, VCC = 3.6V) MAX13030E toc03 VL SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING I/O VL_, VL = 1.8V) VL SUPPLY CURRENT (mA) MAX13030E–MAX13035E 6-Channel High-Speed Logic-Level Translators 500 10 15 20 25 30 CAPACITIVE LOAD (pF) 35 40 10 15 20 25 30 CAPACITIVE LOAD (pF) _______________________________________________________________________________________ 35 40 6-Channel High-Speed Logic-Level Translators RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_) PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_) 4.5 2250 2000 1750 tRVL 1500 1250 tFVL 1000 MAX13030E toc11 2500 PROPAGATION DELAY (ns) 2750 RISE/FALL TIME (ps) 5.0 MAX13030E toc10 3000 tPLH 4.0 3.5 tPHL 3.0 2.5 750 2.0 500 10 15 20 25 30 35 40 15 20 25 30 35 40 CAPACITIVE LOAD (pF) PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_) TYPICAL I/O VL_ DRIVING (FREQUENCY = 26MHz, CIOVCC = 40pF) MAX13030E toc13 MAX13030E toc12 5.0 4.5 PROPAGATION DELAY (ns) 10 CAPACITIVE LOAD (pF) 4.0 I/O VL_ 1V/div tPHL 3.5 3.0 tPLH 2.5 I/O VCC_ 2V/div 2.0 1.5 1.0 10 15 20 25 30 35 40 10ns/div CAPACITIVE LOAD (pF) TYPICAL I/O VCC_ DRIVING (FREQUENCY = 26MHz, CIOVL = 15pF) TYPICAL CLK_ VL DRIVING (FREQUENCY = 26MHz, CCLK_VCC = 40pF) MAX13030E toc14 MAX13030E toc15 CLK_ VL 1V/div I/O VCC_ 2V/div CLK_ VCC 2V/div I/O VL_ 1V/div 10ns/div CLK_RET 1V/div 10ns/div _______________________________________________________________________________________ 7 MAX13030E–MAX13035E Typical Operating Characteristics (continued) (VCC = 3.3V, VL = 1.8V, CL = 15pF, RSOURCE = 150Ω, data rate = 100Mbps, push-pull driver, TA = +25°C, unless otherwise noted.) MAX13030E–MAX13035E 6-Channel High-Speed Logic-Level Translators Pin Description PIN MAX13030E–MAX13034E 8 MAX13035E NAME FUNCTION UCSP TQFN UCSP TQFN A1 4 A1 4 I/O VL3 A2 6 A2 6 I/O VCC3 Input/Output 3. Referenced to VCC. A3 7 A3 7 I/O VCC4 Input/Output 4. Referenced to VCC. A4 9 A4 9 I/O VL4 B1 3 B1 3 I/O VL2 B2 5 B2 5 I/O VCC2 Input/Output 2. Referenced to VCC. B3 8 B3 8 I/O VCC5 Input/Output 5. Referenced to VCC. B4 10 B4 10 I/O VL5 C1 2 C1 2 VL Logic-Supply Voltage, +1.62V to +3.2V. Bypass VL to GND with a 0.1µF capacitor placed as close as possible to the device. Input/Output 3. Referenced to VL. Input/Output 4. Referenced to VL. Input/Output 2. Referenced to VL. Input/Output 5. Referenced to VL. C2 16 C2 16 VCC Power-Supply Voltage, +2.2V to +3.6V. Bypass VCC to GND with a 0.1µF ceramic capacitor. For full ESD protection, connect a 1µF ceramic capacitor from VCC to GND as close as possible to the VCC input. C3 13 C3 13 GND Ground C4 11 — — EN Enable Input. Drive EN to GND for shutdown mode, or drive EN to VL or VCC for normal operation. D1 1 D1 1 I/O VL1 D2 15 D2 15 I/O VCC1 Input/Output 1. Referenced to VCC. Input/Output 1. Referenced to VL. D3 14 — — I/O VCC6 Input/Output 6. Referenced to VCC. D4 12 — — I/O VL6 — — C4 11 CLK_RET Clock Return Output. CLK_RET is the returned signal of a clock applied to CLK_VL. CLK_RET is referenced to VL. — — D3 14 CLK_VCC Translator Channel for a Clock Applied to VCC — — D4 12 CLK_VL — EP — EP EP Input/Output 6. Referenced to VL. Translator Channel for a Clock Applied to VL Exposed Paddle. Connect exposed paddle to GND. _______________________________________________________________________________________ 6-Channel High-Speed Logic-Level Translators VL tRVCC VCC VL 90% VCC EN** MAX13030E– MAX13035E VL tFVCC 90% I/O VL 50% VCC 50% 50% 50% I/O VL_ (CLK_VL*) I/O VCC_ (CLK_VCC*) I/O VCC 150Ω 10% 10% CIOVCC (CCLK_VCC*) *MAX13035E ONLY **MAX13030E–MAX13034E ONLY tPLH tPHL tPVL-VCC = tPLH OR tPHL Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing VL tRVCC VCC tFVCC I/O VCC VL EN** 90% VCC MAX13030E– MAX13035E VL VGATE 50% VCC 50% 50% 50% I/O VL_ (CLK_VL*) 90% I/O VCC_ (CLK_VCC*) 10% 10% CIOVCC (CCLK_VCC*) VGATE tPLH tPHL tPVL-VCC = tPHL *MAX13035E ONLY **MAX13030E–MAX13034E ONLY Figure 2. Open-Drain Driving I/O VL_ Test Circuit and Timing _______________________________________________________________________________________ 9 MAX13030E–MAX13035E Test Circuits/Timing Diagrams MAX13030E–MAX13035E 6-Channel High-Speed Logic-Level Translators Test Circuits/Timing Diagrams (continued) VL VL EN** tFVL tRVL VCC I/O VCC VCC MAX13030E– MAX13035E VL VCC 90% 50% I/O VCC_ (CLK_VCC*) I/O VL_ (CLK_VL*) 50% 150Ω 90% 50% 50% 10% 10% I/O VL CIOVL (CCLK_VL*) tPHL tPLH *MAX13035E ONLY tPVCC-VL = tPLH OR tPHL **MAX13030E–MAX13034E ONLY Figure 3. Push-Pull Driving I/O VCC_ Test Circuit and Timing VL VL (CCLK_VL*) tRVL VCC EN** VCC I/O VL MAX13030E– MAX13035E VL tFVL 90% 50% VCC 90% 50% 50% I/O VCC_ (CLK_VCC*) I/O VL_ (CLK_VL*) CIOVL 10% VGATE (CCLK_VL*) 50% tPLH 10% tPHL tPVCC-VL = tPHL *MAX13035E ONLY **MAX13030E–MAX13034E ONLY Figure 4. Open-Drain Driving I/O VCC_ Test Circuit and Timing 10 ______________________________________________________________________________________ 6-Channel High-Speed Logic-Level Translators VL EN VL MAX13030E– EN VCC MAX13034E t'EN-VCC 0 I/O VCC_ SOURCE I/O VL_ VL I/O VL_ 0 RLOAD VCC CIOVCC I/O VCC_ VL VCC / 2 0 VCC VL EN VL MAX13030E– VCC RLOAD EN t"EN-VCC 0 MAX13034E SOURCE I/O VL_ VL I/O VL_ 0 I/O VCC_ VCC I/O VCC_ VCC / 2 CIOVCC 0 tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC. VL EN VL EN MAX13030E– VCC MAX13034E t'EN-VL SOURCE VCC I/O VCC_ I/O VCC_ I/O VL_ RLOAD CIOVL 0 0 VCC VL I/O VL_ VL / 2 0 VL EN EN VL SOURCE VL MAX13030E– VCC MAX13034E t"EN-VL VCC I/O VCC_ 0 RLOAD I/O VCC_ I/O VL_ VL I/O VL_ VL / 2 CIOVL 0 0 tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC. Figure 5. Enable Test Circuit and Timing ______________________________________________________________________________________ 11 MAX13030E–MAX13035E Test Circuits/Timing Diagrams (continued) MAX13030E–MAX13035E 6-Channel High-Speed Logic-Level Translators Detailed Description The MAX13030E–MAX13035E 6-channel, bidirectional level translators provide the level shifting necessary for 100Mbps data transfer in multivoltage systems. The MAX13030E–MAX13035E are ideally suited for memory card level translation, as well as generic level translation in systems with six channels. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a higher voltage logic signal on the VCC side of the device, and vice versa. The MAX13035E features a CLK_RET output that returns the same clock signal applied to the CLK_VL input. The MAX13030E–MAX13035E operate at full speed with external drivers that source as little as 4mA output current. Each I/O channel is pulled up to VCC or VL by an internal 30µA current source, allowing the MAX13030E–MAX13035E to be driven by either pushpull or open-drain drivers. The MAX13030E–MAX13034E feature an enable (EN) input that places the device into a low-power shutdown mode when driven low. The MAX13030E–MAX13035E features an automatic shutdown mode that disables the part when VCC is less than VL. The state of I/O VCC_ and I/O VL_ during shutdown is chosen by selecting the appropriate part version (see Ordering Information/ Selector Guide). The MAX13030E–MAX13035E accept VCC voltages from +2.2V to +3.6V and VL voltages from +1.62V to +3.2V. Level Translation For proper operation, ensure that +2.2V ≤ VCC ≤ +3.6V, and +1.62V ≤ VL ≤ VCC - 0.2V. When power is supplied to V L while V CC is either missing or less than V L , the MAX13030E–MAX13035E automatically enters a low- power mode. In addition, the MAX13030E– MAX13034E enters a low-power mode if EN = 0V. This allows VCC to be disconnected and still have a known state on I/O VL_. The maximum data rate depends heavily on the load capacitance (see the Typical Operating Characteristics Rise/Fall Times), output impedance of the driver, and the operating voltage range. Input Driver Requirements The MAX13030E–MAX13035E architecture is based on an nMOS pass gate and output accelerator stages (see Figure 6). Output accelerator stages are always in tristate mode except when there is a transition on any of the translators on the input side, either I/O VL_, CLK_VL, I/O VCC_, or CLK_VCC. A short pulse is then generated during which the output accelerator stages become active and charge/discharge the capacitances at the I/Os. Due to its architecture, both input stages become 12 VCC VL ENABLE ENABLE ENABLE 30μA 30μA I/O VL_ I/O VCC_ VCC VL BOOST CIRCUIT VL VCC BOOST CIRCUIT NOTES: 1) THE MAX13030E–MAX13034E ARE ENABLED WHEN VL < VCC - 0.2V AND EN = VL. 2) THE MAX13035E IS ENABLED WHEN VL < VCC - 0.2V. Figure 6. Simplified Functional Diagram for One I/O Line active during the one-shot pulse. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps to speed up the transition on the driven side. The MAX13030E–MAX13035E have internal current sources capable of sourcing 30µA to pullup the I/O lines. These internal pullup current sources allow the inputs to be driven with open-drain drivers, as well as push-pull drivers. It is not recommended to use external pullup resistors on the I/O lines. The architecture of the MAX13030E–MAX13035E permit either side to be driven with a minimum of 4mA drivers or larger. Output Load Requirements The MAX13030E–MAX13035E I/O are designed to drive CMOS inputs. Do not load the I/O lines with a resistive load less than 25kΩ and do not place an RC circuit at the input of these devices to slow down the edges. If a slower rise/fall time is required, refer to the MAX3000E/ MAX3001E logic-level translator datasheet. For I 2C level translation, refer to the MAX3372E–MAX3379E/ MAX3390E–MAX3393E datasheet. Shutdown Mode The MAX13030E–MAX13034E feature an enable (EN) input that places the device into a low-power shutdown mode when driven low. The MAX13030E–MAX13035E features an automatic shutdown mode that disables the part when VCC is missing or less than VL. ______________________________________________________________________________________ 6-Channel High-Speed Logic-Level Translators Open-Drain Signaling The MAX13030E–MAX13035E are designed to pass open-drain as well as CMOS push-pull signals. When used with open-drain signaling, the rise time is dominated by the interaction of the internal pullup current source and the parasitic load capacitance. The MAX13030E–MAX13035E include internal rise time accelerators to speed up transitions, eliminating any need for external pullup resistors. Application Information Layout Recommendations Use standard high-speed layout practices when laying out a board with the MAX13030E–MAX13035E. For example, to minimize line coupling, place all other signal lines not connected to the MAX13030E–MAX13035E at least 1x the substrate height of the PCB away from the input and output lines of the MAX13030E–MAX13035E. Power-Supply Decoupling To reduce ripple and the chance of introducing data errors, bypass VL and VCC to ground with 0.1µF ceramic capacitors. Place all capacitors as close as possible to the power-supply inputs. For full ESD protection, bypass VCC with a 1µF ceramic capacitor located as close as possible to the VCC input. Unidirectional vs. Bidirectional Level Translator The MAX13030E–MAX13035E bidirectional level translators can operate as a unidirectional device to translate signals without inversion. These devices provide the smallest solution (UCSP package) for unidirectional level translation without inversion. SD Card Detection SD, MiniSD, MMC and similar types of cards provide detection of a card through a pullup resistor on one of the DAT lines, or by use of a mechanical switch. This pullup resistor is internal to the memory card itself. The MAX13030E–MAX13035E only support detection of a memory card through a mechanical switch, and it is recommended that the internal resistor for card detection be switched off by the command interface. For example, when using SD cards, the command SET_CLR_CARD_DETECT (ACMD42) disables this resistor. UCSP Applications Information For the latest application details on UCSP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profiles, as well as the latest information on reliability testing results, go to Maxim’s web site at www.maxim-ic.com/ucsp to find the Application Note: UCSP – A Wafer-Level Chip-Scale Package. Use with External Pullup/Pulldown Resistors Due to the architecture of the MAX13030E– MAX13035E, it is not recommended to use external pullup or pulldown resistors on the bus. In certain applications, the use of external pullup or pulldown resistors is desired to have a known bus state when there is no active driver on the bus. For example, this may happen when interfacing to a memory card slot with no memory card inserted. The MAX13030E–MAX13035E include internal pullup current sources that set the bus state when the device is enabled. In shutdown mode, the state of I/O V CC_ and I/O V L_ is dependent on the selected part version (see Ordering Information/ Selector Guide for further information). Chip Information Process: BiCMOS ______________________________________________________________________________________ 13 MAX13030E–MAX13035E Clock Return (CLK_RET) The MAX13035E features a CLK_RET output that returns the clock signal applied to CLK_V L . CLK_V L and CLK_VCC are identical to the other I/O channels, the only difference being that CLK_VCC is internally tied to the VCC side of CLK_RET (see the Functional Diagram). 6-Channel High-Speed Logic-Level Translators MAX13030E–MAX13035E Functional Diagram VL VL VCC VCC MAX13035E MAX13030E– MAX13034E I/O VL1 I/O VCC1 I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 I/O VL2 I/O VCC2 I/O VL3 I/O VCC3 I/O VL3 I/O VCC3 I/O VL4 I/O VCC4 I/O VL4 I/O VCC4 I/O VL5 I/O VCC5 I/O VL5 I/O VCC5 I/O VL6 I/O VCC6 CLK_ VL CLK_ VCC EN GND CLK_RET GND 14 ______________________________________________________________________________________ 6-Channel High-Speed Logic-Level Translators I/O VL6 EN I/O VL5 I/O VL4 TOP VIEW 12 11 10 9 TOP VIEW (BUMPS ON BOTTOM) 1 + GND 13 8 I/O VCC5 I/O VCC6 14 7 I/O VCC4 6 I/O VCC3 5 I/O VCC2 MAX13030E– MAX13034E I/O VCC1 15 VCC *EP 16 2 3 4 MAX13030E–MAX13034E A I/O VL3 I/O VCC3 I/O VCC4 I/O VL4 I/O VL2 I/O VCC2 I/O VCC5 I/O VL5 VL VCC GND EN I/O VL1 I/O VCC1 I/O VCC6 I/O VL6 B 1 2 3 4 I/O VL1 VL I/O VL2 I/O VL3 C + D 16 TQFN (4mm x 4mm) *CONNECT EXPOSED PADDLE TO GROUND 16 UCSP (2mm x 2mm) CLK_VL CLK_RET I/O VL5 I/O VL4 TOP VIEW 12 11 10 9 TOP VIEW (BUMPS ON BOTTOM) 1 + GND 13 8 I/O VCC5 CLK_VCC 14 7 I/O VCC4 6 I/O VCC3 5 I/O VCC2 MAX13035E I/O VCC1 15 VCC *EP 16 2 3 4 MAX13035E A I/O VL3 I/O VCC3 I/O VCC4 I/O VL4 I/O VL2 I/O VCC2 I/O VCC5 I/O VL5 VL VCC GND CLK_RET I/O VL1 I/O VCC1 CLK_VCC CLK_VL B 1 2 3 4 I/O VL1 VL I/O VL2 I/O VL3 C + 16 TQFN (4mm x 4mm) D *CONNECT EXPOSED PADDLE TO GROUND 16 UCSP (2mm x 2mm) ______________________________________________________________________________________ 15 MAX13030E–MAX13035E Pin Configurations 6-Channel High-Speed Logic-Level Translators MAX13030E–MAX13035E Typical Operating Circuits (continued) +3.3V +1.8V 0.1μF VL +1.8V SYSTEM CONTROLLER 1μF 0.1μF VCC +3.3V SYSTEM MAX13030E– MAX13034E EN I/O VL_ EN DATA I/O VCC_ 6 DATA 6 GND GND GND Ordering Information/Selector Guide (continued) PIN-PACKAGE I/O VL_ STATE DURING SHUTDOWN MAX13031EEBE+* 16 UCSP High impedance 16.5kΩ to VCC B16-1 MAX13031EETE+* 16 TQFN-EP** High impedance 16.5kΩ to VCC T1644-4 MAX13032EEBE+ 16 UCSP High impedance 16.5kΩ to GND B16-1 MAX13032EETE+ 16 TQFN-EP** High impedance 16.5kΩ to GND T1644-4 MAX13033EEBE+* 16 UCSP 16.5kΩ to GND High impedance B16-1 MAX13033EETE+* 16 TQFN-EP** 16.5kΩ to GND High impedance T1644-4 MAX13034EEBE+* 16 UCSP 16.5kΩ to GND 16.5kΩ to GND B16-1 MAX13034EETE+* 16 TQFN-EP** 16.5kΩ to GND 16.5kΩ to GND T1644-4 MAX13035EEBE+ 16 UCSP 75kΩ to VL High impedance B16-1 MAX13035EETE+ 16 TQFN-EP** 75kΩ to VL High impedance T1644-4 PART I/O VCC_ STATE DURING SHUTDOWN Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead-free package. **EP = Exposed paddle. 16 ______________________________________________________________________________________ PKG CODE 6-Channel High-Speed Logic-Level Translators 16L,UCSP.EPS PACKAGE OUTLINE, 4x4 UCSP 21-0101 H 1 1 ______________________________________________________________________________________ 17 MAX13030E–MAX13035E Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX13030E–MAX13035E 6-Channel High-Speed Logic-Level Translators PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 1 2 PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products Boblet is a registered trademark of Maxim Integrated Products, Inc.