19-2405; Rev 0; 4/02 10Gbps 16:1 Serializer Features The MAX3952 16:1 serializer is optimized for 10.3Gbps and 9.95Gbps Ethernet applications. A serial clock output is provided for retiming the data at the latch input of the laser driver. Both the high-speed data and clock are CML outputs. The serializer operates from a single +3.3V supply, consuming only 1.15W typical power. ♦ Operates at 9.953Gbps and 10.3125Gbps The clock multiplier reference clock frequency can be either 1/16 or 1/64 the serial output clock rate. A FIFO aligns the phase between the parallel clock input and the internally synthesized clock. In addition, a 1/16 counterdirectional clock output (LVDS) is provided for use as the clock signal of the XAUI codec IC or framer. The operating temperature range is from -40°C to +85°C. The MAX3952 is available in a 10mm ✕ 10mm 68-pin QFN package. ♦ LVDS Source Clock Output ♦ 16-Bit LVDS Interface ♦ Single +3.3V Supply ♦ 1.15W Power Dissipation ♦ Built-In 27 - 1 PRBS Pattern Generator ♦ Deterministic Jitter: 9ps (max) at 0°C to +85°C ♦ Operating Temperature Range: -40°C to +85°C ♦ 68-Pin QFN Package (10mm ✕ 10mm) Applications Ordering Information 10Gbps Ethernet LAN PART 10Gbps Ethernet WAN MAX3952EGK TEMP RANGE PIN-PACKAGE -40°C to +85°C 68 QFN Pin Configuration appears at end of data sheet. Typical Application Circuit 3.3V 644.53MHz REFCLK INPUT MAC 0.1µF 100Ω 5V PDIO+ REFCLK+ REFCLK- CKSET VCC VCC_VCO PDIO- FIL SDO+ PDI15+ SDO- PDI15- MAX3930 MAX3952 PCLKI+ PCLKIPCLKO+ PCLKOFIFOERR SCLKO+ SCLKORESET PRBSEN LOCK GND SCLKEN TTL THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50Ω). ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3952 General Description MAX3952 10Gbps 16:1 Serializer ABSOLUTE MAXIMUM RATINGS Power Supply (VCC)....................................................-0.5 to +5V CML Output Current (SDO±, SCLKO±)..............................22mA LVDS Input Voltage Levels (PDI_±, PCLKI±).....................................-0.5V to (VCC + 0.5V) LVDS Output Voltage (PCLKO±)................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) QFN (derate 30.3mW/°C above 70°C) .......................2424mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Voltage Levels at FIL, RESET, CKSET........-0.5V to (VCC + 0.5V) Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, differential LVDS load = 100Ω, TA = +25°C, unless otherwise noted.) PARAMETER Supply Current SYMBOL ICC CONDITIONS MIN (Note 1) TYP MAX UNITS 350 500 mA 2400 mV LVDS INPUT SPECIFICATIONS (PDI±[15…0], PCLKI±) Input Voltage Range Differential Input Voltage VI 0 |VID| 100 Input Common-Mode Current Input, VOS = 1.2V Threshold Hysteresis Differential Input Impedance mV 100 µA 70 RIN 85 100 mV 115 Ω LVDS OUTPUT SPECIFICATIONS (PCLKO±) Output High Voltage VOH Output Low Voltage VOL 0.925 1.475 Differential Output Voltage |VOD| 250 Change in Magnitude of Differential Outputs for Complementary Inputs ∆|VOD| Offset Output Voltage Change in Magnitude of Output Offset Voltage for Complementary States 1.125 ∆|VOS| Differential Output Impedance Output Current 2 80 400 mV 25 mV 1.275 V 25 mV 140 Ω Short together 12 Short to ground 40 _______________________________________________________________________________________ V V mA 10Gbps 16:1 Serializer (VCC = +3V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, differential LVDS load = 100Ω, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 640 800 1000 mVP-P 100 115 Ω CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±) Differential Output RL = 50Ω to VCC Differential Output Impedance 85 Output Common-Mode Voltage VCC 0.2 RL = 50Ω to VCC V LVTTL SPECIFICATIONS (RESET, FIFO_ERROR, LOCK, PRBSEN) LVTTL Input High Voltage VIH LVTTL Input Low Voltage VIL LVTTL Input High Current IIH LVTTL Input Low Current 2.0 V 0.8 V 10 µA -50 10 µA 2.4 VCC V 0.4 V -28 IIL LVTTL Output High Voltage VOH IOH = 20µA LVTTL Output Low Voltage VOL IOL = 1mA LVPECL INPUT SPECIFICATIONS (REFCLK±) LVPECL Input High Voltage VIH VCC 1.16 VCC 0.88 V LVPECL Input Low Voltage VIL VCC 1.81 VCC 1.48 V LVPECL Input Bias Voltage LVPECL Single-Ended Impedance LVPECL Differential Input Voltage Swing 300 VCC 1.3 V 1.4 kΩ 1900 mVP-P Note 1: CML outputs AC-coupled to 100Ω differential load, PRBSEN = GND, and SCLKEN = GND. _______________________________________________________________________________________ 3 MAX3952 DC ELECTRICAL CHARACTERISTICS (continued) MAX3952 10Gbps 16:1 Serializer AC ELECTRICAL CHARACTERISTICS (VCC = +3V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, differential LVDS and CML load = 100Ω, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Tx DATA INPUT SPECIFICATIONS (PDI±[15…0], PCLKI±) Parallel Input Setup Time tSU (Figure 1) 200 ps Parallel Input Hold Time tH (Figure 1) 200 ps 250 ps 55 % 28 ps +15 ps 0.9 psRMS Tx SOURCE CLOCK OUTPUT SPECIFICATIONS (PCLKO±) Parallel Clock Output Rise/Fall Time tr, tf 20% to 80% Parallel Clock Output Duty Cycle 100 45 SERIAL DATA OUTPUT SPECIFICATIONS (SDO±, SCLKO±) -12 1 ✕ 10 Bit-Error Rate Serial Data Output Rise/Fall Time tr, tf Serial Output Clock-to-Data Delay tCK-Q Serial Data or Clock Output Random Jitter tRJ Serial Data Output Deterministic Jitter tDJ Serial Clock or Data Output Return Loss 20% to 80% (Note 3) -15 0°C to +85°C (Note 4) 9 -40°C to +85°C (Note 4) 15 100kHz to 10GHz RL = 10GHz to 13GHz -20log|S22| 13GHz to 15GHz psP-P 17 dB 10 7 Tx REFERENCE CLOCK INPUT SPECIFICATIONS (REFCLK±) Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle -100 +100 ppm 30 70 % RESET INPUT (RESET) Minimum Pulse Width of FIFO Reset UI is PCLKO period Tolerated Drift Between PCLKI and PCLKO After Reset UI is PCLKO period; drift is PCLKO crossing PCLKI crossing 4 -1 UI +1 UI Note 2: See Table 1 for valid operating clock frequencies. AC characteristics are guaranteed by design and characterization. Note 3: Relative to the falling edge of the SCLKO. Note 4: Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured with a pattern equivalent to 223 - 1 PRBS. 4 _______________________________________________________________________________________ 10Gbps 16:1 Serializer SERIAL CLOCK OUTPUT RANDOM JITTER MAX3952 toc01 0 JITTER TRANSFER (dB) MAX3952 toc02 RCLKI TO SCLKO JITTER TRANSFER 5 -5 -10 -15 -20 -25 10 100 1k 10k fREFCLK = 155.52MHz, RANDOM JITTER = 513fsRMS JITTER FREQUENCY (Hz) SUPPLY CURRENT vs. TEMPERATURE SERIAL CLOCK AND DATA OUTPUTS 430 SUPPLY CURRENT (mA) SCLKO MAX3952 toc04 MAX3952 toc03 450 410 390 370 350 330 SDO 310 290 20ps/div -40 10 60 110 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX3952 Typical Operating Characteristics (TA = +25°C, VCC = +3.3V, unless otherwise noted.) 10Gbps 16:1 Serializer MAX3952 Pin Description 6 PIN NAME FUNCTION 1, 4, 5, 13, 17, 18, 26, 34, 35, 51, 52, 68 GND 2 REFCLK+ Positive Reference Clock Input, LVPECL 3 REFCLK- Negative Reference Clock Input, LVPECL 6, 9, 12, 25, 43, 60 VCC Ground Positive Power Supply 7 SCLKO- 8 SCLKO+ Negative Serial Clock Output, CML. 9.95328GHz or 10.3125GHz 10 SDO- Negative Serial Data Output, CML. 9.95328Gbps or 10.3125Gbps 11 SDO+ Positive Serial Data Output, CML. 9.95328Gbps or 10.3125Gbps 14 SCLKEN 15 PCLKO+ Positive Source Clock Output. LVDS, 622MHz or 644MHz. Clocks the MAC. 16 PCLKO- Negative Source Clock Output. LVDS, 622MHz or 644MHz. Clocks the MAC. 19, 21, 23, 27, 29, 31, 36, 38, 40, 44, 46, 48, 54, 56, 58, 61 PDI15+ to PDI0+ Positive Parallel Data Inputs, LVDS. PDI15+ is MSB 20, 22, 24, 28, 30, 32, 37, 39, 41, 45, 47, 49, 55, 57, 59, 62 PDI15- to PDI0- Negative Parallel Data Inputs, LVDS. PDI15- is MSB Positive Serial Clock Output, CML. 9.95328GHz or 10.3125GHz Control Input for Disabling SCLKO Output: SCLKEN = GND ⇒ SCLKO Off SCLKEN = VCC ⇒ SCLKO Active 33 RESET 42 PRBSEN 16 x 4-Bit FIFO Reset Input, TTL, Active High 50 FIFO_ERROR 53 LOCK 63 PCLKI+ Positive Parallel Clock Input, LVDS 64 PCLKI- Negative Parallel Clock Input, LVDS 65 CKSET 66 FIL 67 VCC_VCO PRBS Pattern Generator Enable Input, TTL, Active High FIFO Error, TTL, Active High PLL Lock Indicator, TTL, Active High Reference Clock Programming Pin. Programming instructions in Table 1. Filter Capacitor Input Pin Loop Filter and VCO Positive Power Supply _______________________________________________________________________________________ 10Gbps 16:1 Serializer The MAX3952 converts 16-bit-wide, 622Mbps/644Mbps data to 9.95Gbps/10.3Gbps serial data (Figures 3 and 4). Data is loaded into the 16:1 mux through a 16 x 4 FIFO buffer for wide tolerance to clock skew. Clock and data inputs are LVDS levels, and high-speed serial outputs are current-mode logic (CML). An internal PLL frequency synthesizer generates a serial clock from a low-speed reference clock. Low-Voltage Differential-Signal Inputs and Outputs The MAX3952 has LVDS inputs for interfacing with high-speed digital circuitry. This technology uses 250mV to 400mV differential low-voltage swings to achieve fast transition times, minimal power dissipation, and noise immunity. For proper operation, the parallel clock LVDS outputs (PCLKO±) require 100Ω differential DC terminations between the positive and negative outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PDI_+, PDI_-, PCLKI+, PCLKI-) are internally terminated with a 100Ω differential input resistance and therefore do not require external termination. LVPECL Inputs The reference clock (REFCLK±) has LVPECL inputs for interfacing to a crystal oscillator using AC- or DC-coupling. The REFCLK± inputs are self-biasing to VCC - 1.3V for AC-coupled inputs. Only a 100Ω differential termination resistance must be added when inputs are AC-coupled. Current-Mode Logic Outputs The high-speed data and clock outputs (SDO±, SCLKO±) of the MAX3952 are designed using CML. The CML outputs include internal 50Ω back termination to V CC. These outputs are intended to drive a 50Ω transmission line terminated with a matched load impedance. For detailed instructions on how to interface with LVDS, PECL, and CML, refer to HFAN-01.0: Introduction to LVDS, PECL, and CML. FIFO Buffer Data is latched into the MAX3952 by the parallel input clock (PCLKI±). The parallel input clock is the FIFO write clock. The parallel output clock (PCLKO±) is the FIFO read clock that loads the 16:1 mux. The FIFO allows the read and write clock to vary by up to ±1UI (unit interval). This specification makes the MAX3952 noncompliant with the IEEE802.3ae standard, as this standard requires a tolerance of ±14UI. Conditions that result in the read and write clock accessing the same FIFO address are indicated by FIFO_ERROR. To clear this condition, assert RESET high for at least 4UI. FIFO_ERROR can be connected directly to the RESET input to clear timing errors. After reset, the full elastic range of the FIFO is available again. Frequency Synthesizer The PLL synthesizes a 9.95GHz/10.31GHz clock from an external reference clock. The PLL reference clock (REFCLK±) can be programmed as 622MHz/644MHz or 155MHz/161MHz using the CKSET pin. See Table 1 for CKSET settings. The parallel output clock (PCLKO±) is derived from the synthesizer and is SCLKO ÷ 16. A TTL-compatible loss-of-lock indicator (LOCK), asserts low when the VCO is unable to lock to the reference frequency. This pin can be used to directly drive an LED. If jitter on the REFCLK± input is present, an error with respect to the divided down SCLKO frequency of 500ppm will be indicated by a low state on LOCK. Table 1. Setting REFCLK Frequency REFERENCE CLOCK FREQUENCY (MHz) CKSET PIN SETTING SERIAL CLOCK FREQUENCY (GHz) 622.08 OPEN 9.95 644.53 VCC 10.3 155.52 GND 9.95 161.13 30kΩ to GND 10.3 Internal Pattern Generator The MAX3952 includes a SONET-compliant internal pattern generator capable of a 2 7 - 1 PRBS pattern. Connecting the PRBSEN pin to VCC enables the pattern generator. Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3952 clock and data inputs and outputs. Give special consideration to filtering the VCC_VCO pin; all other power supplies can be connected through a common filter. Exposed Pad (EP) Package The EP 68-pin QFN incorporates features that provide a very low thermal resistance path for heat removal from the IC to a PC board. The MAX3952’s exposed paddle must be soldered directly to a ground plane with good thermal conductance. Refer to HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages. _______________________________________________________________________________________ 7 MAX3952 Detailed Description MAX3952 10Gbps 16:1 Serializer Chip Information TRANSISTOR COUNT:8400 PROCESS: SiGe bipolar 100.47ps 1.608ns 622MHz CLOCK (PCLKI) 9.953GHz CLOCK (SCLKO) 622Mbps DATA (PDI) 9.953Gbps DATA (SDO) tSU tH tCLK-Q Figure 1. Setup and Hold Time Figure 2. Definition of Clock to Q RESET FIFO-ERROR PCLKI+ LVDS WRITE CLK PCLKISDO+ 16 16-BIT REG PDI+[15...0] LVDS 16 16 16 16:1 MUX CML SDO- 0 16 PDI-[15...0] 16 x 4-BIT FIFO DATA READ 1 PRBS GENERATOR PRBSEN SIS MAX3952 PCLKO+ SCLKO+ LVDS CML PCLKO- SCLKO- REFCLK+ LVPECL FREQUENCY GENERATOR REFCLK- CKSET FIL VCC_VCO LOCK SCLKEN Figure 3. Functional Diagram 8 _______________________________________________________________________________________ 10Gbps 16:1 Serializer MAX3952 PCLKO PCLKI tH tSU PARALLEL INPUT DATA (PDI_) VALID PARALLEL DATA* *D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SERIAL OUTPUT DATA (SDO) NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PDI15 = D15; PDI14 = D14 ... PDIO = DO. THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL INPUT DATA AND SERIAL OUTPUT DATA. Figure 4. Parallel and Serial Data Timing Pin Configuration GND LOCK PDI3+ PDI3- PDI2- PDI2+ PDI1+ PDI1- VCC PDIO+ PDIO- PCLKI+ PCLKI- 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 CKSET VCC_VCO 68 FIL GND TOP VIEW GND 1 51 GND REFCLK+ 2 50 FIFO_ERROR REFCLK- 3 49 PDI4- GND 4 48 PDI4+ GND 5 47 PDI5- VCC 6 46 PDI5+ SCLKO- 7 45 PDI6- SCLKO+ 8 44 PDI6+ VCC 9 43 VCC SDO- 10 42 PRBSEN SDO+ 11 41 PDI7- MAX3951 40 PDI7+ 13 39 PDI8- SCLKEN 14 38 PDI8+ PCLKO+ 15 37 PDI9- PCLKO- 16 36 PDI9+ GND 17 35 GND *EXPOSED PAD IS CONNECTED TO GND. GND RESET PDI10- PDI10+ PDI11- PDI11+ PDI12- PDI12+ GND VCC PDI13- PDI13+ PDI14- PDI14+ 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PDI15- 18 GND 12 PDI15+ VCC GND QFN* _______________________________________________________________________________________ 9 MAX3952 10Gbps 16:1 Serializer Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.