WEDC WV3HG264M72EER403PD4MG

White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED*
512MB – 64Mx72 DDR2 SDRAM REGISTERED, SO-DIMM, w/PLL
FEATURES
DESCRIPTION
Registered 200-pin (SO-DIMM), Small-Outline dual
in-line memory module
Support ECC detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
The WV3HG64M72EER is a 64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of nine 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Multiple internal device banks for concurrent
operation
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Differential clock inputs (CK, CK#)
Programmable CAS# latency (CL): 3, 4, 5*, and 6*
Posted CAS# additive latency: 0, 1, 2, 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
7.8µs average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Utilizes 512Mb DDR2 SDRAM components
Auto & Self Refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
Single Rank
RoHS compliant
JEDEC proposed Pin-out
Package
• 200 Pin SO-DIMM: 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-3200
PC2-4200
PC2-5300*
PC2-6400*
Clock Speed
200MHz
266MHz
333MHz
400MHz
CL-tRCD-tRP
3-3-3
4-4-4
5-5-5
6-6-6
* Consult factory for availability
April 2006
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
April 2006
Rev. 1
Symbol
VREF
VSS
DQ0
DQ4
VSS
DQ5
DQ1
VSS
DQS0#
DM0
DQS0
VSS
VSS
DQ6
DQ2
DQ7
DQ3
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DM1
DQS1#
VSS
DQS1
DQ14
VSS
DQ15
DQ10
VSS
DQ11
DQ20
VSS
DQ21
DQ16
VSS
DQ17
RESET#
VSS
DM2
DQS2#
VSS
DQS2
DQ22
VSS
DQ23
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
DQ18
VSS
DQ19
DQ28
VSS
DQ29
DQ24
VSS
DQ25
DM3
VSS
VSS
DQS3#
DQ30
DQS3
DQ31
VSS
VSS
DQ26
CB4
DQ27
CB5
VSS
VSS
CB0
DM8
CB1
VSS
VSS
CB6
DQS8#
CB7
DQS8
VSS
VSS
CB2
CKE0
CB3
NC
VSS
NC
NC
VCC
NC
A12
A11
A9
VCC
A7
A8
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
VCC
A6
A5
A4
A3
VCC
A2
A1
VCC
A0
A10/AP
BA1
BA0
VCC
RAS#
WE#
VCC
CS0#
CAS#
ODT0
NC
A13
VCC
VCC
NC
CK
NC
CK#
DQ32
VSS
VSS
DQ36
DQ33
DQ37
DQS4#
VSS
DQS4
DM4
VSS
VSS
DQ34
DQ38
DQ35
DQ39
VSS
VSS
DQ40
DQ44
DQ41
DQ45
PIN NAMES
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
VSS
VSS
DQS5#
DM5
DQS5
VSS
VSS
DQ46
DQ42
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DM6
DQS6#
VSS
DQS6
DQ54
VSS
DQ55
DQ50
VSS
DQ51
DQ60
VSS
DQ61
DQ56
VSS
DQ57
DM7
VSS
DQ62
DQS7#
VSS
DQS7
DQ63
DQ58
SDA
VSS
SCL
DQ59
SA1
VCCSPD
SA0
2
Pin Name
A0-A13
Function
Address Inputs
BA0, BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
DQS0#-DQS8#
ODT0
CK,CK#
CKE0
CS0#
RAS#
CAS#
WE#
RESET#
VCC
VSS
SA0-SA1
SDA
VREF
DM0-DM8
VCCSPD
SCL
NC
SDRAM Bank Address
Data Input/Output
Check Bits
Data strobes
Data strobes complement
On-die termination control
Clock inputs
Clock enable input
Chip select input
Row Address Strobe
Column Address Strobe
Write Enable
Register reset input
Core Power
Ground
SPD address
Serial Data Input/Output
Input/Output Reference Voltage
Data-in mask
Serial EEPROM power supply
SPD Clock Input
No connect
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
RCS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DM/
RDQS
DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#
DQS DQS#
CS#
DQS DQS#
CS#
DQS DQS#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS5#
DM5
DQS1
DQS1#
DM1
DM/
RDQS
CS#
DM/
RDQS
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6#
DM6
DQS2
DQS2#
DM2
DM/
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS#
DM/
RDQS
DQS DQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS7
DQS7#
DM7
DQS3
DQS3#
DM3
DM/
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS#
DM/
RDQS
DQS DQS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS8
DQS8#
DM8
Serial PD
DM/
RDQS
CS#
DQS DQS#
SCL
SDA
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS0#
BA0-BA1
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#**
WP A0
A1
A2
SA0 SA1
1:2
R
E
G
I
S
T
E
R
RCS0# CS# : DDR2 SDRAMs
RBA0 - RBA1 BA0-BA1 : DDR2 SDRAMs
RA0 - RA13
A0-A13 : DDR2 SDRAMs
RRAS#
RAS# : DDR2 SDRAMs
RCAS#
CAS# : DDR2 SDRAMs
RWE#
WE# : DDR2 SDRAMs
RCKE0
CKE : DDR2 SDRAMs
RODT0
ODT : DDR2 SDRAMs
120
CK
CK#
PLL
RESET#**
VCCSPD
RST#
PCK**
PCK#**
SA2
CK
CK#
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
REGISTER X 2
Serial PD
VCC/VCCQ
DDR2 SDRAMs
VREF
DDR2 SDRAMs
VSS
DDR2 SDRAMs
** RESET#, PCK and PCK# connect to both Registers. Other signals connect to one of two Registers.
Note: All resistor values are 22 ohms ±5% unless otherwise specified.
April 2006
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
VCC
Voltage on VCC pin relative to VSS
-0.5
2.3
V
VIN, VOUT
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage Temperature
-55
100
°C
Command/Address,
RAS#, CAS#, WE#,
-5
5
µA
CK, CK#
-10
10
µA
TSTG
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
IL
IOZ
IVREF
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
DM
-5
5
µA
DQ, DQS, DQS#
-5
5
µA
-18
18
µA
VREF leakage current; VREF = Valid VREF level
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply Voltage
VCC
1.7
1.8
1.9
V
3
I/O Reference Voltage
VREF
0.49 x VCC
0.50 x VCC
0.51 x VCC
V
1
VTT
VREF-0.04
VREF
VREF+0.04
V
2
VCCSPD
1.7
-
3.6
V
I/O Termination Voltage
SPD Supply Voltage
Notes:
1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. VCCQ of all IC's are tied to VCC.
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Case Temperature (Commercial)
TOPER
0 to +85°C
°C
1, 2
NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 to +85°C, operation temperature range, all DRAM specification will be supported.
April 2006
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Input High (Logic 1) Voltage
Input High (Logic 0) Voltage
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.300
Max
VCC + 0.300
VREF - 0.125
Unit
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
AC Input High (Logic 1) Voltage
DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage
DDR2-667
AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533
AC Input High (Logic 0) Voltage
DDR2-667
Symbol
Min
Max
Unit
VIH(AC)
VREF + 0.250
-
V
VIH(AC)
VREF + 0.200
-
V
VIL(AC)
-
VREF - 0.250
V
VIL(AC)
-
VREF - 0.200
V
INPUT/OUTPUT CAPACITANCE
TA=25°C, f=100MHz
Parameter
Input capacitance (A0~A13, BA0~BA1,
RAS#, CAS#, WE#)
Input capacitance (CKE0), (ODT0)
Input capacitance (CS0#)
Input capacitance (CK, CK#)
Input capacitance (DM0~DM8),
(DQS0~DQS8)
Input capacitance (DQ0~DQ63),
(CB0~CB7)
April 2006
Rev. 1
Symbol
Min
Max
Unit
CIN1
11
12
pF
CIN2
CIN3
CIN4
CIN5 (665)
CIN5 (534, 403)
COUT1 (665)
COUT1 (534, 403)
11
11
10
6.5
6.5
6.5
6.5
12
12
11
7.5
8
7.5
8
pF
pF
pF
pF
pF
pF
pF
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
VCC = +1.8V ± 0.1V
Symbol
ICC0*
ICC1*
ICC2P*
ICC2Q**
ICC2N**
ICC3P**
ICC3N**
ICC4W*
ICC4R*
ICC5B**
ICC6**
ICC7*
Proposed Conditions
806
665
534
403
Units
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,265
1,220
1,220
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
TBD
1,400
1,355
1,355
mA
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD
572
572
572
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD
815
770
770
mA
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
TBD
860
815
815
mA
Fast PDN Exit MRS(12) = 0
TBD
770
770
770
mA
Slow PDN Exit MRS(12) = 1
TBD
608
608
608
mA
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
995
950
950
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,760
1,580
1,490
mA
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as ICC4W
TBD
1,805
1,625
1,490
mA
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
1,805
1,760
1,760
mA
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs
are FLOATING; Data bus inputs are FLOATING
TBD
72
72
72
mA
TBD
2,480
2,480
2,480
mA
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
April 2006
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
PARAMETER
MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CK high-level width
tCH
CK low-level width
Half clock period
Clock jitter
DQ output access time from CK/CK#
Data-out high-impedance window from
CK/CK#
Data-out low-impedance window from
CK/CK#
DQ and DM input setup time relative to
DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each
input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
Data valid output window (DVW)
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold
time
DQS…DQ skew, DQS to last DQ valid, per
group,
per access
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching
transition
tCL
tHP
tJIT
tAC
Data
Clock
Clock cycle time
Data Strobe
665
SYMBOL
tCK (6)
tCK (5)
tCK (4)
tCK (3)
CL = 6
CL = 5
CL = 4
CL = 3
tHZ
tLZ
tDS
tDH
tDIPW
tQHS
tQH
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
534
403
MIN
MAX
MIN
MAX
MIN
MAX
TBD
3,000
3,750
5,000
8,000
8,000
8,000
3,750
5,000
8,000
8,000
5,000
5,000
8,000
8,000
UNIT
ps
ps
ps
ps
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
TBD
TBD
0.55
TBD
TBD
TBD
TBD
0.45
MIN(tCH,tCL)
-125
-600
0.55
TBD
0.45
MIN(tCH,tCL)
-125
-500
0.55
TBD
0.45
MIN(tCH,tCL)
-125
-450
125
+600
tCK
ps
ps
ps
TBD
TBD
tAC(MAX)
ps
TBD
TBD
tAC(MAX)
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
125
+450
tAC(MAX)
tAC(MIN)
tAC(MAX)
125
+500
tAC(MAX)
tAC(MIN)
tAC(MAX)
tAC(MIN)
100
100
150
225
225
275
0.35
0.35
0.35
340
400
tCK
450
ps
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
tQH - tDQSQ
0.35
0.35
-400
0.2
tQH - tDQSQ
0.35
0.35
-450
0.2
tQH - tDQSQ
0.35
0.35
-500
0.2
ns
tCK
tCK
ps
tCK
+400
0.2
tDQSQ
+450
0.2
240
+500
0.2
300
tCK
350
ps
1.1
0.6
tCK
tCK
ps
tCK
tCK
tRPRE
tRPST
TBD
TBD
TBD
TBD
tWPRES
tWPRE
tWPST
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tIPW
TBD
TBD
Address and control input setup time
tIS
TBD
TBD
tIH
TBD
TBD
200
275
250
375
350
475
ps
Address and control input hold time
Address and control input hold time
tCCD
TBD
TBD
2
2
2
tCK
Address and control input pulse width for
each input
tDQSS
0.9
0.4
0
0.35
0.4
WL0.25
0.6
1.1
0.6
0.6
WL+
0.25
0.9
0.4
0
0.35
0.4
WL0.25
0.6
1.1
0.6
0.6
WL+
0.25
0.9
0.4
0
0.35
0.4
WL0.25
0.6
0.6
WL+
0.25
tCK
tCK
ps
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
April 2006
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
AC TIMING PARAMETERS (cont'd)
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
Self Refresh
Command and Address
PARAMETER
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge
time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
SYMBOL
MIN
MAX
MIN
tRC
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
tDAL
TBD
TBD
TBD
TBD
60
7.5
15
37.5
40
7.5
15
tWR+tRP
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tWTR
tRP
tRPA
tMRD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tDELAY
TBD
TBD
TBD
TBD
tRFC
Average periodic refresh interval
tREFI
TBD
TBD
Exit self refresh to non-READ command
tXSNR
TBD
TBD
534
MAX
MIN
37.5
70,000
60
7.5
15
37.5
40
7.5
15
tWR+tRP
7.5
15
tRP+tCK
2
tIS+tCK
tIH
105
403
MAX
MIN
37.5
70,000
55
7.5
15
37.5
40
7.5
15
tWR+tRP
7.5
15
tRP+tCK
2
tIS+tCK
tIH
70,000
105
7.8
MAX
UNIT
37.5
70,000
ns
ns
ns
ns
ns
ns
ns
ns
10
15
tRP+tCK
2
tIS+tCK
tIH
70,000
105
7.8
tRFC(MIN)
+10
200
tRFC(MIN)
+10
200
tIS
tIS
ns
ns
ns
tCK
ns
70,000
ns
7.8
µs
Exit self refresh to READ command
tXSRD
TBD
TBD
tRFC(MIN)
+10
200
Exit self refresh timing reference
tISXR
TBD
TBD
tIS
ODT turn-on delay
tAOND
TBD
TBD
2
2
2
2
2
2
tCK
ODT turn-on
tAON
TBD
TBD
tAC(MIN)
tAC(MAX)
+1000
tAC(MIN)
tAC(MAX)
+1000
tAC(MIN)
tAC(MAX)
+1000
ps
ODT turn-off delay
tAOFD
TBD
TBD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
tAOF
TBD
TBD
tAC(MIN)
tAC(MIN)
tAC(MIN)
+2000
tAC(MAX)
+600
2 x tCK+
tAC(MIN)
+1000
2.5 x
tCK+
tAC(MIN)
+1000
ps
TBD
tAC(MAX)
+600
2 x tCK+
tAC(MIN)
+1000
2.5 x
tCK+
tAC(MIN)
+1000
tAC(MIN)
TBD
tAC(MAX)
+600
2 x tCK+
tAC(MIN)
+1000
2.5 x
tCK+
tAC(MIN)
+1000
ODT turn-on (power-down mode)
tAONPD
ODT turn-off (power-down mode)
tAOFPD
TBD
Power-Down
665
REFRESH to Active of Refresh to Refresh
command interfal
ODT turn-off
ODT
806
TBD
tAC(MIN)
+2000
tAC(MIN)
+2000
tAC(MIN)
+2000
tAC(MIN)
+2000
tAC(MIN)
+2000
ns
tCK
ps
ps
ps
ODT to power-down entry latency
tANPD
TBD
TBD
3
3
3
tCK
ODT power-down exit latency
tAXPD
TBD
TBD
8
8
8
tCK
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
A Exit precharge power-down to any nonREAD command.
CKE minimum high/low time
tXARD
TBD
TBD
2
2
2
tCK
tXARDS
TBD
TBD
7-AL
6-AL
6-AL
tCK
tXP
TBD
TBD
2
2
2
tCK
tCKE
TBD
TBD
3
3
3
tCK
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
April 2006
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
ORDERING INFORMATION FOR PD4
Part Number
Speed/Data Rate
Frequency
CAS
Latency
tRCD
tRP
Height*
WV3HG64M72EER806PD4xxG**
400MHz/800Mb/s
6
6
6
30.00mm (1.181") TYP
WV3HG64M72EER665PD4xxG**
333MHz/667Mb/s
5
5
5
30.00mm (1.181") TYP
WV3HG64M72EER534PD4xxG
266MHz/533Mb/s
4
4
4
30.00mm (1.181") TYP
WV3HG64M72EER403PD4xxG
200MHz/400Mb/s
3
3
3
30.00mm (1.181") TYP
** Consult factory for availability
NOTES:
• RoHS compliant product (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR PD4
3.8 (0.150)
MAX
67.75 (2.667)
67.45 (2.656)
4.10(0.161)(2X)
3.90(0.154)
30.15 (1.187)
29.85 (1.175)
1.80 (0.071)
(2X)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
2.15 (0.085)
1.00 (0.039)
TYP
PIN 1
1.10 (0.043)
0.90 (0.035)
0.45 (0.018) 0.60 (0.024)
TYP
TYP
PIN 199
2.504 (63.60)
TYP
BACK VIEW
PIN 200
4.2 (0.165)
TYP
47.40 (1.866)
TYP
PIN 2
11.40 (0.449)
TYP
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
Tolerances: ±0.13 (0.005) unless otherwise specified
April 2006
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 64M 72 E E R xxx PD4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
REGISTERED
SPEED (Mb/s)
PACKAGE 200 PIN SO-DIMM
(P = JEDEC proposed pin-out)
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
April 2006
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG64M72EER-PD4
ADVANCED
Document Title
512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, SO-DIMM
DRAM DIE OPTIONS:
• SAMSUNG: C-Die, will move to E-Die Q2'06
• MICRON: U37: B-Die
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
March 2006
Concept
Rev 1
1.0 Moved from concept to advanced
April 2006
Advanced
1.1 Added "P" for JEDEC proposed pin-out
1.2 Added die rev info
1.3 Added VCCSPD voltage specification
April 2006
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com