19-2144; Rev 1; 7/04 +3.3V, 2.5Gbps Quad Limiting Amplifier The MAX3822 quad limiting amplifier is ideal for multichannel systems with data rates up to 2.5Gbps. The MAX3822 operates from a single +3.3V supply, over temperatures ranging from 0°C to +85°C. A channelselect (CS) pin is provided to program single-, dual-, or quad-channel operation. The disabled channels are shut down to reduce power consumption. The output interface for all four channels is CML. The input can be driven from 20mVp-p to 1000mVp-p differentially. The threshold voltage control is common for all four channels and is programmable by an external resistor. Four separate power detectors are incorporated to monitor the received signal level for each channel. Individual TTL-compatible loss-of-power (LOP) indicators assert low if the channel signal input is below the programmed threshold. Typically 4dB LOP hysteresis (2dB optical) is provided to prevent chattering when the input signal level is close to the threshold. A general LOP indicator is also provided which asserts low if one or more of the four inputs is in the LOP condition. Applications Optical System Interconnects Multichannel Receiver Modules Dense Digital Cross-Connects ATM Switch Networks High-Speed Parallel Links Features ♦ Single +3.3V Supply ♦ Single-, Dual-, or Quad-Channel Operation at 2.5Gbps ♦ 700mW Total Power Dissipation (Quad-Channel Operation) ♦ 120ps Maximum Output Edge Speed ♦ Overall and Individual Channel Loss-of-Power (LOP) Indicator ♦ Differential CML Outputs with On-Chip Back Termination Resistors ♦ 30ps Maximum Deterministic Jitter ♦ 2ps Random Jitter ♦ Power-Down Feature Shuts Down Unused Channels ♦ Operating Temperature Range: 0°C to +85°C Ordering Information PART TEMP RANGE MAX3822UCM PIN-PACKAGE 0°C to +85°C 48 TQFP-EP* MAX3822UCM+ 0°C to +85°C 48 TQFP-EP* MAX3822U/D 0°C to +85°C Dice** *Exposed pad. **Contact factory for availability. Dice are designed to operate from TA = 0°C to TA = +85°C, but are tested and guaranteed only at TA = +25°C. +Denotes lead-free package. 37 38 39 40 41 42 43 44 45 46 47 48 TOP VIEW GND CZ1+ CZ1GND CZ2+ CZ2GND CS GND GND VTH GND Pin Configuration Typical Operating Circuit appears at end of data sheet. IN1+ IN1VCC 1 36 2 35 3 34 IN2+ IN2VCC VCC IN3+ IN3VCC IN4+ IN4- 4 33 5 32 6 31 MAX3822 7 30 24 23 22 21 20 19 GND CZ4CZ4+ GND CZ3CZ3+ GND LOP LOP1 LOP2 LOP3 LOP4 18 25 17 26 12 16 27 11 15 28 10 14 29 9 13 8 OUT1+ OUT1VCC OUT2+ OUT2VCC VCC OUT3+ OUT3VCC OUT4+ OUT4- TQFP-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3822 General Description MAX3822 +3.3V, 2.5Gbps Quad Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) ........................................... -0.5V to +6.0V Differential Input Voltage Swing (IN1+ - IN1-), (IN2+ - IN2-), (IN3+ - IN3-), (IN4+ - IN4-) ..............................................2Vp-p Voltage at LOP1, LOP2, LOP3, LOP4, LOP, CS........................................-0.5V to (VCC + 0.5V) Voltage at IN1+, IN1-, IN2+, IN2-, IN3+, IN3-, IN4+, IN4- .............................(VCC - 1V) to (VCC + 0.5V) Voltage at VTH .....................................................+0.5V to +2.3V Voltage at CZ1+, CZ1-, CZ2+, CZ2-, CZ3+, CZ3-, CZ4+, CZ4- ........................-0.5V to (VCC + 0.5V) Current into OUT1+, OUT1-, OUT2+, OUT2-, OUT3+, OUT3-, OUT4+, OUT4-, ..................................±22mA Continuous Power Dissipation (TA = +85°C) 48-Pin TQFP-EP (derate 29.4mW/°C above +85°C) ......2.35W Operating Junction Temperature Range(die) ...-55°C to +150°C Processing Temperature (die) .........................................+400°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 1) PARAMETER Power-Supply Current SYMBOL ICC CONDITIONS MIN 60 72 Dual channel (Note 2) 110 137 210 VCC 0.5 VIS Single-Ended Data Input Resistance 40 RTH = 1kΩ Data Input Voltage for LOP Assert RTH = 649Ω LOP Hysteresis 11.5 34 RTH = 1kΩ 4.5 RL = 50Ω to VCC Single-Ended Data Output Resistance 3.0 265 VCC + 0.25 V 60 Ω 32.5 mVp-p 6.0 dB 640 740 1000 mVp-p 40 50 60 Ω VCC 0.2 TTL Output High VOH Sourcing 200µA TTL Output Low VOL Sinking 2mA mA 3.4 CML Output Common-Mode Voltage 2 18.5 RTH = 400Ω RTH = 649Ω VOD 50 UNITS 14 RTH = 400Ω CML Differential Output MAX Single channel (Note 2) Quad channel Single-Ended Data Input Voltage Range TYP 2.4 _______________________________________________________________________________________ V VCC V 0.4 V +3.3V, 2.5Gbps Quad Limiting Amplifier (VCC = +3.0V to +3.6V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Notes 1, 3) PARAMETER Data Input Voltage Range Random Jitter Deterministic Jitter Data Output Edge Speed SYMBOL CONDITIONS VIN MIN TYP 20 UNITS mVp-p 9.5 psRMS (Note 4) 2 VIN = 20mVp-p (Notes 5, 6) 8 VIN = 1000mVp-p to 1000mVp-p (Notes 5, 6) 4 30 90 120 (20% to 80%) LOP Assert/Deassert Time 100 psp-p ps ns Input-Referred Noise (Note 7) 105 Offset Correction LowFrequency Cutoff CZ1 = CZ2 = CZ3 = CZ4 = 0.033µF 150 Channel-to-Channel Skew (Note 8) 20 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: MAX 1000 594 µVRMS kHz 70 ps Characteristics at 0°C are guaranteed by design and characterization. Dice are tested at TA = +25°C. When power is first applied, all four channels are briefly active. AC characteristics are guaranteed by design and characterization. Input data edge speed of 150ps (20% to 80%). Data rate = 2.5Gbps. Measured with 213 -1 PRBS plus 100 consecutive identical digits. Deterministic jitter (p-p) equals total jitter (p-p) minus random jitter (p-p). Input-referred noise is specified (differential output noise)/(small-signal gain). Measured by applying the same input signal to all channels. Skew measurements are made at 50% point of the transition. _______________________________________________________________________________________ 3 MAX3822 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) RANDOM JITTER vs. DIFFERENTIAL INPUT VOLTAGE 8 9 8 RANDOM JITTER (psRMS) 7 6 5 4 3 MAX3822 toc02 10 MAX3822 toc01 9 ELECTRICAL EYE DIAGRAM (VIN = 1V DIFFERENTIAL) MAX3822 toc03 DETERMINISTIC JITTER vs. DIFFERENTIAL INPUT VOLTAGE 7 6 5 100mV/div 4 3 2 2 1 1 0 0 0 100 200 300 400 500 600 700 800 900 1000 DIFFERENTIAL INPUT VOLTAGE (mVp-p) ELECTRICAL EYE DIAGRAM (VIN = 20mV DIFFERENTIAL) ELECTRICAL EYE DIAGRAM (VIN = 100mV DIFFERENTIAL) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY MAX3822 toc04 100mV/div 100mV/div 75ps/div MAX3822 toc05 DIFFERENTIAL INPUT VOLTAGE (mV) 0 MAX3822 toc06 0 100 200 300 400 500 600 700 800 900 1000 POWER-SUPPLY REJECTION RATIO (dB) PEAK-TO-PEAK DETERMINISTIC JITTER (psp-p) -10 -20 -30 -40 -50 -60 -70 -80 -90 75ps/div 75ps/div 1 10 100 FREQUENCY (MHz) LOSS-OF-POWER THRESHOLD LEVEL vs. THRESHOLD RESISTANCE COMMON-MODE REJECTION RATIO vs. FREQUENCY 5 0 -5 -10 -15 -20 60 50 40 DEASSERT THRESHOLD 30 20 ASSERT THRESHOLD 10 0 -25 1 10 FREQUENCY (MHz) 4 MAX3822 toc08 10 70 DIFFERENTIAL INPUT VOLTAGE (mVp-p) MAX3822 toc07 15 COMMON-MODE REJECTION RATIO (dB) MAX3822 +3.3V, 2.5Gbps Quad Limiting Amplifier 100 0 400 800 1200 1600 RTH (Ω) _______________________________________________________________________________________ 2000 1000 +3.3V, 2.5Gbps Quad Limiting Amplifier PIN NAME 1 IN1+ Noninverted Data Input for Channel 1 DESCRIPTION 2 IN1- Inverted Data Input for Channel 1 3, 6, 7, 10, 27, 30, 31, 34 VCC +3.3V Supply Voltage 4 IN2+ Noninverted Data Input for Channel 2 5 IN2- Inverted Data Input for Channel 2 8 IN3+ Noninverted Data Input for Channel 3 9 IN3- Inverted Data Input for Channel 3 11 IN4+ Noninverted Data Input for Channel 4 12 IN4- Inverted Data Input for Channel 4 13, 16, 19, 37, 39, 40, 42, 45, 48 GND Supply Ground 14 CZ4- A capacitor connected between this pin and CZ4+ extends the time constant for the offsetcorrection loop associated with channel 4. Maxim recommends a capacitor value of 0.033µF. 15 CZ4+ A capacitor connected between this pin and CZ4- extends the time constant for the offsetcorrection loop associated with channel 4. Maxim recommends a capacitor value of 0.033µF. 17 CZ3- A capacitor connected between this pin and CZ3+ extends the time constant for the offsetcorrection loop associated with channel 3. Maxim recommends a capacitor value of 0.033µF. 18 CZ3+ A capacitor connected between this pin and CZ3- extends the time constant for the offsetcorrection loop associated with channel 3. Maxim recommends a capacitor value of 0.033µF. 20 LOP LOP is low when any of the individual power detectors (LOP1, LOP2, LOP3, LOP4) are low. 21 LOP1 LOP1 asserts low when the data input signal level to channel 1 drops below the programmed threshold. 22 LOP2 LOP2 asserts low when the data input signal level to channel 2 drops below the programmed threshold. 23 LOP3 LOP3 asserts low when the data input signal level to channel 3 drops below the programmed threshold. 24 LOP4 LOP4 asserts low when the data input signal level to channel 4 drops below the programmed threshold. 25 OUT4- Inverted Data Output for Channel 4 _______________________________________________________________________________________ 5 MAX3822 Pin Description +3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822 Pin Description (continued) PIN NAME 26 OUT4+ Noninverted Data Output for Channel 4 DESCRIPTION 28 OUT3- Inverted Data Output for Channel 3 29 OUT3+ Noninverted Data Output for Channel 3 32 OUT2- Inverted Data Output for Channel 2 33 OUT2+ Noninverted Data Output for Channel 2 35 OUT1- Inverted Data Output for Channel 1 36 OUT1+ Noninverted Data Output for Channel 1 38 VTH A resistor connected from this pin to ground sets the data input signal level at which the loss-ofpower outputs will be asserted. 41 CS Channel-Select Input. To enable channel 1 only, leave CS open. To enable channels 1 and 2, connect CS to VCC. To enable all four channels, connect CS to GND. 43 CZ2- A capacitor connected between this pin and CZ2+ extends the time constant for the offsetcorrection loop associated with channel 2. Maxim recommends a capacitor value of 0.033µF. 44 CZ2+ A capacitor connected between this pin and CZ2- extends the time constant for the offsetcorrection loop associated with channel 2. Maxim recommends a capacitor value of 0.033µF. 46 CZ1- A capacitor connected between this pin and CZ1+ extends the time constant for the offsetcorrection loop associated with channel 1. Maxim recommends a capacitor value of 0.033µF. 47 CZ1+ A capacitor connected between this pin and CZ1- extends the time constant for the offsetcorrection loop associated with channel 1. Maxim recommends a capacitor value of 0.033µF. EP Exposed Pad Ground. This must be soldered to a circuit board for proper thermal and electrical performance (see Exposed Pad (EP) Package). Detailed Description The MAX3822 is a 2.5Gbps quad limiting amplifier designed for fiber applications with input sensitivities as low as 20mVp-p. This device has internally terminated CML inputs with loss-of-power circuitry for each channel, as well as a general loss-of-power indicator valid for the whole part. Offset correction ensures low pulse-width distortion (PWD) and reduced patterndependent jitter (PDJ). A channel-select (CS) pin is used to control the device’s mode of operation as single, dual, or quad. The inputs of the MAX3822 are typically connected to a transimpedance amplifier (TIA) (MAX3825) found within a fiber-optic link. The output signal from a TIA can contain significant amounts of noise, and may vary in amplitude over time. The MAX3822 limiting amplifier quantizes the input signal, and outputs a voltage-limited waveform over a 40dB input dynamic range. Signal input to this device passes through a buffer to a lineargain amplifier. This linear-gain amplifier (Figure 1) drives the power-detection circuitry and a chain of limiting amplifiers leading to the CML output buffer. 6 The power-detection circuitry is used to indicate that the data input voltage has fallen below the programmed threshold level. Each individual channel has a power detector output (LOP1, LOP2, LOP3, LOP4). The LOP output is low when any of the individual powerdetector outputs are low. A threshold adjustment pin (VTH) programs the signal-detect threshold for all four channels with a single external resistor. The offset-correction loop adjusts the input buffer bias until the CML output buffer has a zero offset. This offset-correction loop acts as a high-pass filter where signal components below 150kHz are attenuated. Input Buffer and Gain Stages The MAX3822’s inputs are terminated with 50Ω to VCC (Figure 2). The inputs do not need to be AC-coupled if the upstream TIA has CML outputs, but should be ACcoupled if the differential logic levels are in any other format. The differential input signal is passed through a buffer, and then continues through two sets of differential amplifiers, each with an emitter-follower output stage. The first differential amplifier provides approximately 10dB gain and a linear output for input signals _______________________________________________________________________________________ +3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822 CZ1+ CZ1- LIMITING AMPLIFIER #1 LOW PASS OFFSET CORRECTION OUT1+ IN1+ BUFF GAIN GAIN CML IN1- OUT1- LOSS-OF-POWER LOGIC R RECTIFIER AND LOW-PASS FILTER Q LOP1 S VTH THRESHOLD CONTROL RTH LOSS OF POWER LOP CS CHANNEL SELECT MAX3822 LIMITING AMPLIFIER #2 CZ2+ IN2+ IN2- LIMITING AMPLIFIER #3 LOP2 CZ2CZ3+ OUT2+ OUT2- IN3+ IN3- LIMITING AMPLIFIER #4 LOP3 CZ3CZ4+ OUT3+ OUT3IN4+ IN4- LOP4 CZ4OUT4+ OUT4- Figure 1. Functional Diagram up to 80mVp-p. This differential amplifier is designed to work with the power-detect circuitry. The next high-gain amplifier provides an additional gain of approximately 22dB. This gain stage functions similarly to the input-gain stage. The output signal from this gain stage is applied to the CML output buffer shown in Figure 3, and is used in the offset-correction loop. The input voltage range is limited to VCC + 0.5V by the ESD structure, and to a minimum of VCC - 1V by the internal resistor. Figure 2 shows a model of the input stage of the MAX3822, including the package capacitance and the bond wire inductance. The additional 0.4pF capacitance on the inputs represents the ESD diode’s junction capacitance and a small contribution by the bond pad. For more information about the CML electrical specifications and interfacing to other proto- cols, refer to Application Note HFAN-1.0, Introduction to LVDS, PECL, and CML. Be sure the MAX3822 is placed as close as possible to the TIA when using this device near sensitivity. If you are using a TIA with CML outputs, such as the MAX3825, AC-coupling capacitors are not required. Taking these precautions will ensure the best possible sensitivity. Output Buffer The MAX3822’s CML output buffer is designed to drive 50Ω lines that are used to feed the input of a clock- and data-recovery device (CDR). Figure 3 shows a model of the output stage showing some important details. The outputs of the device are terminated internally with 50Ω to VCC. ESD diode structures are connected to VCC and GND. Figure 3 also shows the model of the output _______________________________________________________________________________________ 7 MAX3822 +3.3V, 2.5Gbps Quad Limiting Amplifier PACKAGE DIE VCC ESD DIODES 50Ω 1.5nH IN+ 50Ω 0.2pF 0.4pF 1.5nH IN0.2pF 0.4pF GND Figure 2. Input Structure ESD DIODES 50Ω and may cause deterministic jitter through an increase of PWD. VCC 50Ω 1.5nH OUT+ 0.4pF 0.2pF 1.5nH OUT- 0.4pF DIE 0.2pF PACKAGE GND Figure 3. Output Structure stage of the MAX3822, including package capacitance and bond-wire inductance. The additional 0.4pF capacitance on the output represents the ESD diode’s junction capacitance and a small contribution by the bond pad. For more information about the CML electrical specifications and interfacing to other protocols, refer to Application Note HFAN-1.0, Introduction to LVDS, PECL, and CML. Offset Correction Each limiting amplifier on the MAX3822 provides approximately 50dB of gain. An input offset as small as 1mV reduces the power-detection circuitry’s accuracy 8 Each of the MAX3822’s integrated limiting amplifiers includes a DC cancellation loop that provides offset correction to the CML output signal in addition to lowfrequency power-supply noise rejection. The DC cancellation loop consists of a low-pass filter and a high-gain amplifier. The input voltage difference of the CML output buffer is amplified, sent through a low-pass filter, inverted, and summed up with the input signal that drives the high-gain input stage. This removes from the output signal all frequency components between the cutoff frequency and DC. The low-frequency cutoff of the DC cancellation loop is set by an external capacitor connected between CZ_+ and CZ_-. Power Detection and Threshold Control The MAX3822 incorporates a chatter-free loss-of-power function that is used to determine if the input signal has dropped below the programmed threshold level. The power detector is implemented by comparing the DCrectified output of the first gain stage to the programmed loss-of-power threshold. The threshold control circuitry enables programming of LOP_ assert and deassert reference voltages by using one external resistor, RTH (Figure 4). An internal amplifier guarantees a voltage at VTH of approximately 0.5V. The external resistor (RTH) connected to GND converts this voltage into a current. The current through this resistor sets the power threshold level for the device (see Typical Operating Characteristics, Loss-of-Power Threshold Level vs. RTH). _______________________________________________________________________________________ +3.3V, 2.5Gbps Quad Limiting Amplifier Channel Select The channel-select circuitry controls the operating mode of the MAX3822 by shutting down unused amplifiers. Single-, dual-, and quad-mode operation is programmed by the channel-select (CS) pin. When CS is left open, the device is placed into single-mode operation with channel 1 enabled, and channels 2, 3, and 4 disabled. Dualmode operation is programmed by connecting CS directly to VCC. In dual-mode operation, channels 1 and 2 are enabled and channels 3 and 4 are disabled. Quadmode operation is programmed by connecting CS directly to GND. In quad-mode operation, all four channels are enabled. Figure 6 shows the input circuitry of the CS pin. Applications Information Set Up the DC Cancellation Loop The value of the offset-correction capacitor (CZ_) affects the maximum speed at which the DC cancellation loop can adjust to changes in DC offset at the input. PWD and pattern-dependent jitter (PDJ) are both error sources that can be minimized by the proper selection of CZ_. Therefore, the loop should be as slow as possible to reduce PDJ while performing its DC cancellation function. Select the CZ_ capacitor to set the bandwidth of the DC cancellation loop. The input impedance between CZ+ and CZ- is approximately 10kΩ. This impedance is in series with CZ_. Therefore, the low-frequency cutoff (foc) associated with the DC offset-correction loop is computed as follows: VCC ESD DIODES VCC VREF ICTAL 2kΩ ESD DIODES 4kΩ LOP VTH RTH 18kΩ GND GND Figure 4. Threshold Set Structure GND Figure 5. TTL Output Structure _______________________________________________________________________________________ 9 MAX3822 Loss-Of-Power Logic (LOP) The loss-of-power logic circuitry is asserted anytime the input power of one of the limiting amplifiers is observed below the threshold set by R TH. The logic of this is comprised of two comparators and an S-R flip-flop to compare the outputs of the threshold-control and power-detect circuitry for each of the limiting amplifiers on the MAX3822. The LOP_ output corresponding to a given input is asserted if the input power is too low. A general LOP output is also given for the whole part; if any LOP_ signal is low, the LOP output will also go low. Once a LOP_ signal has been asserted, the input power must rise above the threshold before resetting. This prevents the LOP_ output from turning on and off when the input signal is near the programmed threshold level, an effect called chatter. The LOP_ indicator will return to its unasserted state when the input power level is increased (4dB typ). Figure 5 shows the output structure. MAX3822 +3.3V, 2.5Gbps Quad Limiting Amplifier In an optical receiver, the dB change at the MAX3822 will equal twice the optical dB change. The MAX3822’s typical voltage hysteresis is 4dB. This provides an optical hysteresis of 2dB. VCC ESD DIODES Exposed-Pad (EP) Package 30kΩ The exposed-pad, 48-pin TQFP-EP incorporates features that provide a very low thermal resistance path for heat removal from the IC. The pad is electrical ground on the MAX3822 and should be soldered to the circuit board for proper thermal and electrical performance. CS 40kΩ 20kΩ Chip Information TRANSISTOR COUNT: 813 SUBSTRATE CONNECTED TO GND PROCESS: Bipolar DIE SIZE: 90mil ✕ 102mil GND Figure 6. Channel-Select Interface 50dB 10 20 foc = 2π × 10kΩ × Cz _ Bond Pad Information (1804.6, 1966.6) (125.2, 2090.8) where 50dB is the gain of the offset-correction loop. Maxim recommends a value of 0.033µF for the filter capacitor. This value will set the lower cutoff frequency of the DC cancellation loop to approximately 150kHz. B HF65Z (46.9, 1804.6) (1947.6, 1804.6) Optical Hysteresis Power and hysteresis are often expressed in decibels. By definition, decibels are always 10log (ratio power). At the inputs to the MAX3822 limiting amplifier, the power is VIN2 / R. If a receiver’s optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage input to the MAX3822 will also increase by a factor of two. The optical power change is: 2x 10log = 10log(2) = + 3dB x MAX3822 A INDEX PAD Y (46.9, 46.9) (1947.6, 46.9) D (125.5, -215) X 10log 10 (2VIN ) /R VIN2 / R ( ) = 10log 22 = 20log(2) = + 6dB (1985.5, -215) *ORIENT PLOT, USING HF65Z AS A KEY. At the MAX3822, the voltage change is: 2 C • ALL DIMENSIONS ARE IN MICRONS • GST2 PROCESS • PAD DIMENSIONS: (BONDING AREA) H = 93.8MICRONS W = 93.8MICRONS • ALL MEASUREMENTS SPECIFY THE CENTER OF THE PAD. • ORIGIN IS DEFINED AS THE BOTTOM LEFT CORNER OF THE INDEX PAD ______________________________________________________________________________________ +3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822 (HF65Z) DIMENSIONS SIDE A SIDE B SIDE C SIDE D 46.9 46.9 125.2 2090.8 1947.6 46.9 125.2 -215 46.9 206.2 292.6 2090.8 1947.6 206.2 279.1 -215 46.9 365.5 460.0 2090.8 1947.6 365.5 433.0 -215 46.9 524.8 627.4 2090.8 1947.6 524.8 586.9 -215 46.9 684.1 794.8 2090.8 1947.6 684.1 740.8 -215 46.9 846.1 962.2 2090.8 1947.6 846.1 894.7 -215 46.9 1005.4 1129.6 2090.8 1947.6 1005.4 1048.6 -215 46.9 1167.4 1297.0 2090.8 1947.6 1167.4 1202.5 -215 46.9 1326.7 1464.4 2090.8 1947.6 1326.7 1356.4 -215 46.9 1486.0 1631.8 2090.8 1947.6 1486.0 1510.3 -215 46.9 1645.3 1799.2 2090.8 1947.6 1645.3 1664.2 -215 46.9 1804.6 1966.6 2090.8 1947.6 1804.6 1818.1 -215 1985.5 -215 Typical Operating Circuit CZ1 50Ω CZ2 CZ3 CZ4 IN1+ OUT1+ IN1- OUT1- IN2+ OUT2+ IN2- OUT2- 50Ω 50Ω IN1+ 50Ω IN150Ω IN2+ 50Ω IN250Ω IN3+ VCC CZ4 50Ω 50Ω VCC CZ3 CS CZ1 VCC CZ2 VCC VCC MAX3822 IN3- OUT3+ OUT3- 50Ω QUAD CDR WITH CML INPUTS IN3+ 50Ω IN350Ω MAX3827* 50Ω PHOTODIODE ARRAY 50Ω MAX3825 *FUTURE PRODUCT IN4+ OUT4+ IN4- OUT4- VTH IN4+ 50Ω IN450Ω RTH LOP1 LOP2 LOP3 LOP4 LOP GND ______________________________________________________________________________________ 11 MAX3822 Bond Pad Information (continued) MAX3822 +3.3V, 2.5Gbps Quad Limiting Amplifier Chip Topography GND VTH GND GND CS GND CZ2- CZ2+ GND CZ1- IN1+ OUT1+ IN1- OUT1- VCC VCC IN2+ OUT2+ IN2- OUT2- VCC VCC VCC VCC IN3+ OUT3+ IN3- OUT3- VCC VCC EPGND LOP4 LOP3 LOP2 LOP1 LOP GND CZ3+ CZ3- OUT4- GND IN4- CZ4+ OUT4+ CZ4- IN4+ GND 12 CZ1+ GND (90mil) ______________________________________________________________________________________ (102mil) +3.3V, 2.5Gbps Quad Limiting Amplifier 48L,TQFP.EPS PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.0mm EP OPTION 21-0065 F 1 2 ______________________________________________________________________________________ 13 MAX3822 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3822 +3.3V, 2.5Gbps Quad Limiting Amplifier Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.0mm EP OPTION 21-0065 F 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.