19-2624; Rev 0; 10/02 10Gbps 1:16 Deserializer with Clock Recovery Features ♦ Serial Data Rate: 9.953Gbps/10.3125Gbps ♦ Clock Recovery with 1:16 Demultiplexer ♦ 0.75UIP-P High-Frequency Jitter Tolerance ♦ 16-Bit Parallel LVDS Output ♦ OIF-Compliant Parallel Interface ♦ Loss-of-Lock (LOL) Indicator ♦ Differential Input Range: 100mVP-P to 1.2VP-P The MAX3953 includes TTL-compatible loss-of-lock (LOL) and sync-error (SYNC_ERR) indicators that allow the user to verify that the part has locked on to incoming data. In case the incoming data becomes invalid, a clock holdover function is provided to maintain a valid reference clock to the upstream device. For proper operation, a reference clock of baud rate/64 or baud rate/16 is required. ♦ Clock Holdover ♦ Reference Clock: Baud Rate/64 or Baud Rate/16 ♦ Temperature Range: 0°C to +85°C ♦ 10mm ✕ 10mm 68-Pin QFN Package The MAX3953 operates from a single +3.3V power supply and typically dissipates 1.5W. The operating temperature range is from 0°C to +85°C. The MAX3953 is available in a 68-pin QFN package. Ordering Information Applications PART MAX3953UGK 10Gbps Ethernet LAN 10Gbps Ethernet WAN TEMP RANGE 0oC to +85oC PIN-PACKAGE 68 QFN (10mm × 10mm) Pin Configuration and Functional Diagram appear at end of data sheet. Add/Drop Multiplexers Digital Cross-Connects Typical Operating Circuit +3.3V VCC RATESET -3.3V 100Ω* FIL PDOI5- 0.1µF 0.01µF REFCLK+ 161MHz CLOCK PDO0+ OVERHEAD 100Ω* TERMINATION 100Ω* REFCLK- MAX3953 0.1µF 100Ω* SDI+ MAX3970 0.1µF PDO0PCLK0+ 0.1µF 0.1µF TIA VCC PDOI5+ 0.047µF LIMITING AMP MAX3971A PCLK0LOL SDI0.1µF LOS_IN GND REFSET SYNC_ERR CLKSEL *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3953 General Description The MAX3953 is a 9.953Gbps/10.3125Gbps 1:16 deserializer with clock recovery for 10Gbps Ethernet and OC192 SONET applications. The integrated phaselocked loop (PLL) recovers a clock from the serial data input, and the data is then retimed and demultiplexed into 16 parallel LVDS outputs. Using Maxim’s SiGe bipolar process, the MAX3953 can achieve 0.75UI of high-frequency jitter tolerance comprised of 0.50UI of deterministic jitter and 0.25UI of random jitter. MAX3953 10Gbps 1:16 Deserializer with Clock Recovery ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) ............................................-0.5V to +5.0V Input Voltage Levels (SDI+, SDI-) .................................(VCC - 1.0V) to (VCC + 0.5V) LVDS Output Voltage Levels (PDO[15..0]±, PCLKO+, PCLKO-) .........-0.5V to (VCC + 0.5V) Voltage at LOL, SYNC_ERR, RATESET, CLKSEL, REFCLK+, REFCLK-, REFSET, LOS_IN, FIL ............-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = 85°C) 68-Lead QFN (derate 30.3mW/°C above +85°C) ............2.5W Operating Temperature Range.............................. 0°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Processing Temperature (die) .........................................+400°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 476 580 mA 100 1200 mVP-P VCC 0.3 VCC V 60 Ω 300 1600 mVP-P LVPECL Input High Voltage VCC 1.16 VCC 0.88 V LVPECL Input Low Voltage VCC 1.81 VCC 1.48 V POWER SUPPLY Supply Current ICC INPUT SPECIFICATION (SDI+, SDI-) Figure 1 Differential Input Voltage VID Common-Mode Input Range Input Termination to VCC AC-coupled or DC-coupled input DC-coupled RIN 40 50 REFERENCE CLOCK INPUT (REFCLK+, REFCLK-) (Note 1) Differential Input Voltage AC-coupled or DC-coupled input LVPECL Input Bias Voltage Differential Input Impedance VCC 1.3 V 2.6 kΩ OUTPUT SPECIFICATION (PDO[15..0]±, PCLKO±) LVDS Output High Voltage VOH LVDS Output Low Voltage VOL 0.925 VOD 250 LVDS Differential Output Voltage LVDS Change in Magnitude of Differential Output for Complementary States LVDS Offset Output Voltage LVDS Change in Magnitude of Output Offset Voltage for Complementary States ∆VOD VOD 1.125 ∆VOD LVDS Differential Output Impedance LVDS Output Current 2 80 Short together or short to GND _______________________________________________________________________________________ 1.475 V 400 mV 25 mV 1.275 V 25 mV 140 Ω 20 mA V 10Gbps 1:16 Deserializer with Clock Recovery (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVTTL INPUT AND OUTPUT (CLKSEL, SYN_ERR, RATESET, LOS_IN, LOL, REFSET) LVTTL Input High Voltage VIH LVTTL Input Low Voltage VIL 2 LVTTL Input Current LVTTL Output High Voltage VOH IOH = 20µA LVTTL Output Low Voltage VOL IOL = 1mA V 0.8 V -50 +6 µA 2.4 VCC V 0.4 V Note 1: Reference clock duty cycle can range from 30% to 70%. AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at +3.3V and TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL Serial Input Data Rate Sinusoidal Jitter Tolerance Tolerated Consecutive Identical Digits CONDITIONS MIN 9.953 RATESET = VCC 10.3125 f = 400kHz (Notes 3, 4) 1.5 f = 4MHz (Note 3) 0.15 Bit-error ratio (BER) = 10-12 Input Return Loss TYP RATESET = GND MAX UNITS Gbps UIP-P 2000 f < 10GHz, differential 10 f < 15GHz, differential 8 f < 15GHz, common mode 9 Bits dB Frequency Difference when PLL Indicates Out of Lock 1000 ppm Frequency Difference when PLL Indicates In Lock 500 ppm LOL Assert Time No transitions at input, Figure 2 PLL Acquisition Time Valid transitions at input, Figure 2 30 Maximum PCLKO Deviation from REFCLK Output Clock to Data Delay Output Clock Duty Cycle tCLK-Q Figure 3 -150 45 50 100 µs 100 µs 2500 ppm +150 ps 55 % _______________________________________________________________________________________ 3 MAX3953 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at +3.3V and TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL Output Clock and Data Rise/Fall Time tR, tF CONDITIONS MIN 20% to 80% TYP 100 MAX UNITS 250 ps LVDS Differential Skew tSKEW1 Any differential pair 50 ps LVDS Channel-to-Channel Skew tSKEW2 PDO[15..0]± 100 ps Note 2: Guaranteed by design and characterization for TA = 0°C to +85°C. Note 3: Measured with 0.45UIP-P deterministic jitter and 0.15UIP-P random jitter, on top of the specified sinusoidal jitter in a 231 - 1 PRBS pattern with a BER = 10-12. Note 4: The jitter tolerance exceeds IEEE 802.3AE specifications. The jitter tolerance outperforms the instrument’s measurement capability. Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE 570 510 480 450 +3.3V 420 +3.0V 390 -50 0 5000 10,000 FREQUENCY (kHz) 4 40 15,000 20,000 60 80 18.0 100 19.5 20.0 20.5 JITTER TOLERANCE JITTER GENERATION vs. POWER-SUPPLY FREQUENCY 100 5 JITTER GENERATION (psRMS) MEASURED WITH 0.45UI DETERMINISTIC JITTER AND 0.15UI RANDOM JITTER 1000 JITTER FREQUENCY (kHz) 10,000 21.0 6 MAX3953 toc05 10Gbps ETHERNET JITTER TOLERANCE 10 19.0 INPUT VOLTAGE (mVP-P) 1 0.1 18.5 TEMPERATURE (°C) 0.01 -60 10-9 10-12 20 10 SINUSOIDAL INPUT JITTER (UIP-P) MAX3953 toc04 -40 10-8 10-11 DIFFERENTIAL S11 vs. FREQUENCY -30 10-7 330 0 -20 10-6 360 300 -10 10-5 10-10 500ps/div 0 10-4 MAX3953 toc06 DATA +3.6V BIT-ERROR RATIO SUPPLY CURRENT (mA) 540 10-3 MAX3953 toc02 600 MAX3953 toc01 CLOCK BIT-ERROR RATIO vs. INPUT VOLTAGE MAX3953 toc03 RECOVERED DATA AND CLOCK (0.3Gbps INPUT) S11 (dB) MAX3953 10Gbps 1:16 Deserializer with Clock Recovery 4 3 2 100mVP-P SINUSOID ON VCC WIDEBAND JITTER GENERATION OF PCLKO AT 622MHz 1 0 0 5000 10,000 15,000 20,000 POWER-SUPPLY FREQUENCY (kHz) _______________________________________________________________________________________ 25,000 10Gbps 1:16 Deserializer with Clock Recovery PIN NAME FUNCTION 1, 4, 5, 6, 14, 17, 18, 34, 35, 51, 52, 60, 68 GND 2 REFCLK+ Positive Reference Clock Input, LVPECL. Connect a baud rate/64 or baud rate/16 reference clock. 3 REFCLK- Negative Reference Clock Input, LVPECL. Connect a baud rate/64 or baud rate/16 reference clock. 7 REFSET Reference Clock Select Input, TTL. When the reference clock is baud rate/64, set REFSET to GND. When the reference clock is baud rate/16, set REFSET to VCC. 8, 11, 12, 13, 15, 16, 27, 42, 59, 66 VCC +3.3V Supply Voltage 9 SDI+ Positive Serial Data Input, CML. 9.953Gbps/10.3125Gbps serial data stream. 10 SDI- Negative Serial Data Input, CML. 9.953Gbps/10.3125Gbps serial data stream. 19 LOS_IN 20 LOL 21 PCLKO+ Positive Parallel Clock Output, LVDS 22 PCLKO- Negative Parallel Clock Output, LVDS 23, 25, 28, 30, 32, 36, 38, 40, 43, 45, 47, 53, 55, 57, 61, 63 PDO15+ to PDO0+ Positive Parallel Data Outputs, LVDS 24, 26, 29, 31, 33, 37, 39, 41, 44, 46, 48, 54, 56, 58, 62, 64 PDO15to PDO0- Negative Parallel Data Outputs, LVDS 49 SYNC_ERR Synchronization Error Output, TTL. SYNC_ERR is intended to drive CLKSEL for holdover mode. See the Clock Holdover Mode section. 50 CLKSEL Output Clock Selector, TTL. CLKSEL is the control input for clock holdover. When CLKSEL = GND, PCLKO is derived from the input data. When CLKSEL = VCC, PCLKO is derived from the reference clock. 65 RATESET Serial Data Rate Select Input, TTL. When the input serial data stream is 9.953Gbps, set RATESET to GND. When the input serial data stream is 10.312Gbps, set RATESET to VCC. 67 FIL EP Exposed Pad Ground Loss-of-Signal Input, TTL. The LOS_IN is an external input. Clock holdover is activated when LOS_IN is TTL low. Connect to VCC if LOS input is not available. See the Clock Holdover Mode section. Loss-of-Lock Indicator Output, TTL. LOL signals a TTL low when the VCO frequency is more than 1000ppm from the reference clock frequency. LOL signals a TTL high when the VCO frequency is within 500ppm of the reference clock frequency. See the Clock Holdover Mode section. PLL Loop Filter Capacitor Input. A capacitor between this pin and VCC sets the loop to zero. A 0.047µF capacitor is recommended. Ground. This must be soldered to the circuit board ground for proper thermal and electrical performance. See the Layout Considerations section. _______________________________________________________________________________________ 5 MAX3953 Pin Description MAX3953 10Gbps 1:16 Deserializer with Clock Recovery Detailed Description The MAX3953 deserializer with clock recovery converts 9.953Gbps/10.3125Gbps serial data into 16-bit wide, 622Mbps/644Mbps parallel data. The device combines a fully integrated phase-locked loop (PLL), TTL-compatible status monitors, input amplifier, data retiming block, 16-bit demultiplexer, clock dividers, and LVDS output buffers. The PLL consists of a phase/frequency detector (PFD), a loop filter, and voltage-controlled oscillator (VCO). The PLL recovers the serial clock from the input data stream and retimes the data. The demultiplexer generates a 16-bit-wide 622Mbps/644Mbps parallel data output. The MAX3953 is designed to deliver the best jitter performance by using differential signal architecture and low-noise design techniques. Input Amplifier The serial data input (SDI) amplifier accepts differential input amplitudes from 100mVP-P to 1200mVP-P. Phase-Frequency Detector The digital phase-frequency detector (PFD) aids frequency acquisition during startup conditions. Depending on the polarity of the frequency input difference between REFCLK and the VCO clock, the PFD drives the VCO until the frequency difference is reduced to zero. False locking is eliminated by this digital phase-frequency detector. The data phase detector is optimized to achieve 0.75UI high-frequency jitter tolerance. Loop Filter and VCO The phase detector and frequency detector outputs are summed into the loop filter. A 0.047µF capacitor (CF) is required to set the PLL damping ratio. The loop filter output controls the on-chip VCO. Loss-of-Lock Monitor A loss-of-lock (LOL) monitor is included in the MAX3953 frequency detector. A loss-of-lock condition is signaled with a TTL low. When the PLL is frequency locked, LOL switches to TTL high in approximately 56µs. LOL signals a TTL low when the VCO frequency is more than 1000ppm from the reference clock frequency. LOL signals a TTL high when the VCO frequency is within 500ppm of the reference clock frequency. Applications Information Clock Holdover Mode The clock holdover mode is designed to provide an accurate parallel clock in the event of a loss-of-lock (LOL) or loss-of-signal (LOS) condition. The activation of the holdover mode is controlled by the SYNC_ERR, LOS_IN, and CLKSEL pins. CLKSEL is an input signal used to select the VCO to lock on to the incoming data (SDI) or the reference clock (REFCLK). The architecture of the holdover mode is shown in Figure 4. Holdover mode is activated by connecting SYNC_ERR to CLKSEL. Consecutive Identical Digits (CIDs) The MAX3953 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 ✕ 10-12. The CID tolerance is tested using a 213 - 1 pseudorandom bit stream (PRBS), substituting a long run of zeros to simulate worst case. A CID tolerance of greater than 2,000 bits is typical. Exposed-Pad Package The exposed pad, 68-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3953 and should be soldered to the circuit board for proper thermal and electrical performance. See Maxim Application Note HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for further information. Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3953 high-speed inputs and outputs. Power-supply decoupling should be placed as close to the VCC as possible. To reduce feed-through, isolate input signals from output signals. Low-Voltage Differential Signal (LVDS) Outputs The MAX3953 features LVDS outputs for interfacing with high-speed circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 500mVP-P to 800mVP-P differential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity. 6 _______________________________________________________________________________________ 10Gbps 1:16 Deserializer with Clock Recovery 50mV 600mV VCC - 0.3V 231 - 1 PRBS 231 - 1 PRBS INPUT DATA VCC - 0.6V (a) DC-COUPLED CML INPUT PLL ACQUISITION TIME LOL ASSERT TIME VCC + 0.3V LOL OUTPUT 600mV VCC 50mV VCC - 0.3V (b) AC-COUPLED CML INPUT Figure 2. LOL Assert and Acquisition Time Figure 1. Input Amplitude REFCLK tCLK VCO PFD LOL STATE MACHINE LOS_IN PCLK+ LOL SYNC_ERR CLKSEL tCLK-Q REFCLK PDO MAX3953 SDI PLL Figure 3. Timing Parameters Figure 4. Clock Holdover Architecture _______________________________________________________________________________________ 7 MAX3953 VCC 10Gbps 1:16 Deserializer with Clock Recovery MAX3953 Functional Diagram CLKSEL LOL SYNC_ERR TTL TTL TTL LOS_IN TTL HOLDOVER STATE MACHINE PCLKO+ DIV 16 LVDS PCLKO- REFCLK+ PECL DIV N PDO15+ REFCLK- REFSET PHASE AND FREQUENCY DETECTOR TTL LOOP FILTER LVDS VCO PDO15- 16-BIT DEMULTIPLEXER Q PDO1+ LVDS PDO1- SDI+ CML D SDI- PDO0+ LVDS PDO0- MAX3953 FIL 8 _______________________________________________________________________________________ 10Gbps 1:16 Deserializer with Clock Recovery GND PDO4+ PDO4- PDO3+ PDO2+ PDO3- PDO2- VCC GND PDO1+ PDO1- 67 66 65 64 PDO0+ PDO0- 68 VCC FIL RATESET GND TOP VIEW 63 62 61 60 59 58 57 56 55 54 53 52 GND 1 51 GND REFCLK+ 2 50 CLKSEL REFCLK- 3 49 SYNC_ERR GND 4 48 PDO5- GND 5 47 PDO5+ GND REFSET 6 46 PDO6- 7 45 PDO6+ VCC 8 SDI+ 9 44 PDO7- MAX3953 43 PDO7+ SDI- 10 42 VCC VCC 11 41 PDO8- VCC 12 40 PDO8+ VCC 13 39 PDO9- GND 14 38 PDO9+ VCC 15 37 PDO10- VCC 16 36 PDO10+ GND 17 35 GND GND PDO11- PDO12- PDO11+ PDO12+ PDO13- PDO13+ VCC PDO14- PDO14+ PDO15- PCLKO- PDO15+ PCLKO+ LOL GND LOS_IN 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 QFN* *THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION. Chip Information TRANSISTOR COUNT: 11,612 PROCESS: SiGe BIPOLAR _______________________________________________________________________________________ 9 MAX3953 Pin Configuration Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 68L QFN, 10x10x09,EPS MAX3953 10Gbps 1:16 Deserializer with Clock Recovery Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.