19-1431; Rev 4; 6/05 Direct-Conversion Tuner IC for Digital DBS Applications Features ♦ Low-Cost Architecture The MAX2104 low-cost direct-conversion tuner IC is designed for use in digital direct-broadcast satellite (DBS) television set-top box units. Its direct-conversion architecture reduces system cost compared to devices with IF-based architectures. The MAX2104 directly converts L-band signals to baseband signals using a broadband I/Q downconverter. The operating frequency range extends from 925MHz to 2175MHz. The IC includes an LNA gain control, I and Q downconverting mixers, lowpass filters with gain control and frequency control, a local oscillator (LO) buffer with a 90° quadrature network, and a charge-pump based PLL for frequency control. The MAX2104 also has an on-chip LO, requiring only an external varactor-tuned LC tank for operation. The output of the LO drives the internal quadrature generator and dual modulus prescaler. An on-chip crystal amplifier drives a reference divider as well as a buffer amplifier to drive off-chip circuitry. The MAX2104 is offered in a 48-pin TQFP-EP package. ♦ Operates from Single 5V Supply ♦ 925MHz to 2175MHz Input Frequency Range ♦ On-Chip Quadrature Generator, Dual-Modulus Prescaler (/32, /33) ♦ On-Chip Crystal Amplifier ♦ PLL Mixer with Gain-Controlled Charge Pump ♦ Input Levels: -25dBm to -65dBm per Carrier ♦ Over 40dB Gain Control Range ♦ Noise Figure = 11.5dB; IIP3 = 7dBm (at 1550MHz) ♦ Automatic Baseband Offset Correction ♦ Loopthrough Replaces External Splitter ♦ Crystal Output Buffer Ordering Information Applications DirecTV, PrimeStar, EchoStar DBS Tuners DVB-Compliant DBS Tuners Broadband Systems LMDS PINPACKAGE PKG CODE PART TEMP RANGE MAX2104CCM* 0°C to +70°C 48 TQFP-EP** C48E-10 MAX2104CCM+ 0°C to +70°C 48 TQFP-EP** C48E-10 *Contact factory for availability. **EP = Exposed paddle. +Denotes lead-free package. Functional Diagram appears at end of data sheet. 37 38 GND VCC PSOUTPSOUT+ 39 40 41 42 TANK+ VRLO TANKGND 44 43 GND VCC 46 45 CP FB 47 TOP VIEW 48 Pin Configuration VCC 1 36 CFLT XTL- 2 35 XTL+ GND VCC RFINRFIN+ GND GND QDCQDC+ 4 33 5 32 EP 3 6 34 31 MAX2104 7 30 24 23 MODMOD+ GND IOUT+ IOUTVCC QOUT+ QOUTFDOUB FLCLK GC2 INSEL 22 21 19 20 XTLOUT CPG2 GC1 18 17 16 25 15 26 12 14 27 11 13 28 10 IDC- 29 9 IDC+ GND GND RFOUT CPG1 VCC 8 PLLINPLLIN+ TQFP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX2104 General Description MAX2104 Direct-Conversion Tuner IC for Digital DBS Applications ABSOLUTE MAXIMUM RATINGS VCC to GND .............................................................-0.5V to +7V All Other Pins to GND.................................-0.3V to (VCC + 0.3V) RF1+ to RF1-, RF2+ to RF2-, TANK+ to TANK-, IDC+ to IDC-, QDC+ to QDC- ............................................±2V IOUT_, QOUT_ to GND Short-Circuit Duration ......................10s PSOUT+, PSOUT- to GND Short-Circuit Duration .................10s Continuous Current (any pin)..............................................20mA Continuous Power Dissipation (TA = +70°C) (derate 30.4mW/°C above +70°C) ..................................2.43W Operating Temperature Range...............................0°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 4.75V to 5.25V, VFB = 2.4V, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RFIN_ = floating, RIOUT_ = RQOUT_ = 10kΩ, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25°C. Typical values are at VCC = 5.0V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Operating Supply Voltage VCC Operating Supply Current ICC CONDITIONS MIN TYP 4.75 190 MAX UNITS 5.25 V 275 mA STANDARD DIGITAL INPUTS (FDOUB, INSEL, CPG1, CPG2) Digital Input Voltage High VIH Digital Input Voltage Low VIL Digital Input Current IIN 2.4 V -15 0.5 V +10 µA SLEW-RATE-LIMITED DIGITAL INPUTS FLCLK Input Voltage High 1.85 V FLCLK Input Voltage Low FLCLK Input Current (Note 1) RSOURCE = 50kΩ, VFLCLK = 1.65V -1 1.45 V +1 µA DIFFERENTIAL DIGITAL INPUTS (MOD+, MOD-, PLLIN+, PLLIN-) Common-Mode Input Voltage VCMI 1.08 Input Voltage Low (Note 2) Referenced to VCMI Input Voltage High (Note 2) Referenced to VCMI 1.2 V mV 100 mV -5 Input Current (Note 1) 1.32 -100 5 µA 2.4 2.64 V -215 -150 mV DIFFERENTIAL DIGITAL OUTPUTS (PSOUT+, PSOUT-) Common-Mode Output Voltage VCMO 2.16 Output Voltage Low (Note 3) Referenced to VCMO Output Voltage High (Note 3) Referenced to VCMO 150 (VMOD+ - VMOD-) = 200mV 32 32 (VMOD+ - VMOD-) = -200mV 33 33 8 8 215 mV FREQUENCY SYNTHESIZER Prescaler Ratio Reference Divider Ratio Charge-Pump Output High Measured at FB 2 VCPG1 = VCPG2 = 0.5V 0.08 0.1 0.12 VCPG1 = 0.5V, VCPG2 = 2.4V 0.24 0.3 0.36 VCPG1 = 2.4V, VCPG2 = 0.5V 0.48 0.6 0.72 VCPG1 = VCPG2 = 2.4V 1.44 1.8 2.16 _______________________________________________________________________________________ mA Direct-Conversion Tuner IC for Digital DBS Applications (VCC = 4.75V to 5.25V, VFB = 2.4V, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RFIN_ = floating, RIOUT_ = RQOUT_ = 10kΩ, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25°C. Typical values are at VCC = 5.0V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -0.12 -0.36 -0.72 -2.16 -0.1 -0.3 -0.6 -1.8 -0.08 -0.24 -0.48 -1.44 mA Charge-Pump Output Low Measured at FB VCPG1 = VCPG2 = 0.5V VCPG1 = 0.5V, VCPG2 = 2.4V VCPG1 = 2.4V, VCPG2 = 0.5V VCPG1 = VCPG2 = 2.4V Charge-Pump Output Current Matching Positive to Negative Measured at FB -5 5 % Charge-Pump Output Leakage Measured at FB -25 25 nA Charge-Pump Output Current Drive (Note 1) Measured at CP 100 VGC_ = 1V to 4V -50 µA ANALOG CONTROL INPUTS (GC_) Analog Control Input Current IGC_ +50 µA BASEBAND OUTPUTS (IOUT+, IOUT-, QOUT+, QOUT-) Differential Output Voltage Swing RL = 2kΩ differential 1 VP-P Common-Mode Output Voltage (Note 1) 0.65 0.85 V Offset Voltage (Note 1) -50 +50 mV AC ELECTRICAL CHARACTERISTICS (VCC = 4.75V to 5.25V, VIOUT_ = VQOUT_ = 0.59VP-P, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RIOUT_ = RQOUT_ = 10kΩ, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25°C. Typical values are at VCC = 5.0V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2175 MHz -65 dBm RF FRONT END RFIN_ Input Frequency Range fRFIN 925 VGC1 = VGC2 = +4V (min gain) -20 VGC1 = VGC2 = +1V (max gain) -68 RFIN_ Input Power for 0.59Vp-p Baseband Levels Single carrier RFIN_ Input Third-Order Intercept (Note 4) fLO = 2175MHz PRFIN_ = -25dBm per fLO = 1550MHz tone fLO = 950MHz IP3RFIN_ RFIN_ Input Second-Order Intercept (Note 5) IP2RFIN_ Output-Referred 1dB Compression Point (Note 6) P1dBOUT_ Noise Figure NF RFIN_ Return Loss (Note 7) dBm 5 7 dBm 8 PRFIN_ = -25dBm per tone, fLO = 951MHz PRFIN_ = -40dBm, signals within filter bandwidth PRFIN_ = -65dBm, fRFIN_ = 1550MHz, VGC1 = 1V, VGC2 adjusted 0.59Vp-p baseband level 15.5 dBm 2 dBV 11.5 dB fRFIN_ = 925MHz 10 fRFIN_ = 2175MHz 10 LO 2nd Harmonic Rejection (Note 8) Average level of VIOUT_, VQOUT_ 27 LO Half Harmonic Rejection (Note 9) Average level of VIOUT_, VQOUT_ 31 dB dBc 38 dBc _______________________________________________________________________________________ 3 MAX2104 DC ELECTRICAL CHARACTERISTICS (continued) MAX2104 Direct-Conversion Tuner IC for Digital DBS Applications AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 4.75V to 5.25V, VIOUT_ = VQOUT_ = 0.59VP-P, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RIOUT_ = RQOUT_ = 10kΩ, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25°C. Typical values are at VCC = 5.0V and TA = +25°C, unless otherwise noted.) PARAMETER LO Leakage Power (Notes 7, 10) SYMBOL CONDITIONS MIN TYP Measured at RFIN_ -66 f = 925MHz 0.5 f = 1550MHz 1.8 f = 2175MHz 2.5 MAX UNITS dBm RFOUT PORT (LOOPTHROUGH) RFIN_ to RFOUT Gain (Note 11) RFOUT Output Third-Order Intercept Point (Note 11) RFOUT Noise Figure (Note 11) RFOUT Return Loss (Notes 1, 11) f = 925MHz 9 f = 1550MHz 7 f = 2175MHz 4 f = 925MHz 15 f = 1550MHz 12 f = 2175MHz 11.5 dB dBm dB 925MHz < f < 2175MHz 8 dB Output Real Impedance (Note 1) IOUT_, QOUT_ 50 Ω Baseband Highpass Frequency (Note 1) CIDC_ = CQDC_ = 0.22µF 750 Hz LPF -3dB Cutoff-Frequency Range (Note 1) Controlled by FLCLK signal 8 33 MHz Baseband Frequency Response (Note 1) Deviation from ideal 7th order, Butterworth, up to 0.7 x fC -0.5 +0.5 dB fFLCLK = 0.5MHz, fC = 8MHz -5.5 +5.5 fFLCLK = 1.25MHz, fC = 19.3MHz -10 +10 fFLCLK = 2.0625MHz, fC = 31.4MHz -10 +10 BASEBAND CIRCUITS LPF -3dB Cutoff-Frequency Accuracy (Note 1) % Ratio of In-Filter-Band to Out-of-Filter-Band Noise fIN_BAND = 100Hz to 22.5MHz, fOUT_BAND = 67.5MHz to 112.5MHz Quadrature Gain Error Includes effects from baseband filters, measured at 125kHz baseband 1.2 dB Quadrature Phase Error Includes effects from baseband filters, measured at 125kHz baseband 4 degrees 4 19 _______________________________________________________________________________________ dB Direct-Conversion Tuner IC for Digital DBS Applications (VCC = 4.75V to 5.25V, VIOUT_ = VQOUT_ = 0.59VP-P, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RIOUT_ = RQOUT_ = 10kΩ, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25°C. Typical values are at VCC = 5.0V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 1.5 VP-P 7.26 MHz SYNTHESIZER SYNTHESIZER XTLOUT Output Voltage Swing Load = 10pF | | 10kΩ, fXTLOUT = 6MHz 0.75 XTLOUT Output Voltage DC 2 Crystal Frequency Range (Note 1) 4 V MOD+, MOD- Setup Time (Note 1) tSUM Figure 1 7 ns MOD+, MOD- Hold Time (Note 1) tHM Figure 1 0 ns LOCAL LOCAL OSCILLATOR OSCILLATOR LO Tuning Range (Note 1) LO Phase Noise (Notes 7, 12) RFIN_ to LO Input Isolation (Note 10) 590 1180 At 1kHz offset, fLO = 2175MHz -55 At 10kHz offset, fLO = 2175MHz -75 At 100kHz offset, fLO = 2175MHz -95 fRFIN_ = 2150MHz 57 MHz dBc/Hz dB Minimum and maximum values are guaranteed by design and characterization over supply voltage. With external 100Ω termination resistor. Driving differential load of 10kΩ || 15pF. Two signals are applied to RFIN_ at fLO - 100MHz and fLO - 199MHz. VGC2 = 1V; VGC1 is set such that the baseband outputs are at 590mVP-P. IM products are measured at baseband outputs but are referred to RF inputs. Note 5: Two signals are applied to RFIN_ at 1200MHz and 2150MHz. VGC2 = 1V, VGC1 is set such that the baseband outputs are at 590mVP-P. IM products are measured at baseband outputs but are referred to RF inputs. Note 6: PRFIN_ = -40dBm so that front end IM contributions are minimized. Note 7: Using L64733/L64734 demo board from LSI Logic. Note 8: Downconverted level, in dBc, of carrier present at fLO x 2, fLO = 1180MHz, fVCO = 590MHz, VFDOUB = 2.4V. Note 9: Downconverted level, in dBc, of carrier present at fO / 2, fLO = 2175MHz, fVCO = 1087.5MHz, VFDOUB = 2.4V. Note 10: Leakage is dominated by board parasitics. Note 11: VCPG1 = VCPG2 = VFDOUB = VINSEL = 0.5V, fFLCLK = 0.5MHz. Note 12: Measured at tuned frequency with PLL locked. All phase noise measurements assume tank components have a Q > 50. Note 1: Note 2: Note 3: Note 4: _______________________________________________________________________________________ 5 MAX2104 AC ELECTRICAL CHARACTERISTICS (continued) Direct-Conversion Tuner IC for Digital DBS Applications MAX2104 Pin Description 6 PIN NAME FUNCTION 1, 6, 19, 29, 39, 45 VCC VCC Power-Supply Input. Connect each pin to a +5V ±5% low-noise supply. Bypass each VCC pin to the nearest GND with a ceramic chip capacitor. 2 CFLT External Bypass for Internal Bias. Bypass this pin with a 0.1µF ceramic chip capacitor to GND. 3 XTL- Inverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements. 4 XTL+ Noninverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements. 5, 9, 10, 15, 16, 32, 40, 41, 46 GND Ground. Connect each of these pins to a solid ground plane. Use multiple vias to reduce inductance where possible. 7 RFIN- RF Inverting Input. Bypass RFIN- with 47pF capacitor in series with a 75Ω resistor to GND. 8 RFIN+ RF Noninverting Input. Connect to 75Ω source with a 47pF ceramic chip capacitor. 11 QDC- Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from QDC- to QDC+ (pin 12). 12 QDC+ Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from QDC+ to QDC- (pin 11). 13 IDC- Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from IDC- to IDC+ (pin 14). 14 IDC+ Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from IDC+ to IDC- (pin 13). 17 RFOUT 18 CPG1 20 XTLOUT 21 CPG2 Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See the DC Electrical Characteristics section for available gain settings. 22 GC1 Gain Control Input for RF Front End. High-impedance analog input, with an input range of 1V to 4V. See the AC Electrical Characteristics section for transfer function. 23 GC2 Gain Control Input for Baseband Signals. High-impedance analog input, with an input range of 1V to 4V. See the AC Electrical Characteristics section for transfer function. 24 INSEL Loopthrough Mode Enable. High-impedance digital input. Drive low to enable the RFOUT buffer and disable the internal downconverters. Connect to VCC for normal tuner operation. 25 FLCLK Baseband Filter Cutoff Adjust. Connect to a slew-rate-limited clock source. See the AC Electrical Characteristics section for transfer function. 26 FDOUB LO Frequency Doubler. High-impedance digital input. Drive high to enable the LO frequency doubler. Drive low to disable the doubling function. 27 QOUT- Baseband Quadrature Output. Connect to inverting input of high-speed ADC. 28 QOUT+ Baseband Quadrature Output. Connect to noninverting input of high-speed ADC. Buffered RF Output. Enabled when INSEL is low. Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See the DC Electrical Characteristics section for available gain settings. Buffered Crystal Oscillator Output 30 IOUT- Baseband In-Phase Output. Connect to inverting input of high-speed ADC. 31 IOUT+ Baseband In-Phase Output. Connect to noninverting input of high-speed ADC. 33 MOD+ PECL Modulus Control. A PECL high on MOD+ sets the dual-modulus prescaler to divide by 32. A PECL logic low sets the divide ratio to 33. Drive with a differential PECL signal with MOD- (pin 34). _______________________________________________________________________________________ Direct-Conversion Tuner IC for Digital DBS Applications PIN NAME FUNCTION 34 MOD- PECL Modulus Control. A PECL low on MOD- sets the dual-modulus prescaler to divide by 32. A PECL logic high sets the divide ratio to 33. Drive with a differential PECL signal with MOD+ (pin 33). 35 PLLIN+ PECL Phase-Locked Loop Input. Drive with a differential PECL signal with PLLIN- (pin 36). 36 PLLIN- PECL Phase-Locked Loop Input. Drive with a differential PECL signal with PLLIN+ (pin 35). 37 PSOUT+ PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used with PSOUT- (pin 38). Requires PECL-compatible termination. 38 PSOUT- PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used with PSOUT+ (pin 37). Requires PECL-compatible termination. 42 TANK- LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning. 43 VRLO LO Internal Regulator. Bypass with a 100pF ceramic chip capacitor to GND. 44 TANK+ LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning. 47 FB Feedback Output. Control of external charge-pump transistor. 48 CP Voltage Drive Output. Control of external charge-pump transistor. — EP Exposed Paddle. Connect EP to GND. MOD+, MOD- 50% tSUM 50% tHM PSOUT+ 50% PSOUT- 50% Figure 1. Timing Diagram _______________________________________________________________________________________ 7 MAX2104 Pin Description (continued) Direct-Conversion Tuner IC for Digital DBS Applications MAX2104 Functional Diagram CPG1 CPG2 PLLIN+ MAX2104 CHARGE PUMP PLLIN- CP FB /8 XTL+ XTLOUT XTLMOD+ MODFDOUB TANK+ x2 TANKVCC VRLO VOLTAGE REGULATOR RFIN+ GC1 PSOUTBASEBAND OFFSET CORRECTION IDC+ IDCQDC+ QDCIOUT+ CFLT GND RFIN- PSOUT+ /32, 33 IOUT0°/90° QOUT+ QOUT- GC2 FLCLK RFOUT INSEL 8 _______________________________________________________________________________________ Direct-Conversion Tuner IC for Digital DBS Applications 48L,TQFP.EPS PACKAGE OUTLINE, 48L TQFP, 7x7x1.0mm EP OPTION 21-0065 G 1 2 PACKAGE OUTLINE, 48L TQFP, 7x7x1.0mm EP OPTION 21-0065 G 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 9 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX2104 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)