STV7622
192 output plasma display panel data driver
Preliminary Data
Features
■
192 high-voltage outputs
■
Output pad placements: I-shape
■
The input data bus is configured by dedicated
input pins:
●
BS1 and BS2: bus width select (3, 6,
2 × 3 bits or RSDS mode)
90V absolute maximum supply
●
DIR input: shift register loading direction
■
EMI control features:
– SmartSlope
– ConstantSlope
– Spread Spectrum Jitter (SSJ)
The STV7622 output stage integrates several ST
patented functions aimed at reducing EMI without
compromising addressing speed or performance
of the PDP modules.
■
Configurable data bus:
– 3, 6 or 2 × 3 bits
– TTL and LVCMOS compatible
– RSDS mode
– Single- or dual-edge clocking mode
– 60MHz clock frequency
These functions mainly consist of:
●
SmartSlope: controls the output falling edge
speed /shape
●
ConstantSlope: controls the output rising
edge speed
●
Spread Spectrum Jitter (SSJ): controls the
spread of the output rising edge
■
3.3/5V CMOS logic compatible
■
- 60/+24mA source/sink output current
capability
■
BCD Process
The STV7622 is powered by a separate 70V
supply for the high-voltage outputs and a 5V
supply for the logic. All command input levels are
5V CMOS as well as 3.3V compatible.
■
Packaging according to customer request:
wafer, die, bumped die/wafer, TCP or COF
Figure 1.
Block diagram
BS1 BS2
DIR
CLK1
CLK2
VDD
Description
VSSLOG
32-bit Shift register
DB2
It controls up to 192 outputs via an input data bus
(3, 6 or 2 × 3-bits wide) operating at up to 60MHz.
This large number of outputs reduces the number
of connections between the controller board and
the data driver ICs.
DB6
3/6/2x3-bit & RSDS
selection
The STV7622 is a data driver for Plasma Display
Panels (PDP) designed in the ST’s proprietary
BCD high-voltage technology.
Shift register direction
DB1
DB3
DB4
DB5
32-bit Shift register
32-bit Shift register
32-bit Shift register
TEST1
32-bit Shift register
TEST2
32-bit Shift register
VREF
Data decoding
10nF
/STB1
Q1 Q2 Q3 Q4
Latch
Q192
/STB2
VCC
RS1
RS2
FS1
FS2
/BLK
The STV7622 contains a new logic input stage
that minimizes EMI resulting from the
transmission of high speed TTL or LVCMOS data
and clock signals. This new input stage is RSDS
compliant. It enables increasing the operating
frequency without compromising noise immunity.
May 2007
Output control / EMI control
POC
VPP
VSSP
Output buffer stage
VSSSUB
OUT1
OUT2
OUT3 …..
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
…. OUT192
1/32
www.st.com
32
Contents
STV7622
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Output stage description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1
Data input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.2
3 x 64-bit data bus, standard transmission (BS1 = H, BS2 = L) . . . . . . . . . 8
5.3
6 x 32-bit data bus, standard transmission (BS1 = L, BS2 = L) . . . . . . . . . 8
5.4
2 x 3 x 32-bit data bus, standard transmission (BS1 = H, BS2 = H) . . . . . 9
5.5
Differential transmission mode: RSDS (BS1 = L, BS2 = H) . . . . . . . . . . . 10
5.6
Power output block and EMI control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
AC timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11
Pad dimensions and positions (in µm) . . . . . . . . . . . . . . . . . . . . . . . . . 22
12
Tested wafer disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
STV7622
Block diagram
1
Block diagram
Figure 2.
STV7622 block diagram
BS1 BS2
DIR
CLK1
CLK2
VDD
VSSLOG
32-bit Shift register
3/6/2x3-bit & RSDS
selection
Shift register direction
DB1
DB2
DB3
DB4
DB5
32-bit Shift register
32-bit Shift register
32-bit Shift register
TEST1
32-bit Shift register
DB6
TEST2
32-bit Shift register
VREF
Data decoding
10nF
/STB1
Q1 Q2 Q3 Q4
Latch
Q192
/STB2
VCC
RS1
RS2
FS1
FS2
/BLK
Output control / EMI control
POC
VPP
VSSP
Output buffer stage
VSSSUB
OUT1
OUT2
OUT3 …..
…. OUT192
3/32
Pin description
STV7622
2
Pin description
Table 1.
Pin description
Pin name
Function
Description
VPP
Supply
DC high-voltage supply of power outputs
VCC
Supply
Analog 5V supply
VDD
Supply
Digital 5V supply
VSSP
Ground
Ground for power outputs
VSSSUB
Ground
Substrate ground
VSSLOG
Ground
Ground for 5V logic
OUT1 to OUT192
Outputs
Power outputs
DB1to DB6
Inputs
Shift register inputs
/BLK
Input
Blanking input
POC
Input
Power output control input
DIR
Input
Selection of shift register direction
BS1 and BS2
Inputs
Shift register configuration pins (3/6/2 × 3-bits and RSDS selection)
CLK1 and CLK2
Inputs
Clock for data shift register
/STB1 and /STB2
Inputs
Latch of data to power outputs
RS1 and RS2
Inputs
Output rise time selection pins
FS1 and FS2
Inputs
Output “slow-slope” fall time selection pins
TEST1
Test pin
Must be grounded
TEST2
Test pin
Must be grounded
VREF
Input
Note:
4/32
Filter for internal reference - must be connected to ground via a 10nF
capacitor
Inputs /BLK, /STB1 and /STB2 are active Low.
STV7622
Output stage description
3
Output stage description
Figure 3.
Output stage description
VCC
VPP
VCC
Totem
pole
T3
to 192
Rise time
RS1/RS2
Output 1
Output stage
T1
OUTn
Fall time
FS1/FS2
Rising edge
control
Falling edge
control
Delay
T2
T4
Output control
VSSP
5/32
Pinout description
Pinout description
Figure 4.
Pinout diagram
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT192
OUT191
OUT190
OUT189
OUT188
OUT187
OUT186
OUT185
OUT184
OUT183
OUT182
OUT181
OUT180
4
STV7622
VSSP1
VSSP4
VSSP2
VSSP3
VSSP5
VSSP6
Y
VPP4
VPP1
VPP5
VPP2
0/0
VPP3
X
VPP6
DUMMY
DUMMY
VSSLOG2
VSSLOG1
VSSSUB2
VSSSUB1
VDD2
VCC2
VCC1
DUMMY
DB6
DB5
DB4
DB3
DB2
DB1
/STB2
/STB1
CLK2
CLK1
VDD3
/BLK
VSSLOG3
POC
VDD4
DUMMY
DUMMY
VREF
DUMMY
VSSLOG4
RS1
VDD5
RS2
VSSLOG5
FS2
VDD6
FS1
VSSLOG6
DIR
VDD7
BS1
VSSLOG7
BS2
VDD8
TEST1
TEST2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VDD1
In the pinout diagram of Figure 4 above:
6/32
●
VDD1 to VDD8 are internally connected. It is not necessary to connect them together
on the tape carrier package (TCP) - the same applies to VCC1 and VCC2.
●
VSSLOG1 to VSSLOG2 are internally connected. It is not necessary to connect them
together on the TCP - the same for VSSSUB1 and VSSSUB2.
●
VSSLOG1 to VSSLOG7 are not internally connected to VSSSUB1 and VSSSUB2. We
recommend shorting them together very close to the die, either on the TCP or at the
TCP connector.
●
VDD1 to VDD8 are not internally connected to VCC1 and VCC2. For good test
coverage, they must not be shorted together on the TCP. In the application, VDD1 to
VDD8, VCC1 and VCC2 must be connected together at the TCP connector level.
●
TEST1 and TEST2 are used to test the device. For good test coverage, they must not
be shorted together on the TCP. In the application, TEST1 and TEST2 must be
grounded at the TCP connector level.
●
VREF must be connected to ground via a 10nF filter capacitor.
STV7622
5
Circuit description
Circuit description
The STV7622 includes all the logic and power circuits necessary to drive the column
electrodes of a Plasma Display Panel (PDP). A low-voltage logic block manages data
information, and a high-voltage block converts the low-voltage information stored in the logic
block into high-voltage signals applied to the display electrodes.
5.1
Data input block
The Data Bus is TTL- and LVCMOS-compatible and can also operate in an RSDS (Reduced
Swing Differential Signaling) mode. The maximum clock frequency is 60MHz.
The data input block consists of several shift registers operating in parallel to load the binary
values of the digital video. The number of cells in each shift register is defined by the BS pin
as described below in Table 2.
Table 2.
BS1/BS2 truth table
BS1
BS2
Shift register configuration
L
L
6 × 32 bits
H
L
3 × 64 bits
L
H
RSDS mode
H
H
2 × 3 × 32 bits (96 + 96)
For the 3 × 64 bit configuration, only pins DB1, DB2 and DB3 of the input data bus are used,
while for the 6 × 32 and 2 × 3 × 32 bit configurations all 6 bits of the input data bus input,
pins DB1 to DB6, are used.
The DIR input pin is used to select the shift register loading direction.
Data is shifted for each low-to-high transition of the clock signal (CLK1). The maximum
frequency of the clock is 60MHz, which is equivalent to a 360MHz serial shift register for a
6 × 32-bit arrangement.
When the /STB signal goes from high-to-low, data is transferred from the shift register to the
latch and to the power output stages. All output data is stored and held in the latch stage
when the latch input is pulled back High.
The core of the STV7622 is powered by 5V. All logic inputs can be driven either by 5V or
3.3V CMOS logic.
The tables in the following sections describe the position of the first data sampled by the first
rising edge of the CLK1 clock.
7/32
Circuit description
5.2
STV7622
3 x 64-bit data bus, standard transmission (BS1 = H, BS2 = L)
The data bus is in 3-bit mode (DB1 to DB3 active) for BS1 = H and BS2 = L.
Data on DB1 is sampled by the first clock pulse and shifted from position 1 to position 190
after 64 clock pulses. The data is then applied to output 190, on the high-to-low transition of
/STB.
Table 3.
3 x 64-bit data bus transmission
Clock pulse number
BS1
BS2
DIR
Input
Comment
Position
01
02
03
…
62
63
64
H
L
L
DB1
DB2
DB3
OUT
OUT
OUT
01
02
03
04
05
06
07
08
09
184
185
186
187
188
189
190
191
192
Left/Right
shift
H
L
H
DB1
DB2
DB3
OUT
OUT
OUT
190
191
192
187
188
189
184
185
186
07
08
09
04
05
06
01
02
03
Right/Left
shift
5.3
6 x 32-bit data bus, standard transmission (BS1 = L, BS2 = L)
The data bus is in 6-bit mode (DB1 to DB6 active) for BS1 = L and BS2 = L.
Table 4 below describes how data is shifted in the register.
Table 4.
6 x 32-bit data bus transmission
Position
BS1
BS2
DIR
01
02
03
…
30
31
32
Input
Comment
Clock pulse number
L
L
8/32
L
L
L
DB1
DB2
DB3
DB4
DB5
DB6
OUT
OUT
OUT
OUT
OUT
OUT
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
Left/Right
shift
H
DB1
DB2
DB3
DB4
DB5
DB6
OUT
OUT
OUT
OUT
OUT
OUT
187
188
189
190
191
192
181
182
183
184
185
186
175
176
177
178
179
180
13
14
15
16
17
18
07
08
09
10
11
12
01
02
03
04
05
06
Right/Left
shift
STV7622
Circuit description
5.4
2 x 3 x 32-bit data bus, standard transmission
(BS1 = H, BS2 = H)
The data bus is in 2 × 3-bit mode (DB1 to DB6 active) for BS1 = H and BS2 = H. Table 5
below describes how data is shifted in the register.
Table 5.
2 x 3 x 32-bit data bus transmission
Clock pulse number
BS1
H
H
BS2
H
H
DIR
Input
Comment
Position
01
02
03
L
DB1
DB2
DB3
DB4
DB5
DB6
OUT
OUT
OUT
OUT
OUT
OUT
01
02
03
97
98
99
04
05
06
100
101
102
H
DB1
DB2
DB3
DB4
DB5
DB6
OUT
OUT
OUT
OUT
OUT
OUT
94
95
96
190
191
192
91
92
93
187
188
189
…
30
31
32
07
08
09
103
104
105
88
89
90
184
185
186
91
92
93
187
188
189
94
95
96
190
191
192
Left/Right shift
88
89
90
184
185
186
07
08
09
103
104
105
04
05
06
100
101
102
01
02
03
97
98
99
Right/Left shift
9/32
Circuit description
5.5
STV7622
Differential transmission mode: RSDS (BS1 = L, BS2 = H)
In differential transmission mode, data is transmitted on two wires, one line transmits the
data value, the other the inverted data. The logic level of the data is determined by the
difference between data and inverted data. Two DB inputs are needed for the transmission
of 1 data value. The sampling clocks, CLK1 and CLK2, as well as strobes STB1/ and STB2
are also transmitted differentially. Data is sampled on the rising and falling edges of the
clock.
Table 6.
BS2
2 x 3 x 32-bit data bus transmission - differential mode
B12
DIR
Input
CLK1 clock pulse number
Position
01↑
01↓
02↑
01
04
02
DB5
DB6
DB1
DB2
DB1
DB2
H
H
L
L
L
H
DB3
DB4
DB3
DB4
OUT
OUT
DB5
DB6
…
Comment
31↓
32↑
32↓
07
184
187
190
05
08
185
188
191
03
06
09
186
189
192
190
187
184
07
04
01
191
188
185
08
05
02
192
189
186
09
06
03
Left/Right
shift
Right/Left
shift
In differential transmission operating mode, the biasing of the data input bus must be
carefully arranged to reduce static power consumption. In stand-by and non-active modes,
DB1, DB3, DB5, CLK1 and /STB1 should be set High to reduce bias current in the
differential input buffers.
For a High level, all differential pairs should be configured with DB1, DB3, DB5, CLK1 and
/STB1 High and with DB2, DB4, DB6, CLK2 and /STB2 Low.
When operating in differential transmission mode, a 100 ohm (1%) resistor termination must
be connected between:
●
DB1 and DB2
●
DB3 and DB4
●
DB5 and DB6
●
CLK1 and CLK2
●
STB1 and STB2
with each resistor placed as close as possible to the STV7622 itself.
10/32
STV7622
Differential input buffer - waveform timing
DB1-3-5
Differential
input buffer
100Ω
VID
DB2-4-6
VIA
VIB
(=DB1-3-5)
V0
1.4V
VIA
1.0V
VIB
0.4V
0
VID
0
-0.4V
tPHLD
tPLHD
90%
90%
OUTn
50%
10%
50%
10%
tFD
tRD
STLVD31
STLVD31
DB1-DB2
CLK1-CLK2
DB5-DB6
DB3-DB4
Data driver
board
DB1-DB2
STV7622
TCP
DB1-DB2
CLK1-CLK2
DB5-DB6
DB3-DB4
DB1-DB2
STV7622
TCP
STB1-STB2
CLK1-CLK2
DB5-DB6
DB3-DB4
STV7622
TCP
DB1-DB2
Figure 5.
Circuit description
STLVD31
Display controller
Video board
11/32
Circuit description
5.6
STV7622
Power output block and EMI control
The high-voltage output stage has a totem pole structure (see Figure 3). The capacitive load
is charged to Vpp by the high-side N-channel transistor, T1, and discharged to ground by
the low-side N-channel transistor, T2. The status of the power outputs can also be controlled
by the configuration pins, POC and /BLK, which can set the power outputs either all High or
all Low.
Several functions, patented by STMicroelectronics, are implemented in the STV7622 to
reduce EMI:
SmartSlope: The falling edge of the output pulse consist of 2 slopes (Figure 6 below): a
smooth slope followed by a steeper one (typically 4 times faster) The duration of the first
slope is set by two logic inputs, FS1 and FS2, according to the table in Figure 6.
Figure 6.
Output falling edge
tF-SLOW
90%
FS2
FS1
tF-SLOW
0
0
10ns
0
1
50ns
1
0
100ns
1
1
200ns
10%
tF-OUT
ConstantSlope: The duration of the output rising edge (Figure 7) is kept constant
independent of the value of the capacitive load connected to the output. This solution
minimizes the peak current in the power outputs as well as any oscillation phenomenon in
the power supplies. In addition, it reduces high-frequency components of the EMI spectrum
by suppressing very rapid rising edge transitions on the power outputs. The total duration of
the rising edge (tR-OUT) is set by another pair of logic inputs, RS1 and RS2, according to the
table in Figure 7 below.
RS2
RS1
tR-OUT
0
0
120ns
0
1
230ns
1
0
400ns
1
1
560ns
RS2=
0
Output rising edge
90%
RS1=
0
Figure 7.
RS
10%
tR-OUT
12/32
1
1=
1
2=
RS
STV7622
Circuit description
Spread Spectrum: To avoid having too large of a current in the driver during the rising edge
of the power outputs, all outputs are not triggered at the same time.
Instead, the STV7622 inserts a small delay between the rising edge of two consecutive
outputs. This delay depends on picture or image content (see Figure 8). For a dark picture,
we have tSSJ-MIN = 1 to 2ns (typ.) between output 1 and any output X, while for a white
picture, we have tSSJ-MAX = 100ns (typ.).
The SSJ function spreads the discharge current in the scan lines and, therefore, reduces
EMI by “spreading” the energy spectrum.
Figure 8.
Spread spectrum filter
OUT-1
OUT-x
tSSJ-MIN
Case #1: Dark picture
OUT-1
OUT-x
tSSJ-MAX
Case #2: White picture
13/32
Truth tables
STV7622
6
Truth tables
Table 7.
Shift register truth table
Input pins
BS2
BS1
DIR
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
H
L
L
H
L
L
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
Shift register function
CLK1
H or L
H or L
H or L
H or L
CLK2(1)
Q output
N.C.
Left/Right shift
DB1,2, …6 input pins, 6 × 32-bit mode
N.C.
Steady
N.C.
Right/Left shift
DB1,2, …6 input pins, 6 × 32-bit mode
N.C.
Steady
N.C.
Left/Right shift
DB1,2, 3 input pins, 3 × 64-bit mode
N.C.
Steady
N.C.
Right/Left shift
DB1,2, 3 input pins, 3 × 64-bit mode
N.C.
Steady
Left/Right shift
DB1,2, …6 input pins, RSDS mode
H or L
L or H
Steady
Right/Left shift
DB1,2, …6 input pins, RSDS mode
H or L
H or L
H or L
L or H
Steady
N.C.
Left /Right shift, DB1,2, …6 input pins,
2 × 3 × 32-bit mode
N.C.
Steady
N.C.
Left /Right shift, DB1,2, …6 input pins,
2 × 3 × 32-bit mode
N.C.
Steady
1. CLK2 is not used in LVCMOS operating mode and can be left “open” or “floating”.
14/32
STV7622
Table 8.
Truth tables
Truth table for power outputs
Qn(1)
/STB1
/STB2 (2)
BS1
BS2
/BLK
POC
Driver
output
X
X
X
X
X
L
X
all L
Output at Low level
X
X
X
X
X
H
L
all H
Output at High level
X
H
X
L
L
H
H
Qn
(3)
Data latched
X
H
L
L
H
H
H
Qn
(4)
Data latched
Qn
(5)
Data latched (RSDS)
Data latched
X
H
X
H
L
H
H
Note
Comments
X
H
X
H
H
H
H
Qn
(6)
L
L
X
L
L
H
H
L
(3)
Data copied
H
(3)
Data copied
L
(4)
Data copied (RSDS)
Data copied (RSDS)
H
L
L
L
X
H
L
L
L
H
H
H
H
H
H
L
H
L
H
H
H
H
(4)
L
L
X
H
L
H
H
L
(5)
Data copied
H
(5)
Data copied
L
(6)
Data copied
H
(6)
Data copied
H
L
H
L
L
L
X
X
X
H
H
H
L
H
H
H
H
H
H
H
H
1. Qn is the state of the shift register output (Figure 2). “X” means either High or Low (H or L).
2. /STB2 is not used in LVCMOS operating mode and can be left “open” or “floating”.
3. Qn + 1 = DB1, Qn + 2 = DB2, Qn + 3 = DB3, Qn + 4 = DB4, Qn + 5 = DB5, Qn + 6 = DB6; n = {0, 6, 12, 18, …186}.
4. RSDS mode: Qn + 1 = DB1, Qn + 1 = DB2, Qn + 2 = DB3, Qn + 2 = DB4, Qn + 3 = DB5, Qn + 3 = DB6; n = {0, 6, 12, 18, …186}.
5. Qn + 1 = DB1, Qn + 2 = DB2, Qn + 3 = DB3; n = {0, 3, 6, 9, …186, 189}.
6. Qn + 1 = DB1, Qn + 2 = DB2, Qn + 3 = DB3, Qn + 97 = DB4, Qn + 98 = DB5, Qn + 99 = DB6; n = {0, 3, 6, 9, …186, 189}.
15/32
Absolute maximum ratings
STV7622
7
Absolute maximum ratings
Table 9.
Absolute maximum ratings
Symbol
Parameter
Value
Units
Vdd
Digital supply range
-0.3, +7
V
Vcc
Analog supply range
-0.3, +7
V
Vpp
Driver supply range
-0.3, +90
V
Vin
Logic input voltage range
-0.3, Vcc+0.3
V
- 70/+35
mA
(1), (2), (3)
Ipout
Driver output current x
Idout
Diode output current(1), (2), (3)
-200/+300
mA
Vout
Output power voltage range
-0.3, +90
V
VESD
ESD susceptibility, Human Body Model (100pF
discharged through 1.5Kohms), on all except the VCC
pins(4)
2
KV
Tjmax
Maximum junction temperature
100
°C
-50, +150
°C
Tstg
Storage temperature range
1. Measurements done on one single output, x. The other outputs are either not used or are connected to output x. Assumes
junction temperature remains less than Tjmax during measurement.
2. All transient current measurements are made under conditions close to those encountered in a typical application (that is,
with duration of any output current spike always less than 300 ns).
3. These parameters are measured during STMicroelectronics’ internal qualification which includes temperature
characterization on standard as well as corner batches of the process. These parameters are not tested in production.
4. VCC pins withstand 1.3 KV.
16/32
STV7622
8
Electrical characteristics
Electrical characteristics
VCC = VDD = 5V, VPP = 70V, VSSP = VSSLOG = VSSSUB = 0V, TAMB = 25°C,
fCLK = 50 MHz, unless otherwise specified.
Table 10.
Electrical characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
4.50
5
5.5
V
10
µA
Supply
Vdd
Idd
Digital supply voltage
Digital supply current
(1)
Iddl
Digital Dynamic Supply Current (CLK1 freq =
Idd
Vcc
20MHz) (2)
-
15
20
mA
Digital Supply Current @ VIH = 2.0V
250
500
900
µA
Analog supply voltage
4.50
5
5.5
V
Icc_1
Analog supply current in standard transmission mode
-
1.1
2
mA
Icc_2
Analog supply current in RSDS mode (that is, with
BS1 = BS2 = L) and with DB1, DB3, DB5, CLK1 and
/STB1 less than DB2, DB4, DB6, CLK2 and /STB2,
respectively
-
5
10
mA
80
V
Vpp
DC power output supply voltage
15
Ipph-1
Power output supply current (steady outputs)
@ VCC = 0V
-
-
20
µA
Ipph-2
Power output supply current (steady outputs)
@ VCC = 5V and RS1 = RS2 = L
300
450
600
µA
OUT1 to OUT192
Vpouth
Power output high level (voltage drop versus Vpp)
@ Ipouth = -20mA and Vpp = 70V
2
3.5
5
V
Vpoutl
Power output low level
@ Ipoutl = +20mA
3
6
10
V
Vdouth
Output upper diode voltage drop
@ Idouth = +30mA (see Figure 9)
-
1
2
V
Vdoutl
Output lower diode voltage drop
@ Idoutl = -30mA (see Figure 9)
-2
-1
-
V
Standard Mode, TTL/LVCMOS inputs: CLK1, DIR, /STB1, POC, /BLK, BS1, BS2 and DB1 to DB6
VIH
High level input voltage
2.0
-
-
V
VIL
Low level input voltage
-
-
0.8
V
IIH
High level input current (VIH ≥ 2.0V)
-
-
5
µA
IIL
Low level input current (VIL = 0V)
-
-
5
µA
17/32
Electrical characteristics
Table 10.
STV7622
Electrical characteristics (continued)
Symbol
Parameter
Min.
Typ.
Max.
Units
100
400
600
mV
0.5 Vid
1.2
2.4 −
0.5 Vid
V
-
-
15
pF
RSDS Mode, inputs: CLK1, CLK2, /STB1, /STB2 and DB1 to DB6
Vid
Magnitude of differential input voltage
Vic
Common mode input range
Cin
Input capacitance (3)
1. For 5V CMOS input logic levels (0 or 5V)
2. All input data is switched at 10MHz rate.
3. Same for TTL and RSDS modes. This parameter is measured during qualification by ST Microelectronics which includes
temperature characterization on standard as well as corner batches of the process. This parameter is not tested in
production.
Figure 9.
Output test configuration
VPP
ON
VPP
OFF
Vdouth
OFF
Idouth (*)
OUTn
VSSP/VSSSUB
(*) Output sinking current is
considered as positive.
18/32
+
Idoutl (**)
ON
OUTn
Vdoutl
VSSP/VSSSUB
(**) Output sourcing current is
considered as negative.
-
STV7622
9
AC timing requirements
AC timing requirements
VCC = VDD = 4.5V to 5.5V, Tamb = -20°C to +85°C,
input signal edge maximum rise and fall times (tr, tf) = 3ns.
Table 11.
AC timing requirements
Symbol
Min.
Typ.
Max.
Units
Data clock period
16.7
-
-
ns
tWHCLK
Duration of clock pulse at high level
8.8
-
-
ns
tWLCLK
Duration of clock pulse at low level
8.8
-
-
ns
tCLK
Parameter
tSDAT
Input data set-up time before low-to-high clock transition
5
-
-
ns
tHDAT
Input data hold-time after low-to-high clock transition
5
-
-
ns
tHSTB
Strobe hold-time after low-to-high clock transition
5
-
-
ns
tSTB
Duration of strobe Low level
10
-
-
ns
tSSTB
Strobe set-up time before low-to-high clock transition
5
ns
19/32
AC timing characteristics
10
STV7622
AC timing characteristics
VCC = VDD = 5V, VPP = 70V, VSSP = VSSLOG = VSSSUB = 0V, Tamb = 25°C,
Fclk= 60MHz, VILmax = 0.2 × VCC, VIHmin = 0.8 × VCC.
Table 12.
AC timing characteristics
Symbol
Parameter
Min
Typ
Max
Units
Delay of power output change after CLK1/CLK2 transition
tPHL1
- high to low
-
35
100
ns
tPLH1
- low to high
-
30
100
ns
-
95
ns
-
-
95
ns
tPHL2
tPLH2
Delay of power output change after /STB1/STB2
transition
- high to low
- low to high
Delay of power output change after /BLK transition
tPHL3
- high to low
-
25
90
ns
tPLH3
- low to high
-
20
90
ns
tR-OUT
Power output rise time(1) (RS = “L” and RS2 = “L”)
90
120
150
ns
tR-OUT
Power output rise time(1) (RS = “H” and RS2 = “L”)
180
230
280
ns
tR-OUT
Power output rise time(1) (RS= “L” and RS2 = “H”)
320
400
480
ns
tR-OUT
Power output rise time(1) (RS = “H” and RS2 = “H”)
470
560
670
ns
tF-OUT
Power output fall time(2)
50
-
200
ns
tF-SLOW
Soft slope duration(3) (FS1 = “L” and FS2 = “L”)
8
10
12
ns
tF-SLOW
Soft slope duration(3) (FS1 = “H” and FS2 = “L”)
40
50
60
ns
tF-SLOW
Soft slope duration(3) (FS1 = “L” and FS2 = “H”)
80
100
120
ns
tF-SLOW
Soft slope duration(3) (FS1 = “H” and FS2 = “H”)
160
200
240
ns
1. tR-OUT is set externally by inputs RS1 and RS2.
2. Measurement made on one of the 192 power outputs with FS1 = “H” and FS2 = “L”. Load capacitor CL = 50pF, all other
power outputs Low.
3. tF-SLOW is set externally by inputs FS1 and FS2.
20/32
STV7622
AC timing characteristics
Figure 10. AC characteristic waveforms
tCLK
Standard mode
tWHCLK
CLK
tWLCLK
50%
50%
50%
tSDAT
50%
DB (input)
tSTB
/STB
tHDAT
50%
tHSTB
50%
50%
50%
tSSTB
tPHL2
OUT(n)
tPHL1
90%
90%
10%
10%
tPLH2
tPLH1
/BLK
50%
50%
tPHL3
tPLH3
90%
90%
OUTn
10%
10%
(See sections on output falling/rising edge)
tF-OUT
Differential mode
tR-OUT
tCLK
tWHCLK
tWLCLK
CLK1
50%
50%
50%
CLK2
tSDAT
tHDAT
DB1-3-5 (input)
50%
50%
DB2-4-6 (input)
tSTB
tHSTB
/STB1
50%
/STB2
50%
50%
tSSTB
21/32
Pad dimensions and positions (in µm)
11
STV7622
Pad dimensions and positions (in µm)
The reference (x=0, y=0) is the centre of the die. Output pad pitch is 76.5µm.
Pad placement coordinate values correspond to the center of each bump pad center. Pad
size is specified for bumping.
Table 13.
Pad placement and bump pad dimensions (in microns)
Lead pad name
Pad placements
Bump dimensions
X
Y
X
Y
OUT192
-7303.1
624.2
43.5
65.6
OUT191
-7226.6
624.2
43.5
65.6
OUT190
-7150.1
624.2
43.5
65.6
OUT189
-7073.6
624.2
43.5
65.6
OUT188
-6997.1
624.2
43.5
65.6
OUT187
-6920.6
624.2
43.5
65.6
OUT186
-6844.1
624.2
43.5
65.6
OUT185
-6767.6
624.2
43.5
65.6
OUT184
-6691.1
624.2
43.5
65.6
OUT183
-6614.6
624.2
43.5
65.6
OUT182
-6538.1
624.2
43.5
65.6
OUT181
-6461.6
624.2
43.5
65.6
OUT180
-6385.1
624.2
43.5
65.6
OUT179
-6308.6
624.2
43.5
65.6
OUT178
-6232.1
624.2
43.5
65.6
OUT177
-6155.6
624.2
43.5
65.6
OUT176
-6079.1
624.2
43.5
65.6
OUT175
-6002.6
624.2
43.5
65.6
OUT174
-5926.1
624.2
43.5
65.6
OUT173
-5849.6
624.2
43.5
65.6
OUT172
-5773.1
624.2
43.5
65.6
OUT171
-5696.6
624.2
43.5
65.6
OUT170
-5620.1
624.2
43.5
65.6
OUT169
-5543.6
624.2
43.5
65.6
OUT168
-5467.1
624.2
43.5
65.6
OUT167
-5390.6
624.2
43.5
65.6
OUT166
-5314.1
624.2
43.5
65.6
TOP SIDE from left to right
22/32
STV7622
Pad dimensions and positions (in µm)
Table 13.
Pad placement and bump pad dimensions (in microns) (continued)
Lead pad name
Pad placements
Bump dimensions
X
Y
X
Y
OUT165
-5237.6
624.2
43.5
65.6
OUT164
-5161.1
624.2
43.5
65.6
OUT163
-5084.6
624.21
43.5
65.6
OUT162
-5008.1
624.2
43.5
65.6
OUT161
-4931.6
624.2
43.5
65.6
OUT160
-4855.1
624.2
43.5
65.6
OUT159
-4778.6
624.2
43.5
65.6
OUT158
-4702.1
624.2
43.5
65.6
OUT157
-4625.6
624.2
43.5
65.6
OUT156
-4549.1
624.2
43.5
65.6
OUT155
-4472.6
624.2
43.5
65.6
OUT154
-4396.1
624.2
43.5
65.6
OUT153
-4319.6
624.2
43.5
65.6
OUT152
-4243.1
624.2
43.5
65.6
OUT151
-4166.6
624.2
43.5
65.6
OUT150
-4090.1
624.2
43.5
65.6
OUT149
-4013.6
624.2
43.5
65.6
OUT148
-3937.1
624.2
43.5
65.6
OUT147
-3860.6
624.2
43.5
65.6
OUT146
-3784.1
624.2
43.5
65.6
OUT145
-3707.6
624.2
43.5
65.6
OUT144
-3631.1
624.2
43.5
65.6
OUT143
-3554.6
624.2
43.5
65.6
OUT142
-3478.1
624.2
43.5
65.6
OUT141
-3401.6
624.2
43.5
65.6
OUT140
-3325.1
624.2
43.5
65.6
OUT139
-3248.6
624.2
43.5
65.6
OUT138
-3172.1
624.2
43.5
65.6
OUT137
-3095.6
624.2
43.5
65.6
OUT136
-3019.1
624.2
43.5
65.6
OUT135
-2942.6
624.2
43.5
65.6
OUT134
-2866.1
624.2
43.5
65.6
OUT133
-2789.6
624.2
43.5
65.6
23/32
Pad dimensions and positions (in µm)
Table 13.
STV7622
Pad placement and bump pad dimensions (in microns) (continued)
Lead pad name
24/32
Pad placements
Bump dimensions
X
Y
X
Y
OUT132
-2713.1
624.2
43.5
65.6
OUT131
-2636.6
624.2
43.5
65.6
OUT130
-2560.1
624.2
43.5
65.6
OUT129
-2483.6
624.2
43.5
65.6
OUT128
-2407.1
624.2
43.5
65.6
OUT127
-2330.6
624.2
43.5
65.6
OUT126
-2254.1
624.215
43.5
65.6
OUT125
-2177.6
624.2
43.5
65.6
OUT124
-2101.1
624.2
43.5
65.6
OUT123
-2024.6
624.2
43.5
65.6
OUT122
-1948.1
624.2
43.5
65.6
OUT121
-1871.6
624.2
43.5
65.6
OUT120
-1795.1
624.2
43.5
65.6
OUT119
-1718.6
624.2
43.5
65.6
OUT118
-1642.1
624.2
43.5
65.6
OUT117
-1565.6
624.2
43.5
65.6
OUT116
-1489.1
624.2
43.5
65.6
OUT115
-1412.6
624.2
43.5
65.6
OUT114
-1336.1
624.2
43.5
65.6
OUT113
-1259.6
624.2
43.5
65.6
OUT112
-1183.1
624.2
43.5
65.6
OUT111
-1106.6
624.2
43.5
65.6
OUT110
-1030.1
624.2
43.5
65.6
OUT109
-953.6
624.2
43.5
65.6
OUT108
-877.1
624.2
43.5
65.6
OUT107
-800.6
624.2
43.5
65.6
OUT106
-724.1
624.2
43.5
65.6
OUT105
-647.6
624.2
43.5
65.6
OUT104
-571.1
624.2
43.5
65.6
OUT103
-494.6
624.2
43.5
65.6
OUT102
-418.1
624.2
43.5
65.6
OUT101
-341.6
624.2
43.5
65.6
OUT100
-265.1
624.2
43.5
65.6
STV7622
Pad dimensions and positions (in µm)
Table 13.
Pad placement and bump pad dimensions (in microns) (continued)
Lead pad name
Pad placements
Bump dimensions
X
Y
X
Y
OUT99
-188.6
624.2
43.5
65.6
OUT98
-112.1
624.2
43.5
65.6
OUT97
-35.6
624.2
43.5
65.6
OUT96
40.9
624.2
43.5
65.6
OUT95
117.4
624.2
43.5
65.6
OUT94
193.9
624.2
43.5
65.6
OUT93
270.4
624.2
43.5
65.6
OUT92
346.9
624.2
43.5
65.6
OUT91
423.4
624.2
43.5
65.6
OUT90
499.9
624.2
43.5
65.6
OUT89
576.4
624.2
43.5
65.6
OUT88
652.9
624.2
43.5
65.6
OUT87
729.4
624.2
43.5
65.6
OUT86
805.9
624.2
43.5
65.6
OUT85
882.4
624.2
43.5
65.6
OUT84
958.9
624.2
43.5
65.6
OUT83
1035.4
624.2
43.5
65.6
OUT82
1111.9
624.2
43.5
65.6
OUT81
1188.4
624.2
43.5
65.6
OUT80
1264.9
624.2
43.5
65.6
OUT79
1341.4
624.2
43.5
65.6
OUT78
1417.9
624.2
43.5
65.6
OUT77
1494.4
624.2
43.5
65.6
OUT76
1570.9
624.2
43.5
65.6
OUT75
1647.4
624.2
43.5
65.6
OUT74
1723.9
624.2
43.5
65.6
OUT73
1800.4
624.2
43.5
65.6
OUT72
1876.9
624.2
43.5
65.6
OUT71
1953.4
624.2
43.5
65.6
OUT70
2029.9
624.2
43.5
65.6
OUT69
2106.4
624.2
43.5
65.6
OUT68
2182.9
624.2
43.5
65.6
OUT67
2259.4
624.2
43.5
65.6
25/32
Pad dimensions and positions (in µm)
Table 13.
STV7622
Pad placement and bump pad dimensions (in microns) (continued)
Lead pad name
26/32
Pad placements
Bump dimensions
X
Y
X
Y
OUT66
2335.8
624.2
43.5
65.6
OUT65
2412.3
624.2
43.5
65.6
OUT64
2488.9
624.2
43.5
65.6
OUT63
2565.4
624.2
43.5
65.6
OUT62
2641.9
624.2
43.5
65.6
OUT61
2718.4
624.2
43.5
65.6
OUT60
2794.9
624.2
43.5
65.6
OUT59
2871.4
624.2
43.5
65.6
OUT58
2947.9
624.2
43.5
65.6
OUT57
3024.4
624.2
43.5
65.6
OUT56
3100.9
624.2
43.5
65.6
OUT55
3177.4
624.2
43.5
65.6
OUT54
3253.9
624.2
43.5
65.6
OUT53
3330.4
624.2
43.5
65.6
OUT52
3406.9
624.2
43.5
65.6
OUT51
3483.4
624.2
43.5
65.6
OUT50
3559.9
624.2
43.5
65.6
OUT49
3636.4
624.2
43.5
65.6
OUT48
3712.9
624.2
43.5
65.6
OUT47
3789.4
624.2
43.5
65.6
OUT46
3865.9
624.2
43.5
65.6
OUT45
3942.4
624.2
43.5
65.6
OUT44
4018.9
624.2
43.5
65.6
OUT43
4095.4
624.2
43.5
65.6
OUT42
4171.9
624.2
43.5
65.6
OUT41
4248.4
624.2
43.5
65.6
OUT40
4324.9
624.2
43.5
65.6
OUT39
4401.4
624.2
43.5
65.6
OUT38
4477.9
624.2
43.5
65.6
OUT37
4554.4
624.2
43.5
65.6
OUT36
4630.9
624.2
43.5
65.6
OUT35
4707.4
624.2
43.5
65.6
OUT34
4783.9
624.2
43.5
65.6
STV7622
Pad dimensions and positions (in µm)
Table 13.
Pad placement and bump pad dimensions (in microns) (continued)
Lead pad name
Pad placements
Bump dimensions
X
Y
X
Y
OUT33
4860.4
624.2
43.5
65.6
OUT32
4936.9
624.2
43.5
65.6
OUT31
5013.4
624.2
43.5
65.6
OUT30
5089.9
624.2
43.5
65.6
OUT29
5166.4
624.2
43.5
65.6
OUT28
5242.9
624.2
43.5
65.6
OUT27
5319.4
624.2
43.5
65.6
OUT26
5395.9
624.2
43.5
65.6
OUT25
5472.4
624.2
43.5
65.6
OUT24
5548.9
624.2
43.5
65.6
OUT23
5625.4
624.2
43.5
65.6
OUT22
5701.9
624.2
43.5
65.6
OUT21
5778.4
624.2
43.5
65.6
OUT20
5854.9
624.2
43.5
65.6
OUT19
5931.4
624.2
43.5
65.6
OUT18
6007.9
624.2
43.5
65.6
OUT17
6084.4
624.2
43.5
65.6
OUT16
6160.9
624.2
43.5
65.6
OUT15
6237.4
624.2
43.5
65.6
OUT14
6313.9
624.2
43.5
65.6
OUT13
6390.4
624.2
43.5
65.6
OUT12
6466.9
624.2
43.5
65.6
OUT11
6543.4
624.2
43.5
65.6
OUT10
6619.9
624.2
43.5
65.6
OUT9
6696.4
624.2
43.5
65.6
OUT8
6772.9
624.2
43.5
65.6
OUT7
6849.4
624.2
43.5
65.6
OUT6
6925.9
624.2
43.5
65.6
OUT5
7002.4
624.2
43.5
65.6
OUT4
7078.9
624.2
43.5
65.6
OUT3
7155.4
624.2
43.5
65.6
OUT2
7231.9
624.2
43.5
65.6
OUT1
7308.4
624.2
43.5
65.6
27/32
Pad dimensions and positions (in µm)
Table 13.
STV7622
Pad placement and bump pad dimensions (in microns) (continued)
Lead pad name
Pad placements
Bump dimensions
X
Y
X
Y
VSSP4
7461.3
635.2
65.6
43.5
VSSP5
7473.2
560.3
65.6
43.5
VSSP6
7473.2
485.4
65.6
43.5
VPP4
7473.2
260.1
65.6
43.5
VPP5
7473.2
185.2
65.6
43.5
VPP6
7473.2
110.3
65.6
43.5
DUMMY
7473.2
35.5
65.6
43.5
VSSLOG2
7473.2
-39.4
65.6
43.5
VSSSUB2
7473.2
-114.3
65.6
43.5
VDD2
7473.2
-189.2
65.6
43.5
VCC2
7473.2
-555.2
65.6
43.5
DUMMY
7461.3
-633.5
65.6
43.5
DUMMY
6838.2
-622.5
43.5
65.6
DUMMY
6749.7
-622.5
43.5
65.6
DUMMY
6673.1
-622.5
43.5
65.6
DUMMY
6486.3
-622.5
43.5
65.6
DUMMY
6409.8
-622.5
43.5
65.6
DUMMY
6333.3
-622.5
43.5
65.6
DUMMY
6256.8
-622.5
43.5
65.6
DUMMY
6103.6
-622.5
43.5
65.6
TEST2
5928.9
-622.5
43.5
65.6
TEST1
5617.8
-622.5
43.5
65.6
VDD8
4783.9
-622.5
43.5
65.6
BS2
4634.4
-622.5
43.5
65.6
VSSLOG7
4466.3
-622.5
43.5
65.6
BS1
4325.9
-622.5
43.5
65.6
VDD7
4095.4
-622.5
43.5
65.6
DIR
3949.6
-622.5
43.5
65.6
VSSLOG6
3709.5
-622.5
43.5
65.6
FS1
3560.2
-622.5
43.5
65.6
VDD6
3327.0
-622.5
43.5
65.6
RIGHT SIDE from top to bottom
BOTTOM SIDE from right to left
28/32
STV7622
Pad dimensions and positions (in µm)
Table 13.
Pad placement and bump pad dimensions (in microns) (continued)
Lead pad name
Pad placements
Bump dimensions
X
Y
X
Y
FS2
3178.1
-622.5
43.5
65.6
VSSLOG5
2944.5
-622.5
43.5
65.6
RS2
2798.8
-622.5
43.5
65.6
VDD5
2629.4
-622.5
43.5
65.6
RS1
2486.6
-622.5
43.5
65.6
VSSLOG4
2314.1
-622.5
43.5
65.6
DUMMY
648.6
-622.5
43.5
65.6
VREF
117.6
-622.5
43.5
65.6
DUMMY
-271.1
-622.5
43.5
65.6
DUMMY
-424.1
-622.5
43.5
65.6
VDD4
-572.067
-622.5
43.5
65.6
POC
-870.5
-622.5
43.5
65.6
VSSLOG3
-1110.0
-622.5
43.5
65.6
BLK/
-1458.1
-622.5
43.5
65.6
VDD3
-1722.0
-622.5
43.5
65.6
CLK1
-1958.7
-622.5
43.5
65.6
CLK2
-2567.3
-622.5
43.5
65.6
STB1/
-3018.9
-622.5
43.5
65.6
STB2/
-3561.8
-622.5
43.5
65.6
DB1
-4021.4
-622.5
43.5
65.6
DB2
-4632.8
-622.5
43.5
65.6
DB3
-5015.9
-622.5
43.5
65.6
DB4
-5840.8
-622.5
43.5
65.6
DB5
-6114.5
-622.5
43.5
65.6
DB6
-7094.6
-622.5
43.5
65.6
29/32
Pad dimensions and positions (in µm)
Table 13.
STV7622
Pad placement and bump pad dimensions (in microns) (continued)
Lead pad name
Pad placements
Bump dimensions
X
Y
X
Y
VCC1
-7474.9
-555.2
65.6
43.5
VDD1
-7474.9
-189.2
65.6
43.5
VSSSUB1
-7474.9
-114.3
65.6
43.5
VSSLOG1
-7474.9
-39.4
65.6
43.5
DUMMY
-7474.9
35.5
65.6
43.5
VPP3
-7474.9
110.3
65.6
43.5
VPP2
-7474.9
185.2
65.6
43.5
VPP1
-7474.9
260.1
65.6
43.5
VSSP3
-7474.9
485.5
65.6
43.5
VSSP2
-7474.9
560.3
65.6
43.5
VSSP1
-7462.9
635.2
65.6
43.5
LEFT SIDE from bottom to top
30/32
STV7622
12
Tested wafer disclaimer
Tested wafer disclaimer
All wafers are tested and guaranteed to comply with this specification until the wafer sawing
stage, for a period of ninety (90) days from the delivery date.
Please remember that it is the customer’s responsibility to test and qualify their application
using the STMicroelectronics die. STMicroelectronics is ready to support customers when
qualifying the product.
13
Ordering information
Table 14. Order codes
Part number
STV7622/BMP
14
Description
Tested and usawn bump wafer (u = die)
Revision history
Table 15.
Document revision history
Date
Revision
29-May-2007
1
Changes
Initial release
31/32
STV7622
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