Micrel, Inc. 7GHz, 1:2 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION SY58011U ® Precision Edge SY58011U FEATURES Precision 1:2, 400mV CML fanout buffer Guaranteed AC performance over temperature/ voltage: • > 7GHz fMAX clock • < 60ps tr / tf times • < 250ps tpd • < 15ps max. skew Low jitter performance: • < 10psPP total jitter (clock) • < 1psRMS random jitter (data) • < 10psPP deterministic jitter (data) Accepts an input signal as low as 100mV Unique input termination and VT pin accepts DCcoupled and AC-coupled differential inputs: LVPECL, LVDS, and CML 50Ω source terminated CML outputs Power supply 2.5V ±5% and 3.3V ±10% Industrial temperature range: –40°C to +85°C Available in 16-pin (3mm × 3mm) MLF® package Precision Edge® DESCRIPTION The SY58011U is a 2.5V/3.3V precision, high-speed, fully differential 1:2 CML fanout buffer. Optimized to provide two identical output copies with less than 15ps of skew and less than 10ps(pk-pk) total jitter, the SY58011U can process clock signals as fast as 7GHz or data patterns up to 10.7Gbps. The differential input includes Micrel’s unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS, or CML differential signals, (AC-coupled or DC-coupled) as small as 100mV without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an on-board output reference voltage (VREF-AC) is provided to bias the VT pin. The outputs are compatible with 400mV typical swing into 50Ω loads, with extremely fast rise/fall times guaranteed to be less than 60ps. The SY58011U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (–40°C to +85°C). For applications that require LVPECL outputs, consider the SY58012U or SY58013U 1:2 fanout buffer with 800mV and 400mV output swing, respectively. The SY58011U is part of Micrel’s highspeed, Precision Edge™ product line. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. APPLICATIONS ■ ■ ■ ■ ■ All SONET and GigE clock distribution Fibre Channel clock and data distribution Backplanes Data distribution: OC-48, OC-48+FEC, XAUI High-end, low skew, multiprocessor synchronous clock distribution TYPICAL PERFORMANCE 2GHz Output FUNCTIONAL BLOCK DIAGRAM Output Swing (100mV/div.) VCC = 2.5V Q0 IN 50Ω /Q0 VT 50Ω /IN Q1 TIME (70ps/div.) /Q1 VREF-AC 2GHz with 100mV Input Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-020207 [email protected] or (408) 955-1690 Rev.: D 1 Amendment: /0 Issue Date: February 2007 SY58011U Micrel, Inc. GND VCC 16 GND VCC PACKAGE/ORDERING INFORMATION 15 14 13 Ordering Information(1) 2 11 /Q0 VREF-AC 3 10 /Q1 /IN 4 9 Q1 5 6 7 8 VCC Q0 VT GND 12 VCC 1 GND IN 16-Pin MLF® (MLF-16) Part Number Package Type Operating Range Package Marking Lead Finish SY58011UMI MLF-16 Industrial 011U Sn-Pb SY58011UMITR(2) MLF-16 Industrial 011U Sn-Pb SY58011UMG(3) MLF-16 Industrial 011U with Pb-Free bar-line indicator Pb-Free NiPdAu SY58011UMGTR(2, 3) MLF-16 Industrial 011U with Pb-Free bar-line indicator Pb-Free NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs. PIN DESCRIPTION Pin Number Pin Name 1, 4 IN, /IN Differential Input: This input pair is the signal to be buffered. Each pin of this pair internally terminates with 50Ω to the VT pin. Note that this input will default to an indeterminate state if left open. See “Input Interface Applications” section. 2 VT Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See “Input Interface Applications” section. 3 VREF-AC Reference Output Voltage: This output biases to VCC –1.2V. It is used when AC-coupling the inputs (IN, /IN). Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Maximum current source or sink is 0.5mA. See “Input Interface Applica tions” section. 5, 8, 13, 16 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC pins as possible. 6, 7, 14, 15 GND, (Exposed Pad) Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pin. 12, 11 9, 10 Q0, /Q0, Q1, /Q1 M9999-020207 [email protected] or (408) 955-1690 Pin Function CML Differential Output Pairs: Differential buffered output copy of the input signal. The output swing is typically 400mV. Unused output pairs may be left floating with no impact on jitter. See “CML Output Termination” section. 2 SY58011U Micrel, Inc. Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Power Supply Voltage (VCC) ....................... –0.5V to +4.0V Input Voltage (VIN) ......................................... –0.5V to VCC CML Output Voltage (VOUT) ........... VCC–1.0V to VCC+0.5V Current (VT) Source or sink current on VT pin ........................ ±100mA Input Current Source or sink current on IN, /IN .......................... ±50mA Current (VREF) Source or sink current on VREF-AC, Note 4 ........ ±1.5mA Lead Temperature Soldering, (20 seconds) .............. 260°C Storage Temperature Range (TSTORE) .... –65°C to +150°C Supply Voltage (VCC) ............................ +2.375V to +3.60V Operating Temperature Range (TA) ........... –40°C to +85°C Package Thermal Resistance, Note 3 MLF® (θJA) Still-Air ............................................................. 60°C/W 500lfpm ............................................................ 54°C/W MLF® (ψJB) .......................................................... 33°C/W DC ELECTRICAL CHARACTERISTICS(Note 5) TA= –40°C to +85°C Symbol Parameter Condition Min VCC Power Supply Voltage ICC Power Supply Current Max. VCC, no load VIH Input HIGH Voltage IN, /IN VIL Input LOW Voltage IN, /IN VIN Input Voltage Swing VDIFF_IN Differential Input Voltage Swing RIN Into VT Resistance VREF-AC Output Reference Voltage Typ Max Units 3.60 V 95 mA VCC–1.2 VCC V 0 VIH–0.1 V see Figure 1a. 0.1 1.7 V see Figure 1b. 0.2 3.4 V 2.375 75 40 50 60 Ω VCC –1.3 VCC –1.2 VCC –1.1 V 1.28 V IN to VT CML DC ELECTRICAL CHARACTERISTICS(Note 5) VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C; RL = 100Ω across each output pair, or equivalent, unless otherwise stated. Symbol Parameter Condition Min Typ VOH Output HIGH Voltage Q0, /Q0, Q1, /Q1 VOUT Output Voltage Swing Q0, /Q0, Q1, /Q1; see Figure 1a 325 400 mV VDIFF_OUT Differential Output Voltage Swing Q0, /Q0, Q1, /Q1; see Figure 1b 650 800 mV ROUT Output Source Impedance Q0, /Q0, Q1, /Q1 40 50 VCC –0.020 VCC –0.010 Max Units VCC V 60 Ω Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Thermal performance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential (gnd) on the pcb. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. M9999-020207 [email protected] or (408) 955-1690 3 SY58011U Micrel, Inc. AC ELECTRICAL CHARACTERISTICS (Note 7) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to +85°C; RL = 100Ω across each output pair, or equivalent, unless otherwise stated. Symbol Parameter Condition fMAX Maximum Operating Frequency Min NRZ Data VOUT ≥ 200mV Clock Typ Max Units 10.7 Gbps 7 8 GHz 100 170 250 ps 3 15 ps tpd Propagation Delay VIN ≥ 100mV tCHAN Channel-to-Channel Skew Note 8 tSKEW Part-to-Part Skew Note 9 100 ps tJITTER Data Random Jitter (RJ) Deterministic Jitter (DJ) Note 10 Note 11 1 10 psRMS psPP Cycle-to-Cycle Jitter Total Jitter (TJ) Note 12 Note 13 1 10 psRMS psPP 60 ps Clock tr, tf Output Rise/Fall Time 20% to 80% at full output swing 20 40 Notes: 7. High frequency AC electricals are guaranteed by design and characterization. 8. Skew is measured between outputs of the same bank under identical transitions. 9. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. RJ is measured with a K28.7 comma detect character pattern, measured at 10.7Gbps and 2.5Gbps/3.2Gbps. 11. DJ is measured at 10.7Gbps and 2.5Gbps/3.2Gbps with both K28.5 and 223–1 PRBS pattern 12. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output signal. 13. Total jitter definition: With an ideal clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. TIMING DIAGRAM /IN IN /Q Q tpd SINGLE-ENDED AND DIFFERENTIAL SWINGS VIN, VOUT (Typ. 400mV) VDIFF_IN, VDIFF_OUT (Typ. 800mV) Figure 1b. Differential Voltage Swing Figure 1a. Single-Ended Voltage Swing M9999-020207 [email protected] or (408) 955-1690 4 SY58011U Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, GND = 0, VIN = 100mV, TA = 25°C, unless otherwise stated. Frequency vs. Amplitude 10 WITHIN-DEVICE SKEW (ps) 400 350 300 250 200 150 12000 10000 8000 6000 0 0 4000 100 50 2000 AMPLITUDE (mV) 500 450 Within-Device Skew vs. Temperature 9 8 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) FREQUENCY (MHz) Propagation Delay vs. Input Voltage Swing Propagation Delay vs. Temperature PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 162 160 158 156 154 152 150 0 200 400 600 800 1000 INPUT VOLTAGE SWING (V) M9999-020207 [email protected] or (408) 955-1690 5 185 180 VIN ≥ 200mV 175 170 165 160 155 150 145 140 135 130 125 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) SY58011U Micrel, Inc. FUNCTIONAL CHARACTERISTICS VCC = 2.5V, GND = 0, VIN = 100mV, TA = 25°C, unless otherwise stated. 200MHz Output 2GHz Output Output Swing (100mV/div.) Output Swing (100mV/div.) VCC = 2.5V TIME (70ps/div.) TIME (600ps/div.) Output Swing (100mV/div.) 7GHz Output TIME (20ps/div.) M9999-020207 [email protected] or (408) 955-1690 6 SY58011U Micrel, Inc. INPUT STAGE VCC IN 50 VT 50 W W GND /IN Figure 2. Simplified Differential Input Buffer INPUT INTERFACE APPLICATIONS VCC VCC VCC VCC VCC VCC IN LVPECL IN IN /IN CML CML SY58011U /IN /IN SY58011U VT SY58011U 0.01 VT NC VT NC VREF-AC m F Rpd NC VREF-AC VREF-AC m 0.01 F Note: For VCC = 2.5V system, Rpd = 19 VCC Figure 3a. DC-Coupled CML Input Interface For VCC = 3.3V system, Rpd = 50 Figure 3b. AC-Coupled CML Input Interface (option: may connect VT to VCC) VCC VCC IN VCC VCC LVPECL /IN Rpd SY58011U Rpd IN LVDS /IN VT SY58011U VREF-AC m 0.01 F Note: VCC NC VT NC VREF-AC W for a 3.3V system W for a 2.5V system Rpd = 100 Rpd = 50 Figure 3d. AC-Coupled LVPECL Input Interface M9999-020207 [email protected] or (408) 955-1690 Figure 3e. LVDS Input Interface 7 Figure 3c. LVPECL Input Interface W W SY58011U Micrel, Inc. CML OUTPUT TERMINATION Figure 4 and Figure 5 illustrates how to terminate a CML output using both the AC-coupled and DC-coupled configuration. All outputs of the SY58011 are 50Ω with a 16mA current source. VCC VCC 50 W 50 W Q ZO = 50 50W W 100 50W Q 50W W /Q /Q ZO = 50 W 16mA 16mA 50W DC-bias per application GND GND Figure 4. CML DC-Coupled Termination Figure 5. CML AC-Coupled Termination RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY58011U 7GHz, 1:2 CML Fanout Buffer/Translator with Internal I/O Termination http://www.micrel.com/product-info/products/sy58011u.shtml SY58012U 5GHz, 1:2 LVPECL Fanout Buffer/Translator with Internal Input Termination http://www.micrel.com/product-info/products/sy58012u.shtml SY58013U 6GHz, 1:2 Fanout Buffer/Translator with 400mV LVPECL Outputs and Internal Input Termination http://www.micrel.com/product-info/products/sy58013u.shtml 16-MLF™ Manufacturing Guidelines Exposed Pad Application Note www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf HBW Solutions http://www.micrel.com/product-info/as/solutions.shtml M9999-020207 [email protected] or (408) 955-1690 8 SY58011U Micrel, Inc. 16-PIN MicroLeadFrame® (MLF-16) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-020207 [email protected] or (408) 955-1690 9